2 * Contains register definitions common to the Book E PowerPC
3 * specification. Notice that while the IBM-40x series of CPUs
4 * are not true Book E PowerPCs, they borrowed a number of features
5 * before Book E was finalized, and are included here as well. Unfortunatly,
6 * they sometimes used different locations than true Book E CPUs did.
9 #ifndef __ASM_PPC_REG_BOOKE_H__
10 #define __ASM_PPC_REG_BOOKE_H__
13 /* Device Control Registers */
14 void __mtdcr(int reg
, unsigned int val
);
15 unsigned int __mfdcr(int reg
);
17 ({unsigned int rval; \
18 if (__builtin_constant_p(rn)) \
19 asm volatile("mfdcr %0," __stringify(rn) \
25 #define mtdcr(rn, v) \
27 if (__builtin_constant_p(rn)) \
28 asm volatile("mtdcr " __stringify(rn) ",%0" \
34 /* R/W of indirect DCRs make use of standard naming conventions for DCRs */
35 #define mfdcri(base, reg) \
37 mtdcr(base ## _CFGADDR, base ## _ ## reg); \
38 mfdcr(base ## _CFGDATA); \
41 #define mtdcri(base, reg, data) \
43 mtdcr(base ## _CFGADDR, base ## _ ## reg); \
44 mtdcr(base ## _CFGDATA, data); \
47 /* Performance Monitor Registers */
48 #define mfpmr(rn) ({unsigned int rval; \
49 asm volatile("mfpmr %0," __stringify(rn) \
50 : "=r" (rval)); rval;})
51 #define mtpmr(rn, v) asm volatile("mtpmr " __stringify(rn) ",%0" : : "r" (v))
52 #endif /* __ASSEMBLY__ */
55 /* Machine State Register (MSR) Fields */
56 #define MSR_UCLE (1<<26) /* User-mode cache lock enable */
57 #define MSR_SPE (1<<25) /* Enable SPE */
58 #define MSR_DWE (1<<10) /* Debug Wait Enable */
59 #define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
60 #define MSR_IS MSR_IR /* Instruction Space */
61 #define MSR_DS MSR_DR /* Data Space */
62 #define MSR_PMM (1<<2) /* Performance monitor mark bit */
64 /* Default MSR for kernel mode. */
65 #if defined (CONFIG_40x)
66 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_IR|MSR_DR|MSR_CE|MSR_DE)
67 #elif defined(CONFIG_BOOKE)
68 #define MSR_KERNEL (MSR_ME|MSR_RI|MSR_CE|MSR_DE)
71 /* Special Purpose Registers (SPRNs)*/
72 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
73 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
74 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
75 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
76 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
77 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
78 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
79 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
80 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
81 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
82 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
83 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
84 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
85 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
86 #define SPRN_DVC1 0x13E /* Data Value Compare Register 1 */
87 #define SPRN_DVC2 0x13F /* Data Value Compare Register 2 */
88 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
89 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
90 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
91 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
92 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
93 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
94 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
95 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
96 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
97 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
98 #define SPRN_IVOR10 0x19A /* Interrupt Vector Offset Register 10 */
99 #define SPRN_IVOR11 0x19B /* Interrupt Vector Offset Register 11 */
100 #define SPRN_IVOR12 0x19C /* Interrupt Vector Offset Register 12 */
101 #define SPRN_IVOR13 0x19D /* Interrupt Vector Offset Register 13 */
102 #define SPRN_IVOR14 0x19E /* Interrupt Vector Offset Register 14 */
103 #define SPRN_IVOR15 0x19F /* Interrupt Vector Offset Register 15 */
104 #define SPRN_SPEFSCR 0x200 /* SPE & Embedded FP Status & Control */
105 #define SPRN_BBEAR 0x201 /* Branch Buffer Entry Address Register */
106 #define SPRN_BBTAR 0x202 /* Branch Buffer Target Address Register */
107 #define SPRN_IVOR32 0x210 /* Interrupt Vector Offset Register 32 */
108 #define SPRN_IVOR33 0x211 /* Interrupt Vector Offset Register 33 */
109 #define SPRN_IVOR34 0x212 /* Interrupt Vector Offset Register 34 */
110 #define SPRN_IVOR35 0x213 /* Interrupt Vector Offset Register 35 */
111 #define SPRN_MCSRR0 0x23A /* Machine Check Save and Restore Register 0 */
112 #define SPRN_MCSRR1 0x23B /* Machine Check Save and Restore Register 1 */
113 #define SPRN_MCSR 0x23C /* Machine Check Status Register */
114 #define SPRN_MCAR 0x23D /* Machine Check Address Register */
115 #define SPRN_MAS0 0x270 /* MMU Assist Register 0 */
116 #define SPRN_MAS1 0x271 /* MMU Assist Register 1 */
117 #define SPRN_MAS2 0x272 /* MMU Assist Register 2 */
118 #define SPRN_MAS3 0x273 /* MMU Assist Register 3 */
119 #define SPRN_MAS4 0x274 /* MMU Assist Register 4 */
120 #define SPRN_MAS5 0x275 /* MMU Assist Register 5 */
121 #define SPRN_MAS6 0x276 /* MMU Assist Register 6 */
122 #define SPRN_PID1 0x279 /* Process ID Register 1 */
123 #define SPRN_PID2 0x27A /* Process ID Register 2 */
124 #define SPRN_TLB0CFG 0x2B0 /* TLB 0 Config Register */
125 #define SPRN_TLB1CFG 0x2B1 /* TLB 1 Config Register */
126 #define SPRN_CCR1 0x378 /* Core Configuration Register 1 */
127 #define SPRN_ZPR 0x3B0 /* Zone Protection Register (40x) */
128 #define SPRN_MMUCR 0x3B2 /* MMU Control Register */
129 #define SPRN_CCR0 0x3B3 /* Core Configuration Register 0 */
130 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
131 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
132 #define SPRN_SLER 0x3BB /* Little-endian real mode */
133 #define SPRN_SU0R 0x3BC /* "User 0" real mode (40x) */
134 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
135 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
136 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
137 #define SPRN_L1CSR0 0x3F2 /* L1 Cache Control and Status Register 0 */
138 #define SPRN_L1CSR1 0x3F3 /* L1 Cache Control and Status Register 1 */
139 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
140 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
141 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
142 #define SPRN_SVR 0x3FF /* System Version Register */
145 * SPRs which have conflicting definitions on true Book E versus classic,
149 #define SPRN_PID 0x030 /* Process ID */
150 #define SPRN_PID0 SPRN_PID/* Process ID Register 0 */
151 #define SPRN_CSRR0 0x03A /* Critical Save and Restore Register 0 */
152 #define SPRN_CSRR1 0x03B /* Critical Save and Restore Register 1 */
153 #define SPRN_DEAR 0x03D /* Data Error Address Register */
154 #define SPRN_ESR 0x03E /* Exception Syndrome Register */
155 #define SPRN_PIR 0x11E /* Processor Identification Register */
156 #define SPRN_DBSR 0x130 /* Debug Status Register */
157 #define SPRN_DBCR0 0x134 /* Debug Control Register 0 */
158 #define SPRN_DBCR1 0x135 /* Debug Control Register 1 */
159 #define SPRN_IAC1 0x138 /* Instruction Address Compare 1 */
160 #define SPRN_IAC2 0x139 /* Instruction Address Compare 2 */
161 #define SPRN_DAC1 0x13C /* Data Address Compare 1 */
162 #define SPRN_DAC2 0x13D /* Data Address Compare 2 */
163 #define SPRN_TSR 0x150 /* Timer Status Register */
164 #define SPRN_TCR 0x154 /* Timer Control Register */
167 #define SPRN_PID 0x3B1 /* Process ID */
168 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
169 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
170 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
171 #define SPRN_TSR 0x3D8 /* Timer Status Register */
172 #define SPRN_TCR 0x3DA /* Timer Control Register */
173 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
174 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
175 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
176 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
177 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
178 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
179 #define SPRN_CSRR0 SPRN_SRR2 /* Critical Save and Restore Register 0 */
180 #define SPRN_CSRR1 SPRN_SRR3 /* Critical Save and Restore Register 1 */
183 /* Bit definitions for CCR1. */
184 #define CCR1_TCS 0x00000080 /* Timer Clock Select */
186 /* Bit definitions for the MCSR. */
188 #define MCSR_MCS 0x80000000 /* Machine Check Summary */
189 #define MCSR_IB 0x40000000 /* Instruction PLB Error */
190 #define MCSR_DRB 0x20000000 /* Data Read PLB Error */
191 #define MCSR_DWB 0x10000000 /* Data Write PLB Error */
192 #define MCSR_TLBP 0x08000000 /* TLB Parity Error */
193 #define MCSR_ICP 0x04000000 /* I-Cache Parity Error */
194 #define MCSR_DCSP 0x02000000 /* D-Cache Search Parity Error */
195 #define MCSR_DCFP 0x01000000 /* D-Cache Flush Parity Error */
196 #define MCSR_IMPE 0x00800000 /* Imprecise Machine Check Exception */
199 #define MCSR_MCP 0x80000000UL /* Machine Check Input Pin */
200 #define MCSR_ICPERR 0x40000000UL /* I-Cache Parity Error */
201 #define MCSR_DCP_PERR 0x20000000UL /* D-Cache Push Parity Error */
202 #define MCSR_DCPERR 0x10000000UL /* D-Cache Parity Error */
203 #define MCSR_GL_CI 0x00010000UL /* Guarded Load or Cache-Inhibited stwcx. */
204 #define MCSR_BUS_IAERR 0x00000080UL /* Instruction Address Error */
205 #define MCSR_BUS_RAERR 0x00000040UL /* Read Address Error */
206 #define MCSR_BUS_WAERR 0x00000020UL /* Write Address Error */
207 #define MCSR_BUS_IBERR 0x00000010UL /* Instruction Data Error */
208 #define MCSR_BUS_RBERR 0x00000008UL /* Read Data Bus Error */
209 #define MCSR_BUS_WBERR 0x00000004UL /* Write Data Bus Error */
210 #define MCSR_BUS_IPERR 0x00000002UL /* Instruction parity Error */
211 #define MCSR_BUS_RPERR 0x00000001UL /* Read parity Error */
214 /* Bit definitions for the DBSR. */
216 * DBSR bits which have conflicting definitions on true Book E versus IBM 40x.
219 #define DBSR_IC 0x08000000 /* Instruction Completion */
220 #define DBSR_BT 0x04000000 /* Branch Taken */
221 #define DBSR_TIE 0x01000000 /* Trap Instruction Event */
222 #define DBSR_IAC1 0x00800000 /* Instr Address Compare 1 Event */
223 #define DBSR_IAC2 0x00400000 /* Instr Address Compare 2 Event */
224 #define DBSR_IAC3 0x00200000 /* Instr Address Compare 3 Event */
225 #define DBSR_IAC4 0x00100000 /* Instr Address Compare 4 Event */
226 #define DBSR_DAC1R 0x00080000 /* Data Addr Compare 1 Read Event */
227 #define DBSR_DAC1W 0x00040000 /* Data Addr Compare 1 Write Event */
228 #define DBSR_DAC2R 0x00020000 /* Data Addr Compare 2 Read Event */
229 #define DBSR_DAC2W 0x00010000 /* Data Addr Compare 2 Write Event */
232 #define DBSR_IC 0x80000000 /* Instruction Completion */
233 #define DBSR_BT 0x40000000 /* Branch taken */
234 #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
235 #define DBSR_IAC1 0x00800000 /* Instruction Address Compare 1 Event */
236 #define DBSR_IAC2 0x00400000 /* Instruction Address Compare 2 Event */
237 #define DBSR_IAC3 0x00200000 /* Instruction Address Compare 3 Event */
238 #define DBSR_IAC4 0x00100000 /* Instruction Address Compare 4 Event */
239 #define DBSR_DAC1R 0x00080000 /* Data Address Compare 1 Read Event */
240 #define DBSR_DAC1W 0x00040000 /* Data Address Compare 1 Write Event */
241 #define DBSR_DAC2R 0x00020000 /* Data Address Compare 2 Read Event */
242 #define DBSR_DAC2W 0x00010000 /* Data Address Compare 2 Write Event */
245 /* Bit definitions related to the ESR. */
246 #define ESR_MCI 0x80000000 /* Machine Check - Instruction */
247 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
248 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
249 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
250 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
251 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
252 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
253 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
254 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
255 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
256 #define ESR_ST 0x00800000 /* Store Operation */
257 #define ESR_DLK 0x00200000 /* Data Cache Locking */
258 #define ESR_ILK 0x00100000 /* Instr. Cache Locking */
259 #define ESR_BO 0x00020000 /* Byte Ordering */
261 /* Bit definitions related to the DBCR0. */
262 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
263 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
264 #define DBCR0_RST 0x30000000 /* all the bits in the RST field */
265 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
266 #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
267 #define DBCR0_RST_CORE 0x10000000 /* Core Reset */
268 #define DBCR0_RST_NONE 0x00000000 /* No Reset */
269 #define DBCR0_IC 0x08000000 /* Instruction Completion */
270 #define DBCR0_BT 0x04000000 /* Branch Taken */
271 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */
272 #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
273 #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
274 #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
275 #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
276 #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
277 #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
278 #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
279 #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
280 #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
281 #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
282 #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
283 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
285 /* Bit definitions related to the TCR. */
286 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
287 #define TCR_WP_MASK TCR_WP(3)
288 #define WP_2_17 0 /* 2^17 clocks */
289 #define WP_2_21 1 /* 2^21 clocks */
290 #define WP_2_25 2 /* 2^25 clocks */
291 #define WP_2_29 3 /* 2^29 clocks */
292 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
293 #define TCR_WRC_MASK TCR_WRC(3)
294 #define WRC_NONE 0 /* No reset will occur */
295 #define WRC_CORE 1 /* Core reset will occur */
296 #define WRC_CHIP 2 /* Chip reset will occur */
297 #define WRC_SYSTEM 3 /* System reset will occur */
298 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
299 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
300 #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
301 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
302 #define TCR_FP_MASK TCR_FP(3)
303 #define FP_2_9 0 /* 2^9 clocks */
304 #define FP_2_13 1 /* 2^13 clocks */
305 #define FP_2_17 2 /* 2^17 clocks */
306 #define FP_2_21 3 /* 2^21 clocks */
307 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
308 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
310 /* Bit definitions for the TSR. */
311 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
312 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
313 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
314 #define WRS_NONE 0 /* No WDT reset occurred */
315 #define WRS_CORE 1 /* WDT forced core reset */
316 #define WRS_CHIP 2 /* WDT forced chip reset */
317 #define WRS_SYSTEM 3 /* WDT forced system reset */
318 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
319 #define TSR_DIS TSR_PIS /* DEC Interrupt Status */
320 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
322 /* Bit definitions for the DCCR. */
323 #define DCCR_NOCACHE 0 /* Noncacheable */
324 #define DCCR_CACHE 1 /* Cacheable */
326 /* Bit definitions for DCWR. */
327 #define DCWR_COPY 0 /* Copy-back */
328 #define DCWR_WRITE 1 /* Write-through */
330 /* Bit definitions for ICCR. */
331 #define ICCR_NOCACHE 0 /* Noncacheable */
332 #define ICCR_CACHE 1 /* Cacheable */
334 /* Bit definitions for L1CSR0. */
335 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
336 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
338 /* Bit definitions for L1CSR0. */
339 #define L1CSR1_ICLFR 0x00000100 /* Instr Cache Lock Bits Flash Reset */
340 #define L1CSR1_ICFI 0x00000002 /* Instr Cache Flash Invalidate */
341 #define L1CSR1_ICE 0x00000001 /* Instr Cache Enable */
343 /* Bit definitions for SGR. */
344 #define SGR_NORMAL 0 /* Speculative fetching allowed. */
345 #define SGR_GUARDED 1 /* Speculative fetching disallowed. */
347 /* Bit definitions for SPEFSCR. */
348 #define SPEFSCR_SOVH 0x80000000 /* Summary integer overflow high */
349 #define SPEFSCR_OVH 0x40000000 /* Integer overflow high */
350 #define SPEFSCR_FGH 0x20000000 /* Embedded FP guard bit high */
351 #define SPEFSCR_FXH 0x10000000 /* Embedded FP sticky bit high */
352 #define SPEFSCR_FINVH 0x08000000 /* Embedded FP invalid operation high */
353 #define SPEFSCR_FDBZH 0x04000000 /* Embedded FP div by zero high */
354 #define SPEFSCR_FUNFH 0x02000000 /* Embedded FP underflow high */
355 #define SPEFSCR_FOVFH 0x01000000 /* Embedded FP overflow high */
356 #define SPEFSCR_FINXS 0x00200000 /* Embedded FP inexact sticky */
357 #define SPEFSCR_FINVS 0x00100000 /* Embedded FP invalid op. sticky */
358 #define SPEFSCR_FDBZS 0x00080000 /* Embedded FP div by zero sticky */
359 #define SPEFSCR_FUNFS 0x00040000 /* Embedded FP underflow sticky */
360 #define SPEFSCR_FOVFS 0x00020000 /* Embedded FP overflow sticky */
361 #define SPEFSCR_MODE 0x00010000 /* Embedded FP mode */
362 #define SPEFSCR_SOV 0x00008000 /* Integer summary overflow */
363 #define SPEFSCR_OV 0x00004000 /* Integer overflow */
364 #define SPEFSCR_FG 0x00002000 /* Embedded FP guard bit */
365 #define SPEFSCR_FX 0x00001000 /* Embedded FP sticky bit */
366 #define SPEFSCR_FINV 0x00000800 /* Embedded FP invalid operation */
367 #define SPEFSCR_FDBZ 0x00000400 /* Embedded FP div by zero */
368 #define SPEFSCR_FUNF 0x00000200 /* Embedded FP underflow */
369 #define SPEFSCR_FOVF 0x00000100 /* Embedded FP overflow */
370 #define SPEFSCR_FINXE 0x00000040 /* Embedded FP inexact enable */
371 #define SPEFSCR_FINVE 0x00000020 /* Embedded FP invalid op. enable */
372 #define SPEFSCR_FDBZE 0x00000010 /* Embedded FP div by zero enable */
373 #define SPEFSCR_FUNFE 0x00000008 /* Embedded FP underflow enable */
374 #define SPEFSCR_FOVFE 0x00000004 /* Embedded FP overflow enable */
375 #define SPEFSCR_FRMC 0x00000003 /* Embedded FP rounding mode control */
377 /* Short-hand for various SPRs. */
379 #define CSRR0 SPRN_CSRR0 /* Critical Save and Restore Register 0 */
380 #define CSRR1 SPRN_CSRR1 /* Critical Save and Restore Register 1 */
382 #define CSRR0 SPRN_SRR2 /* Logically and functionally equivalent. */
383 #define CSRR1 SPRN_SRR3 /* Logically and functionally equivalent. */
385 #define MCSRR0 SPRN_MCSRR0 /* Machine Check Save and Restore Register 0 */
386 #define MCSRR1 SPRN_MCSRR1 /* Machine Check Save and Restore Register 1 */
387 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
388 #define SPRG4R SPRN_SPRG4R /* Supervisor Private Registers */
389 #define SPRG5R SPRN_SPRG5R
390 #define SPRG6R SPRN_SPRG6R
391 #define SPRG7R SPRN_SPRG7R
392 #define SPRG4W SPRN_SPRG4W
393 #define SPRG5W SPRN_SPRG5W
394 #define SPRG6W SPRN_SPRG6W
395 #define SPRG7W SPRN_SPRG7W
398 * The IBM-403 is an even more odd special case, as it is much
399 * older than the IBM-405 series. We put these down here incase someone
400 * wishes to support these machines again.
403 /* Special Purpose Registers (SPRNs)*/
404 #define SPRN_TBHU 0x3CC /* Time Base High User-mode */
405 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode */
406 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
407 #define SPRN_TBHI 0x3DC /* Time Base High */
408 #define SPRN_TBLO 0x3DD /* Time Base Low */
409 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
410 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
411 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
412 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
413 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
416 /* Bit definitions for the DBCR. */
417 #define DBCR_EDM DBCR0_EDM
418 #define DBCR_IDM DBCR0_IDM
419 #define DBCR_RST(x) (((x) & 0x3) << 28)
420 #define DBCR_RST_NONE 0
421 #define DBCR_RST_CORE 1
422 #define DBCR_RST_CHIP 2
423 #define DBCR_RST_SYSTEM 3
424 #define DBCR_IC DBCR0_IC /* Instruction Completion Debug Evnt */
425 #define DBCR_BT DBCR0_BT /* Branch Taken Debug Event */
426 #define DBCR_EDE DBCR0_EDE /* Exception Debug Event */
427 #define DBCR_TDE DBCR0_TDE /* TRAP Debug Event */
428 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
429 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
430 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
431 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
432 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
433 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
434 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
439 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
440 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
441 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
442 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
443 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
444 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
445 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
446 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
447 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
448 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
450 #endif /* __ASM_PPC_REG_BOOKE_H__ */
451 #endif /* __KERNEL__ */
