| blob | bc831c367c6a5333649d5b05ea18c2d4b8146b58 |
1 /*
2 *
3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1k CPU.
5 *
6 * Copyright 2004 Embedded Edge, LLC
7 * dan@embeddededge.com
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
15 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
17 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
20 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
21 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
24 *
25 * You should have received a copy of the GNU General Public License along
26 * with this program; if not, write to the Free Software Foundation, Inc.,
27 * 675 Mass Ave, Cambridge, MA 02139, USA.
28 */
30 /* Specifics for the Au1xxx Programmable Serial Controllers, first
31 * seen in the AU1550 part.
32 */
33 #ifndef _AU1000_PSC_H_
34 #define _AU1000_PSC_H_
36 /* The PSC base addresses.
37 */
38 #define PSC_BASE0 0xb1a00000
39 #define PSC_BASE1 0xb1b00000
40 #define PSC_BASE2 0xb0a00000
41 #define PSC_BASE3 0xb0d00000
43 /* These should be defined in a board specific file!
44 */
45 #ifdef CONFIG_MIPS_PB1550
46 #define SPI_PSC_BASE PSC_BASE0
47 #define AC97_PSC_BASE PSC_BASE1
48 #define SMBUS_PSC_BASE PSC_BASE2
49 #endif
50 #ifdef CONFIG_MIPS_DB1550
51 #define SPI_PSC_BASE PSC_BASE0
52 #define AC97_PSC_BASE PSC_BASE1
53 #define SMBUS_PSC_BASE PSC_BASE2
54 #endif
57 /* The PSC select and control registers are common to
58 * all protocols.
59 */
60 #define PSC_SEL_OFFSET 0x00000000
61 #define PSC_CTRL_OFFSET 0x00000004
63 #define PSC_SEL_CLK_MASK (3 << 4)
64 #define PSC_SEL_CLK_INTCLK (0 << 4)
65 #define PSC_SEL_CLK_EXTCLK (1 << 4)
66 #define PSC_SEL_CLK_SERCLK (2 << 4)
68 #define PSC_SEL_PS_MASK 0x00000007
69 #define PSC_SEL_PS_DISABLED (0)
70 #define PSC_SEL_PS_SPIMODE (2)
71 #define PSC_SEL_PS_I2SMODE (3)
72 #define PSC_SEL_PS_AC97MODE (4)
73 #define PSC_SEL_PS_SMBUSMODE (5)
75 #define PSC_CTRL_DISABLE (0)
76 #define PSC_CTRL_SUSPEND (2)
77 #define PSC_CTRL_ENABLE (3)
79 /* AC97 Registers.
80 */
81 #define PSC_AC97CFG_OFFSET 0x00000008
82 #define PSC_AC97MSK_OFFSET 0x0000000c
83 #define PSC_AC97PCR_OFFSET 0x00000010
84 #define PSC_AC97STAT_OFFSET 0x00000014
85 #define PSC_AC97EVNT_OFFSET 0x00000018
86 #define PSC_AC97TXRX_OFFSET 0x0000001c
87 #define PSC_AC97CDC_OFFSET 0x00000020
88 #define PSC_AC97RST_OFFSET 0x00000024
89 #define PSC_AC97GPO_OFFSET 0x00000028
90 #define PSC_AC97GPI_OFFSET 0x0000002c
92 #define AC97_PSC_SEL (AC97_PSC_BASE + PSC_SEL_OFFSET)
93 #define AC97_PSC_CTRL (AC97_PSC_BASE + PSC_CTRL_OFFSET)
94 #define PSC_AC97CFG (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
95 #define PSC_AC97MSK (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
96 #define PSC_AC97PCR (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
97 #define PSC_AC97STAT (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
98 #define PSC_AC97EVNT (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
99 #define PSC_AC97TXRX (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
100 #define PSC_AC97CDC (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
101 #define PSC_AC97RST (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
102 #define PSC_AC97GPO (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
103 #define PSC_AC97GPI (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
105 /* AC97 Config Register.
106 */
107 #define PSC_AC97CFG_RT_MASK (3 << 30)
108 #define PSC_AC97CFG_RT_FIFO1 (0 << 30)
109 #define PSC_AC97CFG_RT_FIFO2 (1 << 30)
110 #define PSC_AC97CFG_RT_FIFO4 (2 << 30)
111 #define PSC_AC97CFG_RT_FIFO8 (3 << 30)
113 #define PSC_AC97CFG_TT_MASK (3 << 28)
114 #define PSC_AC97CFG_TT_FIFO1 (0 << 28)
115 #define PSC_AC97CFG_TT_FIFO2 (1 << 28)
116 #define PSC_AC97CFG_TT_FIFO4 (2 << 28)
117 #define PSC_AC97CFG_TT_FIFO8 (3 << 28)
119 #define PSC_AC97CFG_DD_DISABLE (1 << 27)
120 #define PSC_AC97CFG_DE_ENABLE (1 << 26)
121 #define PSC_AC97CFG_SE_ENABLE (1 << 25)
123 #define PSC_AC97CFG_LEN_MASK (0xf << 21)
124 #define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
125 #define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
126 #define PSC_AC97CFG_GE_ENABLE (1)
128 /* Enable slots 3-12.
129 */
130 #define PSC_AC97CFG_TXSLOT_ENA(x) (1 << (((x) - 3) + 11))
131 #define PSC_AC97CFG_RXSLOT_ENA(x) (1 << (((x) - 3) + 1))
133 /* The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
134 * The only sensible numbers are 7, 9, or possibly 11. Nah, just do the
135 * arithmetic in the macro.
136 */
137 #define PSC_AC97CFG_SET_LEN(x) (((((x)-2)/2) & 0xf) << 21)
138 #define PSC_AC97CFG_GET_LEN(x) (((((x) >> 21) & 0xf) * 2) + 2)
140 /* AC97 Mask Register.
141 */
142 #define PSC_AC97MSK_GR (1 << 25)
143 #define PSC_AC97MSK_CD (1 << 24)
144 #define PSC_AC97MSK_RR (1 << 13)
145 #define PSC_AC97MSK_RO (1 << 12)
146 #define PSC_AC97MSK_RU (1 << 11)
147 #define PSC_AC97MSK_TR (1 << 10)
148 #define PSC_AC97MSK_TO (1 << 9)
149 #define PSC_AC97MSK_TU (1 << 8)
150 #define PSC_AC97MSK_RD (1 << 5)
151 #define PSC_AC97MSK_TD (1 << 4)
152 #define PSC_AC97MSK_ALLMASK (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
153 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
154 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
155 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
156 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
158 /* AC97 Protocol Control Register.
159 */
160 #define PSC_AC97PCR_RC (1 << 6)
161 #define PSC_AC97PCR_RP (1 << 5)
162 #define PSC_AC97PCR_RS (1 << 4)
163 #define PSC_AC97PCR_TC (1 << 2)
164 #define PSC_AC97PCR_TP (1 << 1)
165 #define PSC_AC97PCR_TS (1 << 0)
167 /* AC97 Status register (read only).
168 */
169 #define PSC_AC97STAT_CB (1 << 26)
170 #define PSC_AC97STAT_CP (1 << 25)
171 #define PSC_AC97STAT_CR (1 << 24)
172 #define PSC_AC97STAT_RF (1 << 13)
173 #define PSC_AC97STAT_RE (1 << 12)
174 #define PSC_AC97STAT_RR (1 << 11)
175 #define PSC_AC97STAT_TF (1 << 10)
176 #define PSC_AC97STAT_TE (1 << 9)
177 #define PSC_AC97STAT_TR (1 << 8)
178 #define PSC_AC97STAT_RB (1 << 5)
179 #define PSC_AC97STAT_TB (1 << 4)
180 #define PSC_AC97STAT_DI (1 << 2)
181 #define PSC_AC97STAT_DR (1 << 1)
182 #define PSC_AC97STAT_SR (1 << 0)
184 /* AC97 Event Register.
185 */
186 #define PSC_AC97EVNT_GR (1 << 25)
187 #define PSC_AC97EVNT_CD (1 << 24)
188 #define PSC_AC97EVNT_RR (1 << 13)
189 #define PSC_AC97EVNT_RO (1 << 12)
190 #define PSC_AC97EVNT_RU (1 << 11)
191 #define PSC_AC97EVNT_TR (1 << 10)
192 #define PSC_AC97EVNT_TO (1 << 9)
193 #define PSC_AC97EVNT_TU (1 << 8)
194 #define PSC_AC97EVNT_RD (1 << 5)
195 #define PSC_AC97EVNT_TD (1 << 4)
197 /* CODEC Command Register.
198 */
199 #define PSC_AC97CDC_RD (1 << 25)
200 #define PSC_AC97CDC_ID_MASK (3 << 23)
201 #define PSC_AC97CDC_INDX_MASK (0x7f << 16)
202 #define PSC_AC97CDC_ID(x) (((x) & 0x3) << 23)
203 #define PSC_AC97CDC_INDX(x) (((x) & 0x7f) << 16)
205 /* AC97 Reset Control Register.
206 */
207 #define PSC_AC97RST_RST (1 << 1)
208 #define PSC_AC97RST_SNC (1 << 0)