include/asm-mips/mach-au1x00/au1xxx_dbdma.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *      Include file for Alchemy Semiconductor's Au1550 Descriptor
   5  *      Based DMA Controller.
   6  *
   7  * Copyright 2004 Embedded Edge, LLC
   8  *      dan@embeddededge.com
   9  *
  10  *  This program is free software; you can redistribute  it and/or modify it
  11  *  under  the terms of  the GNU General  Public License as published by the
  12  *  Free Software Foundation;  either version 2 of the  License, or (at your
  13  *  option) any later version.
  14  *
  15  *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
  16  *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
  17  *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
  18  *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
  19  *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  20  *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
  21  *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  22  *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
  23  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  24  *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  *  You should have received a copy of the  GNU General Public License along
  27  *  with this program; if not, write  to the Free Software Foundation, Inc.,
  28  *  675 Mass Ave, Cambridge, MA 02139, USA.
  29  */
  30
  31 /* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
  32  * seen in the AU1550 part.
  33  */
  34 #ifndef _AU1000_DBDMA_H_
  35 #define _AU1000_DBDMA_H_
  36
  37 #ifndef _LANGUAGE_ASSEMBLY
  38
  39 /* The DMA base addresses.
  40  * The Channels are every 256 bytes (0x0100) from the channel 0 base.
  41  * Interrupt status/enable is bits 15:0 for channels 15 to zero.
  42  */
  43 #define DDMA_GLOBAL_BASE        0xb4003000
  44 #define DDMA_CHANNEL_BASE       0xb4002000
  45
  46 typedef struct dbdma_global {
  47         u32     ddma_config;
  48         u32     ddma_intstat;
  49         u32     ddma_throttle;
  50         u32     ddma_inten;
  51 } dbdma_global_t;
  52
  53 /* General Configuration.
  54 */
  55 #define DDMA_CONFIG_AF          (1 << 2)
  56 #define DDMA_CONFIG_AH          (1 << 1)
  57 #define DDMA_CONFIG_AL          (1 << 0)
  58
  59 #define DDMA_THROTTLE_EN        (1 << 31)
  60
  61 /* The structure of a DMA Channel.
  62 */
  63 typedef struct au1xxx_dma_channel {
  64         u32     ddma_cfg;       /* See below */
  65         u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
  66         u32     ddma_statptr;   /* word aligned pointer to status word */
  67         u32     ddma_dbell;     /* A write activates channel operation */
  68         u32     ddma_irq;       /* If bit 0 set, interrupt pending */
  69         u32     ddma_stat;      /* See below */
  70         u32     ddma_bytecnt;   /* Byte count, valid only when chan idle */
  71         /* Remainder, up to the 256 byte boundary, is reserved.
  72         */
  73 } au1x_dma_chan_t;
  74
  75 #define DDMA_CFG_SED    (1 << 9)        /* source DMA level/edge detect */
  76 #define DDMA_CFG_SP     (1 << 8)        /* source DMA polarity */
  77 #define DDMA_CFG_DED    (1 << 7)        /* destination DMA level/edge detect */
  78 #define DDMA_CFG_DP     (1 << 6)        /* destination DMA polarity */
  79 #define DDMA_CFG_SYNC   (1 << 5)        /* Sync static bus controller */
  80 #define DDMA_CFG_PPR    (1 << 4)        /* PCI posted read/write control */
  81 #define DDMA_CFG_DFN    (1 << 3)        /* Descriptor fetch non-coherent */
  82 #define DDMA_CFG_SBE    (1 << 2)        /* Source big endian */
  83 #define DDMA_CFG_DBE    (1 << 1)        /* Destination big endian */
  84 #define DDMA_CFG_EN     (1 << 0)        /* Channel enable */
  85
  86 /* Always set when descriptor processing done, regardless of
  87  * interrupt enable state.  Reflected in global intstat, don't
  88  * clear this until global intstat is read/used.
  89  */
  90 #define DDMA_IRQ_IN     (1 << 0)
  91
  92 #define DDMA_STAT_DB    (1 << 2)        /* Doorbell pushed */
  93 #define DDMA_STAT_V     (1 << 1)        /* Descriptor valid */
  94 #define DDMA_STAT_H     (1 << 0)        /* Channel Halted */
  95
  96 /* "Standard" DDMA Descriptor.
  97  * Must be 32-byte aligned.
  98  */
  99 typedef struct au1xxx_ddma_desc {
 100         u32     dscr_cmd0;              /* See below */
 101         u32     dscr_cmd1;              /* See below */
 102         u32     dscr_source0;           /* source phys address */
 103         u32     dscr_source1;           /* See below */
 104         u32     dscr_dest0;             /* Destination address */
 105         u32     dscr_dest1;             /* See below */
 106         u32     dscr_stat;              /* completion status */
 107         u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
 108 } au1x_ddma_desc_t;
 109
 110 #define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
 111 #define DSCR_CMD0_MEM           (1 << 30)       /* mem-mem transfer */
 112 #define DSCR_CMD0_SID_MASK      (0x1f << 25)    /* Source ID */
 113 #define DSCR_CMD0_DID_MASK      (0x1f << 20)    /* Destination ID */
 114 #define DSCR_CMD0_SW_MASK       (0x3 << 18)     /* Source Width */
 115 #define DSCR_CMD0_DW_MASK       (0x3 << 16)     /* Destination Width */
 116 #define DSCR_CMD0_ARB           (0x1 << 15)     /* Set for Hi Pri */
 117 #define DSCR_CMD0_DT_MASK       (0x3 << 13)     /* Descriptor Type */
 118 #define DSCR_CMD0_SN            (0x1 << 12)     /* Source non-coherent */
 119 #define DSCR_CMD0_DN            (0x1 << 11)     /* Destination non-coherent */
 120 #define DSCR_CMD0_SM            (0x1 << 10)     /* Stride mode */
 121 #define DSCR_CMD0_IE            (0x1 << 8)      /* Interrupt Enable */
 122 #define DSCR_CMD0_SP            (0x1 << 4)      /* Status pointer select */
 123 #define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
 124 #define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
 125
 126 /* Command 0 device IDs.
 127 */
 128 #define DSCR_CMD0_UART0_TX      0
 129 #define DSCR_CMD0_UART0_RX      1
 130 #define DSCR_CMD0_UART3_TX      2
 131 #define DSCR_CMD0_UART3_RX      3
 132 #define DSCR_CMD0_DMA_REQ0      4
 133 #define DSCR_CMD0_DMA_REQ1      5
 134 #define DSCR_CMD0_DMA_REQ2      6
 135 #define DSCR_CMD0_DMA_REQ3      7
 136 #define DSCR_CMD0_USBDEV_RX0    8
 137 #define DSCR_CMD0_USBDEV_TX0    9
 138 #define DSCR_CMD0_USBDEV_TX1    10
 139 #define DSCR_CMD0_USBDEV_TX2    11
 140 #define DSCR_CMD0_USBDEV_RX3    12
 141 #define DSCR_CMD0_USBDEV_RX4    13
 142 #define DSCR_CMD0_PSC0_TX       14
 143 #define DSCR_CMD0_PSC0_RX       15
 144 #define DSCR_CMD0_PSC1_TX       16
 145 #define DSCR_CMD0_PSC1_RX       17
 146 #define DSCR_CMD0_PSC2_TX       18
 147 #define DSCR_CMD0_PSC2_RX       19
 148 #define DSCR_CMD0_PSC3_TX       20
 149 #define DSCR_CMD0_PSC3_RX       21
 150 #define DSCR_CMD0_PCI_WRITE     22
 151 #define DSCR_CMD0_NAND_FLASH    23
 152 #define DSCR_CMD0_MAC0_RX       24
 153 #define DSCR_CMD0_MAC0_TX       25
 154 #define DSCR_CMD0_MAC1_RX       26
 155 #define DSCR_CMD0_MAC1_TX       27
 156 #define DSCR_CMD0_THROTTLE      30
 157 #define DSCR_CMD0_ALWAYS        31
 158 #define DSCR_NDEV_IDS           32
 159
 160 #define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
 161 #define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
 162
 163 /* Source/Destination transfer width.
 164 */
 165 #define DSCR_CMD0_BYTE          0
 166 #define DSCR_CMD0_HALFWORD      1
 167 #define DSCR_CMD0_WORD          2
 168
 169 #define DSCR_CMD0_SW(x)         (((x) & 0x3) << 18)
 170 #define DSCR_CMD0_DW(x)         (((x) & 0x3) << 16)
 171
 172 /* DDMA Descriptor Type.
 173 */
 174 #define DSCR_CMD0_STANDARD      0
 175 #define DSCR_CMD0_LITERAL       1
 176 #define DSCR_CMD0_CMP_BRANCH    2
 177
 178 #define DSCR_CMD0_DT(x)         (((x) & 0x3) << 13)
 179
 180 /* Status Instruction.
 181 */
 182 #define DSCR_CMD0_ST_NOCHANGE   0       /* Don't change */
 183 #define DSCR_CMD0_ST_CURRENT    1       /* Write current status */
 184 #define DSCR_CMD0_ST_CMD0       2       /* Write cmd0 with V cleared */
 185 #define DSCR_CMD0_ST_BYTECNT    3       /* Write remaining byte count */
 186
 187 #define DSCR_CMD0_ST(x)         (((x) & 0x3) << 0)
 188
 189 /* Descriptor Command 1
 190 */
 191 #define DSCR_CMD1_SUPTR_MASK    (0xf << 28)     /* upper 4 bits of src addr */
 192 #define DSCR_CMD1_DUPTR_MASK    (0xf << 24)     /* upper 4 bits of dest addr */
 193 #define DSCR_CMD1_FL_MASK       (0x3 << 22)     /* Flag bits */
 194 #define DSCR_CMD1_BC_MASK       (0x3fffff)      /* Byte count */
 195
 196 /* Flag description.
 197 */
 198 #define DSCR_CMD1_FL_MEM_STRIDE0        0
 199 #define DSCR_CMD1_FL_MEM_STRIDE1        1
 200 #define DSCR_CMD1_FL_MEM_STRIDE2        2
 201
 202 #define DSCR_CMD1_FL(x)         (((x) & 0x3) << 22)
 203
 204 /* Source1, 1-dimensional stride.
 205 */
 206 #define DSCR_SRC1_STS_MASK      (3 << 30)       /* Src xfer size */
 207 #define DSCR_SRC1_SAM_MASK      (3 << 28)       /* Src xfer movement */
 208 #define DSCR_SRC1_SB_MASK       (0x3fff << 14)  /* Block size */
 209 #define DSCR_SRC1_SB(x)         (((x) & 0x3fff) << 14)
 210 #define DSCR_SRC1_SS_MASK       (0x3fff << 0)   /* Stride */
 211 #define DSCR_SRC1_SS(x)         (((x) & 0x3fff) << 0)
 212
 213 /* Dest1, 1-dimensional stride.
 214 */
 215 #define DSCR_DEST1_DTS_MASK     (3 << 30)       /* Dest xfer size */
 216 #define DSCR_DEST1_DAM_MASK     (3 << 28)       /* Dest xfer movement */
 217 #define DSCR_DEST1_DB_MASK      (0x3fff << 14)  /* Block size */
 218 #define DSCR_DEST1_DB(x)        (((x) & 0x3fff) << 14)
 219 #define DSCR_DEST1_DS_MASK      (0x3fff << 0)   /* Stride */
 220 #define DSCR_DEST1_DS(x)        (((x) & 0x3fff) << 0)
 221
 222 #define DSCR_xTS_SIZE1          0
 223 #define DSCR_xTS_SIZE2          1
 224 #define DSCR_xTS_SIZE4          2
 225 #define DSCR_xTS_SIZE8          3
 226 #define DSCR_SRC1_STS(x)        (((x) & 3) << 30)
 227 #define DSCR_DEST1_DTS(x)       (((x) & 3) << 30)
 228
 229 #define DSCR_xAM_INCREMENT      0
 230 #define DSCR_xAM_DECREMENT      1
 231 #define DSCR_xAM_STATIC         2
 232 #define DSCR_xAM_BURST          3
 233 #define DSCR_SRC1_SAM(x)        (((x) & 3) << 28)
 234 #define DSCR_DEST1_DAM(x)       (((x) & 3) << 28)
 235
 236 /* The next descriptor pointer.
 237 */
 238 #define DSCR_NXTPTR_MASK        (0x07ffffff)
 239 #define DSCR_NXTPTR(x)          ((x) >> 5)
 240 #define DSCR_GET_NXTPTR(x)      ((x) << 5)
 241 #define DSCR_NXTPTR_MS          (1 << 27)
 242
 243 /* The number of DBDMA channels.
 244 */
 245 #define NUM_DBDMA_CHANS 16
 246
 247 /* External functions for drivers to use.
 248 */
 249 /* Use this to allocate a dbdma channel.  The device ids are one of the
 250  * DSCR_CMD0 devices IDs, which is usually redefined to a more
 251  * meaningful name.  The 'callback' is called during dma completion
 252  * interrupt.
 253  */
 254 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
 255        void (*callback)(int, void *, struct pt_regs *), void *callparam);
 256
 257 #define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
 258
 259 /* ACK!  These should be in a board specific description file.
 260 */
 261 #ifdef CONFIG_MIPS_PB1550
 262 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
 263 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
 264 #endif
 265 #ifdef CONFIG_MIPS_DB1550
 266 #define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
 267 #define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
 268 #endif
 269
 270
 271 /* Set the device width of a in/out fifo.
 272 */
 273 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
 274
 275 /* Allocate a ring of descriptors for dbdma.
 276 */
 277 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
 278
 279 /* Put buffers on source/destination descriptors.
 280 */
 281 u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
 282 u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
 283
 284 /* Get a buffer from the destination descriptor.
 285 */
 286 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
 287
 288 void au1xxx_dbdma_stop(u32 chanid);
 289 void au1xxx_dbdma_start(u32 chanid);
 290 void au1xxx_dbdma_reset(u32 chanid);
 291 u32 au1xxx_get_dma_residue(u32 chanid);
 292
 293 void au1xxx_dbdma_chan_free(u32 chanid);
 294 void au1xxx_dbdma_dump(u32 chanid);
 295
 296 #endif /* _LANGUAGE_ASSEMBLY */
 297 #endif /* _AU1000_DBDMA_H_ */