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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / pci / msi.c
blobd4c89d73e16dda76ad69b1a50730da6322ceef0b
1 /*
2 * File: msi.c
3 * Purpose: PCI Message Signaled Interrupt (MSI)
4 *
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
7 */
8
9 #include <linux/mm.h>
10 #include <linux/irq.h>
11 #include <linux/interrupt.h>
12 #include <linux/init.h>
13 #include <linux/config.h>
14 #include <linux/ioport.h>
15 #include <linux/smp_lock.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18
19 #include <asm/errno.h>
20 #include <asm/io.h>
21 #include <asm/smp.h>
22
23 #include "msi.h"
24
25 static spinlock_t msi_lock = SPIN_LOCK_UNLOCKED;
26 static struct msi_desc* msi_desc[NR_IRQS] = { [0 ... NR_IRQS-1] = NULL };
27 static kmem_cache_t* msi_cachep;
28
29 static int pci_msi_enable = 1;
30 static int last_alloc_vector = 0;
31 static int nr_released_vectors = 0;
32 static int nr_reserved_vectors = NR_HP_RESERVED_VECTORS;
33 static int nr_msix_devices = 0;
34
35 #ifndef CONFIG_X86_IO_APIC
36 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
37 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
38 #endif
39
40 static void msi_cache_ctor(void *p, kmem_cache_t *cache, unsigned long flags)
41 {
42 memset(p, 0, NR_IRQS * sizeof(struct msi_desc));
43 }
44
45 static int msi_cache_init(void)
46 {
47 msi_cachep = kmem_cache_create("msi_cache",
48 NR_IRQS * sizeof(struct msi_desc),
49 0, SLAB_HWCACHE_ALIGN, msi_cache_ctor, NULL);
50 if (!msi_cachep)
51 return -ENOMEM;
52
53 return 0;
54 }
55
56 static void msi_set_mask_bit(unsigned int vector, int flag)
57 {
58 struct msi_desc *entry;
59
60 entry = (struct msi_desc *)msi_desc[vector];
61 if (!entry || !entry->dev || !entry->mask_base)
62 return;
63 switch (entry->msi_attrib.type) {
64 case PCI_CAP_ID_MSI:
65 {
66 int pos;
67 u32 mask_bits;
68
69 pos = entry->mask_base;
70 pci_read_config_dword(entry->dev, pos, &mask_bits);
71 mask_bits &= ~(1);
72 mask_bits |= flag;
73 pci_write_config_dword(entry->dev, pos, mask_bits);
74 break;
75 }
76 case PCI_CAP_ID_MSIX:
77 {
78 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
79 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET;
80 writel(flag, entry->mask_base + offset);
81 break;
82 }
83 default:
84 break;
85 }
86 }
87
88 #ifdef CONFIG_SMP
89 static void set_msi_affinity(unsigned int vector, cpumask_t cpu_mask)
90 {
91 struct msi_desc *entry;
92 struct msg_address address;
93
94 entry = (struct msi_desc *)msi_desc[vector];
95 if (!entry || !entry->dev)
96 return;
97
98 switch (entry->msi_attrib.type) {
99 case PCI_CAP_ID_MSI:
100 {
101 int pos;
102
103 if (!(pos = pci_find_capability(entry->dev, PCI_CAP_ID_MSI)))
104 return;
105
106 pci_read_config_dword(entry->dev, msi_lower_address_reg(pos),
107 &address.lo_address.value);
108 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
109 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
110 MSI_TARGET_CPU_SHIFT);
111 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
112 pci_write_config_dword(entry->dev, msi_lower_address_reg(pos),
113 address.lo_address.value);
114 break;
115 }
116 case PCI_CAP_ID_MSIX:
117 {
118 int offset = entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
119 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET;
120
121 address.lo_address.value = readl(entry->mask_base + offset);
122 address.lo_address.value &= MSI_ADDRESS_DEST_ID_MASK;
123 address.lo_address.value |= (cpu_mask_to_apicid(cpu_mask) <<
124 MSI_TARGET_CPU_SHIFT);
125 entry->msi_attrib.current_cpu = cpu_mask_to_apicid(cpu_mask);
126 writel(address.lo_address.value, entry->mask_base + offset);
127 break;
128 }
129 default:
130 break;
131 }
132 }
133
134 #ifdef CONFIG_IRQBALANCE
135 static inline void move_msi(int vector)
136 {
137 if (!cpus_empty(pending_irq_balance_cpumask[vector])) {
138 set_msi_affinity(vector, pending_irq_balance_cpumask[vector]);
139 cpus_clear(pending_irq_balance_cpumask[vector]);
140 }
141 }
142 #endif /* CONFIG_IRQBALANCE */
143 #endif /* CONFIG_SMP */
144
145 static void mask_MSI_irq(unsigned int vector)
146 {
147 msi_set_mask_bit(vector, 1);
148 }
149
150 static void unmask_MSI_irq(unsigned int vector)
151 {
152 msi_set_mask_bit(vector, 0);
153 }
154
155 static unsigned int startup_msi_irq_wo_maskbit(unsigned int vector)
156 {
157 struct msi_desc *entry;
158 unsigned long flags;
159
160 spin_lock_irqsave(&msi_lock, flags);
161 entry = msi_desc[vector];
162 if (!entry || !entry->dev) {
163 spin_unlock_irqrestore(&msi_lock, flags);
164 return 0;
165 }
166 entry->msi_attrib.state = 1; /* Mark it active */
167 spin_unlock_irqrestore(&msi_lock, flags);
168
169 return 0; /* never anything pending */
170 }
171
172 static void release_msi(unsigned int vector);
173 static void shutdown_msi_irq(unsigned int vector)
174 {
175 release_msi(vector);
176 }
177
178 #define shutdown_msi_irq_wo_maskbit shutdown_msi_irq
179 static void enable_msi_irq_wo_maskbit(unsigned int vector) {}
180 static void disable_msi_irq_wo_maskbit(unsigned int vector) {}
181 static void ack_msi_irq_wo_maskbit(unsigned int vector) {}
182 static void end_msi_irq_wo_maskbit(unsigned int vector)
183 {
184 move_msi(vector);
185 ack_APIC_irq();
186 }
187
188 static unsigned int startup_msi_irq_w_maskbit(unsigned int vector)
189 {
190 struct msi_desc *entry;
191 unsigned long flags;
192
193 spin_lock_irqsave(&msi_lock, flags);
194 entry = msi_desc[vector];
195 if (!entry || !entry->dev) {
196 spin_unlock_irqrestore(&msi_lock, flags);
197 return 0;
198 }
199 entry->msi_attrib.state = 1; /* Mark it active */
200 spin_unlock_irqrestore(&msi_lock, flags);
201
202 unmask_MSI_irq(vector);
203 return 0; /* never anything pending */
204 }
205
206 #define shutdown_msi_irq_w_maskbit shutdown_msi_irq
207 #define enable_msi_irq_w_maskbit unmask_MSI_irq
208 #define disable_msi_irq_w_maskbit mask_MSI_irq
209 #define ack_msi_irq_w_maskbit mask_MSI_irq
210
211 static void end_msi_irq_w_maskbit(unsigned int vector)
212 {
213 move_msi(vector);
214 unmask_MSI_irq(vector);
215 ack_APIC_irq();
216 }
217
218 /*
219 * Interrupt Type for MSI-X PCI/PCI-X/PCI-Express Devices,
220 * which implement the MSI-X Capability Structure.
221 */
222 static struct hw_interrupt_type msix_irq_type = {
223 .typename = "PCI-MSI-X",
224 .startup = startup_msi_irq_w_maskbit,
225 .shutdown = shutdown_msi_irq_w_maskbit,
226 .enable = enable_msi_irq_w_maskbit,
227 .disable = disable_msi_irq_w_maskbit,
228 .ack = ack_msi_irq_w_maskbit,
229 .end = end_msi_irq_w_maskbit,
230 .set_affinity = set_msi_irq_affinity
231 };
232
233 /*
234 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
235 * which implement the MSI Capability Structure with
236 * Mask-and-Pending Bits.
237 */
238 static struct hw_interrupt_type msi_irq_w_maskbit_type = {
239 .typename = "PCI-MSI",
240 .startup = startup_msi_irq_w_maskbit,
241 .shutdown = shutdown_msi_irq_w_maskbit,
242 .enable = enable_msi_irq_w_maskbit,
243 .disable = disable_msi_irq_w_maskbit,
244 .ack = ack_msi_irq_w_maskbit,
245 .end = end_msi_irq_w_maskbit,
246 .set_affinity = set_msi_irq_affinity
247 };
248
249 /*
250 * Interrupt Type for MSI PCI/PCI-X/PCI-Express Devices,
251 * which implement the MSI Capability Structure without
252 * Mask-and-Pending Bits.
253 */
254 static struct hw_interrupt_type msi_irq_wo_maskbit_type = {
255 .typename = "PCI-MSI",
256 .startup = startup_msi_irq_wo_maskbit,
257 .shutdown = shutdown_msi_irq_wo_maskbit,
258 .enable = enable_msi_irq_wo_maskbit,
259 .disable = disable_msi_irq_wo_maskbit,
260 .ack = ack_msi_irq_wo_maskbit,
261 .end = end_msi_irq_wo_maskbit,
262 .set_affinity = set_msi_irq_affinity
263 };
264
265 static void msi_data_init(struct msg_data *msi_data,
266 unsigned int vector)
267 {
268 memset(msi_data, 0, sizeof(struct msg_data));
269 msi_data->vector = (u8)vector;
270 msi_data->delivery_mode = MSI_DELIVERY_MODE;
271 msi_data->level = MSI_LEVEL_MODE;
272 msi_data->trigger = MSI_TRIGGER_MODE;
273 }
274
275 static void msi_address_init(struct msg_address *msi_address)
276 {
277 unsigned int dest_id;
278
279 memset(msi_address, 0, sizeof(struct msg_address));
280 msi_address->hi_address = (u32)0;
281 dest_id = (MSI_ADDRESS_HEADER << MSI_ADDRESS_HEADER_SHIFT);
282 msi_address->lo_address.u.dest_mode = MSI_DEST_MODE;
283 msi_address->lo_address.u.redirection_hint = MSI_REDIRECTION_HINT_MODE;
284 msi_address->lo_address.u.dest_id = dest_id;
285 msi_address->lo_address.value |= (MSI_TARGET_CPU << MSI_TARGET_CPU_SHIFT);
286 }
287
288 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign);
289 static int assign_msi_vector(void)
290 {
291 static int new_vector_avail = 1;
292 int vector;
293 unsigned long flags;
294
295 /*
296 * msi_lock is provided to ensure that successful allocation of MSI
297 * vector is assigned unique among drivers.
298 */
299 spin_lock_irqsave(&msi_lock, flags);
300
301 if (!new_vector_avail) {
302 int free_vector = 0;
303
304 /*
305 * vector_irq[] = -1 indicates that this specific vector is:
306 * - assigned for MSI (since MSI have no associated IRQ) or
307 * - assigned for legacy if less than 16, or
308 * - having no corresponding 1:1 vector-to-IOxAPIC IRQ mapping
309 * vector_irq[] = 0 indicates that this vector, previously
310 * assigned for MSI, is freed by hotplug removed operations.
311 * This vector will be reused for any subsequent hotplug added
312 * operations.
313 * vector_irq[] > 0 indicates that this vector is assigned for
314 * IOxAPIC IRQs. This vector and its value provides a 1-to-1
315 * vector-to-IOxAPIC IRQ mapping.
316 */
317 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
318 if (vector_irq[vector] != 0)
319 continue;
320 free_vector = vector;
321 if (!msi_desc[vector])
322 break;
323 else
324 continue;
325 }
326 if (!free_vector) {
327 spin_unlock_irqrestore(&msi_lock, flags);
328 return -EBUSY;
329 }
330 vector_irq[free_vector] = -1;
331 nr_released_vectors--;
332 spin_unlock_irqrestore(&msi_lock, flags);
333 if (msi_desc[free_vector] != NULL) {
334 struct pci_dev *dev;
335 int tail;
336
337 /* free all linked vectors before re-assign */
338 do {
339 spin_lock_irqsave(&msi_lock, flags);
340 dev = msi_desc[free_vector]->dev;
341 tail = msi_desc[free_vector]->link.tail;
342 spin_unlock_irqrestore(&msi_lock, flags);
343 msi_free_vector(dev, tail, 1);
344 } while (free_vector != tail);
345 }
346
347 return free_vector;
348 }
349 vector = assign_irq_vector(AUTO_ASSIGN);
350 last_alloc_vector = vector;
351 if (vector == LAST_DEVICE_VECTOR)
352 new_vector_avail = 0;
353
354 spin_unlock_irqrestore(&msi_lock, flags);
355 return vector;
356 }
357
358 static int get_new_vector(void)
359 {
360 int vector;
361
362 if ((vector = assign_msi_vector()) > 0)
363 set_intr_gate(vector, interrupt[vector]);
364
365 return vector;
366 }
367
368 static int msi_init(void)
369 {
370 static int status = -ENOMEM;
371
372 if (!status)
373 return status;
374
375 if ((status = msi_cache_init()) < 0) {
376 pci_msi_enable = 0;
377 printk(KERN_INFO "WARNING: MSI INIT FAILURE\n");
378 return status;
379 }
380 last_alloc_vector = assign_irq_vector(AUTO_ASSIGN);
381 if (last_alloc_vector < 0) {
382 pci_msi_enable = 0;
383 printk(KERN_INFO "WARNING: ALL VECTORS ARE BUSY\n");
384 status = -EBUSY;
385 return status;
386 }
387 vector_irq[last_alloc_vector] = 0;
388 nr_released_vectors++;
389 printk(KERN_INFO "MSI INIT SUCCESS\n");
390
391 return status;
392 }
393
394 static int get_msi_vector(struct pci_dev *dev)
395 {
396 return get_new_vector();
397 }
398
399 static struct msi_desc* alloc_msi_entry(void)
400 {
401 struct msi_desc *entry;
402
403 entry = (struct msi_desc*) kmem_cache_alloc(msi_cachep, SLAB_KERNEL);
404 if (!entry)
405 return NULL;
406
407 memset(entry, 0, sizeof(struct msi_desc));
408 entry->link.tail = entry->link.head = 0; /* single message */
409 entry->dev = NULL;
410
411 return entry;
412 }
413
414 static void attach_msi_entry(struct msi_desc *entry, int vector)
415 {
416 unsigned long flags;
417
418 spin_lock_irqsave(&msi_lock, flags);
419 msi_desc[vector] = entry;
420 spin_unlock_irqrestore(&msi_lock, flags);
421 }
422
423 static void irq_handler_init(int cap_id, int pos, int mask)
424 {
425 spin_lock(&irq_desc[pos].lock);
426 if (cap_id == PCI_CAP_ID_MSIX)
427 irq_desc[pos].handler = &msix_irq_type;
428 else {
429 if (!mask)
430 irq_desc[pos].handler = &msi_irq_wo_maskbit_type;
431 else
432 irq_desc[pos].handler = &msi_irq_w_maskbit_type;
433 }
434 spin_unlock(&irq_desc[pos].lock);
435 }
436
437 static void enable_msi_mode(struct pci_dev *dev, int pos, int type)
438 {
439 u16 control;
440
441 pci_read_config_word(dev, msi_control_reg(pos), &control);
442 if (type == PCI_CAP_ID_MSI) {
443 /* Set enabled bits to single MSI & enable MSI_enable bit */
444 msi_enable(control, 1);
445 pci_write_config_word(dev, msi_control_reg(pos), control);
446 } else {
447 msix_enable(control);
448 pci_write_config_word(dev, msi_control_reg(pos), control);
449 }
450 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
451 /* PCI Express Endpoint device detected */
452 u16 cmd;
453 pci_read_config_word(dev, PCI_COMMAND, &cmd);
454 cmd |= PCI_COMMAND_INTX_DISABLE;
455 pci_write_config_word(dev, PCI_COMMAND, cmd);
456 }
457 }
458
459 static void disable_msi_mode(struct pci_dev *dev, int pos, int type)
460 {
461 u16 control;
462
463 pci_read_config_word(dev, msi_control_reg(pos), &control);
464 if (type == PCI_CAP_ID_MSI) {
465 /* Set enabled bits to single MSI & enable MSI_enable bit */
466 msi_disable(control);
467 pci_write_config_word(dev, msi_control_reg(pos), control);
468 } else {
469 msix_disable(control);
470 pci_write_config_word(dev, msi_control_reg(pos), control);
471 }
472 if (pci_find_capability(dev, PCI_CAP_ID_EXP)) {
473 /* PCI Express Endpoint device detected */
474 u16 cmd;
475 pci_read_config_word(dev, PCI_COMMAND, &cmd);
476 cmd &= ~PCI_COMMAND_INTX_DISABLE;
477 pci_write_config_word(dev, PCI_COMMAND, cmd);
478 }
479 }
480
481 static int msi_lookup_vector(struct pci_dev *dev, int type)
482 {
483 int vector;
484 unsigned long flags;
485
486 spin_lock_irqsave(&msi_lock, flags);
487 for (vector = FIRST_DEVICE_VECTOR; vector < NR_IRQS; vector++) {
488 if (!msi_desc[vector] || msi_desc[vector]->dev != dev ||
489 msi_desc[vector]->msi_attrib.type != type ||
490 msi_desc[vector]->msi_attrib.default_vector != dev->irq)
491 continue;
492 spin_unlock_irqrestore(&msi_lock, flags);
493 /* This pre-assigned MSI vector for this device
494 already exits. Override dev->irq with this vector */
495 dev->irq = vector;
496 return 0;
497 }
498 spin_unlock_irqrestore(&msi_lock, flags);
499
500 return -EACCES;
501 }
502
503 void pci_scan_msi_device(struct pci_dev *dev)
504 {
505 if (!dev)
506 return;
507
508 if (pci_find_capability(dev, PCI_CAP_ID_MSIX) > 0)
509 nr_msix_devices++;
510 else if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0)
511 nr_reserved_vectors++;
512 }
513
514 /**
515 * msi_capability_init - configure device's MSI capability structure
516 * @dev: pointer to the pci_dev data structure of MSI device function
517 *
518 * Setup the MSI capability structure of device funtion with a single
519 * MSI vector, regardless of device function is capable of handling
520 * multiple messages. A return of zero indicates the successful setup
521 * of an entry zero with the new MSI vector or non-zero for otherwise.
522 **/
523 static int msi_capability_init(struct pci_dev *dev)
524 {
525 struct msi_desc *entry;
526 struct msg_address address;
527 struct msg_data data;
528 int pos, vector;
529 u16 control;
530
531 pos = pci_find_capability(dev, PCI_CAP_ID_MSI);
532 pci_read_config_word(dev, msi_control_reg(pos), &control);
533 /* MSI Entry Initialization */
534 if (!(entry = alloc_msi_entry()))
535 return -ENOMEM;
536
537 if ((vector = get_msi_vector(dev)) < 0) {
538 kmem_cache_free(msi_cachep, entry);
539 return -EBUSY;
540 }
541 entry->link.head = vector;
542 entry->link.tail = vector;
543 entry->msi_attrib.type = PCI_CAP_ID_MSI;
544 entry->msi_attrib.state = 0; /* Mark it not active */
545 entry->msi_attrib.entry_nr = 0;
546 entry->msi_attrib.maskbit = is_mask_bit_support(control);
547 entry->msi_attrib.default_vector = dev->irq; /* Save IOAPIC IRQ */
548 dev->irq = vector;
549 entry->dev = dev;
550 if (is_mask_bit_support(control)) {
551 entry->mask_base = msi_mask_bits_reg(pos,
552 is_64bit_address(control));
553 }
554 /* Replace with MSI handler */
555 irq_handler_init(PCI_CAP_ID_MSI, vector, entry->msi_attrib.maskbit);
556 /* Configure MSI capability structure */
557 msi_address_init(&address);
558 msi_data_init(&data, vector);
559 entry->msi_attrib.current_cpu = ((address.lo_address.u.dest_id >>
560 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
561 pci_write_config_dword(dev, msi_lower_address_reg(pos),
562 address.lo_address.value);
563 if (is_64bit_address(control)) {
564 pci_write_config_dword(dev,
565 msi_upper_address_reg(pos), address.hi_address);
566 pci_write_config_word(dev,
567 msi_data_reg(pos, 1), *((u32*)&data));
568 } else
569 pci_write_config_word(dev,
570 msi_data_reg(pos, 0), *((u32*)&data));
571 if (entry->msi_attrib.maskbit) {
572 unsigned int maskbits, temp;
573 /* All MSIs are unmasked by default, Mask them all */
574 pci_read_config_dword(dev,
575 msi_mask_bits_reg(pos, is_64bit_address(control)),
576 &maskbits);
577 temp = (1 << multi_msi_capable(control));
578 temp = ((temp - 1) & ~temp);
579 maskbits |= temp;
580 pci_write_config_dword(dev,
581 msi_mask_bits_reg(pos, is_64bit_address(control)),
582 maskbits);
583 }
584 attach_msi_entry(entry, vector);
585 /* Set MSI enabled bits */
586 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
587
588 return 0;
589 }
590
591 /**
592 * msix_capability_init - configure device's MSI-X capability
593 * @dev: pointer to the pci_dev data structure of MSI-X device function
594 *
595 * Setup the MSI-X capability structure of device funtion with a
596 * single MSI-X vector. A return of zero indicates the successful setup of
597 * requested MSI-X entries with allocated vectors or non-zero for otherwise.
598 **/
599 static int msix_capability_init(struct pci_dev *dev,
600 struct msix_entry *entries, int nvec)
601 {
602 struct msi_desc *head = NULL, *tail = NULL, *entry = NULL;
603 struct msg_address address;
604 struct msg_data data;
605 int vector, pos, i, j, nr_entries, temp = 0;
606 u32 phys_addr, table_offset;
607 u16 control;
608 u8 bir;
609 void *base;
610
611 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
612 /* Request & Map MSI-X table region */
613 pci_read_config_word(dev, msi_control_reg(pos), &control);
614 nr_entries = multi_msix_capable(control);
615 pci_read_config_dword(dev, msix_table_offset_reg(pos),
616 &table_offset);
617 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
618 phys_addr = pci_resource_start (dev, bir);
619 phys_addr += (u32)(table_offset & ~PCI_MSIX_FLAGS_BIRMASK);
620 if (!request_mem_region(phys_addr,
621 nr_entries * PCI_MSIX_ENTRY_SIZE,
622 "MSI-X vector table"))
623 return -ENOMEM;
624 base = ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
625 if (base == NULL) {
626 release_mem_region(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
627 return -ENOMEM;
628 }
629 /* MSI-X Table Initialization */
630 for (i = 0; i < nvec; i++) {
631 entry = alloc_msi_entry();
632 if (!entry)
633 break;
634 if ((vector = get_msi_vector(dev)) < 0)
635 break;
636
637 j = entries[i].entry;
638 entries[i].vector = vector;
639 entry->msi_attrib.type = PCI_CAP_ID_MSIX;
640 entry->msi_attrib.state = 0; /* Mark it not active */
641 entry->msi_attrib.entry_nr = j;
642 entry->msi_attrib.maskbit = 1;
643 entry->msi_attrib.default_vector = dev->irq;
644 entry->dev = dev;
645 entry->mask_base = (unsigned long)base;
646 if (!head) {
647 entry->link.head = vector;
648 entry->link.tail = vector;
649 head = entry;
650 } else {
651 entry->link.head = temp;
652 entry->link.tail = tail->link.tail;
653 tail->link.tail = vector;
654 head->link.head = vector;
655 }
656 temp = vector;
657 tail = entry;
658 /* Replace with MSI-X handler */
659 irq_handler_init(PCI_CAP_ID_MSIX, vector, 1);
660 /* Configure MSI-X capability structure */
661 msi_address_init(&address);
662 msi_data_init(&data, vector);
663 entry->msi_attrib.current_cpu =
664 ((address.lo_address.u.dest_id >>
665 MSI_TARGET_CPU_SHIFT) & MSI_TARGET_CPU_MASK);
666 writel(address.lo_address.value,
667 base + j * PCI_MSIX_ENTRY_SIZE +
668 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
669 writel(address.hi_address,
670 base + j * PCI_MSIX_ENTRY_SIZE +
671 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
672 writel(*(u32*)&data,
673 base + j * PCI_MSIX_ENTRY_SIZE +
674 PCI_MSIX_ENTRY_DATA_OFFSET);
675 attach_msi_entry(entry, vector);
676 }
677 if (i != nvec) {
678 i--;
679 for (; i >= 0; i--) {
680 vector = (entries + i)->vector;
681 msi_free_vector(dev, vector, 0);
682 (entries + i)->vector = 0;
683 }
684 return -EBUSY;
685 }
686 /* Set MSI-X enabled bits */
687 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
688
689 return 0;
690 }
691
692 /**
693 * pci_enable_msi - configure device's MSI capability structure
694 * @dev: pointer to the pci_dev data structure of MSI device function
695 *
696 * Setup the MSI capability structure of device function with
697 * a single MSI vector upon its software driver call to request for
698 * MSI mode enabled on its hardware device function. A return of zero
699 * indicates the successful setup of an entry zero with the new MSI
700 * vector or non-zero for otherwise.
701 **/
702 int pci_enable_msi(struct pci_dev* dev)
703 {
704 int pos, temp = dev->irq, status = -EINVAL;
705 u16 control;
706
707 if (!pci_msi_enable || !dev)
708 return status;
709
710 if ((status = msi_init()) < 0)
711 return status;
712
713 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
714 return -EINVAL;
715
716 pci_read_config_word(dev, msi_control_reg(pos), &control);
717 if (control & PCI_MSI_FLAGS_ENABLE)
718 return 0; /* Already in MSI mode */
719
720 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
721 /* Lookup Sucess */
722 unsigned long flags;
723
724 spin_lock_irqsave(&msi_lock, flags);
725 if (!vector_irq[dev->irq]) {
726 msi_desc[dev->irq]->msi_attrib.state = 0;
727 vector_irq[dev->irq] = -1;
728 nr_released_vectors--;
729 spin_unlock_irqrestore(&msi_lock, flags);
730 enable_msi_mode(dev, pos, PCI_CAP_ID_MSI);
731 return 0;
732 }
733 spin_unlock_irqrestore(&msi_lock, flags);
734 dev->irq = temp;
735 }
736 /* Check whether driver already requested for MSI-X vectors */
737 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
738 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
739 printk(KERN_INFO "Can't enable MSI. Device already had MSI-X vectors assigned\n");
740 dev->irq = temp;
741 return -EINVAL;
742 }
743 status = msi_capability_init(dev);
744 if (!status) {
745 if (!pos)
746 nr_reserved_vectors--; /* Only MSI capable */
747 else if (nr_msix_devices > 0)
748 nr_msix_devices--; /* Both MSI and MSI-X capable,
749 but choose enabling MSI */
750 }
751
752 return status;
753 }
754
755 void pci_disable_msi(struct pci_dev* dev)
756 {
757 struct msi_desc *entry;
758 int pos, default_vector;
759 u16 control;
760 unsigned long flags;
761
762 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSI)))
763 return;
764
765 pci_read_config_word(dev, msi_control_reg(pos), &control);
766 if (!(control & PCI_MSI_FLAGS_ENABLE))
767 return;
768
769 spin_lock_irqsave(&msi_lock, flags);
770 entry = msi_desc[dev->irq];
771 if (!entry || !entry->dev || entry->msi_attrib.type != PCI_CAP_ID_MSI) {
772 spin_unlock_irqrestore(&msi_lock, flags);
773 return;
774 }
775 if (entry->msi_attrib.state) {
776 spin_unlock_irqrestore(&msi_lock, flags);
777 printk(KERN_DEBUG "Driver[%d:%d:%d] unloaded wo doing free_irq on vector->%d\n",
778 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
779 dev->irq);
780 BUG_ON(entry->msi_attrib.state > 0);
781 } else {
782 vector_irq[dev->irq] = 0; /* free it */
783 nr_released_vectors++;
784 default_vector = entry->msi_attrib.default_vector;
785 spin_unlock_irqrestore(&msi_lock, flags);
786 /* Restore dev->irq to its default pin-assertion vector */
787 dev->irq = default_vector;
788 disable_msi_mode(dev, pci_find_capability(dev, PCI_CAP_ID_MSI),
789 PCI_CAP_ID_MSI);
790 }
791 }
792
793 static void release_msi(unsigned int vector)
794 {
795 struct msi_desc *entry;
796 unsigned long flags;
797
798 spin_lock_irqsave(&msi_lock, flags);
799 entry = msi_desc[vector];
800 if (entry && entry->dev)
801 entry->msi_attrib.state = 0; /* Mark it not active */
802 spin_unlock_irqrestore(&msi_lock, flags);
803 }
804
805 static int msi_free_vector(struct pci_dev* dev, int vector, int reassign)
806 {
807 struct msi_desc *entry;
808 int head, entry_nr, type;
809 unsigned long base = 0L;
810 unsigned long flags;
811
812 spin_lock_irqsave(&msi_lock, flags);
813 entry = msi_desc[vector];
814 if (!entry || entry->dev != dev) {
815 spin_unlock_irqrestore(&msi_lock, flags);
816 return -EINVAL;
817 }
818 type = entry->msi_attrib.type;
819 entry_nr = entry->msi_attrib.entry_nr;
820 head = entry->link.head;
821 base = entry->mask_base;
822 msi_desc[entry->link.head]->link.tail = entry->link.tail;
823 msi_desc[entry->link.tail]->link.head = entry->link.head;
824 entry->dev = NULL;
825 if (!reassign) {
826 vector_irq[vector] = 0;
827 nr_released_vectors++;
828 }
829 msi_desc[vector] = NULL;
830 spin_unlock_irqrestore(&msi_lock, flags);
831
832 kmem_cache_free(msi_cachep, entry);
833
834 if (type == PCI_CAP_ID_MSIX) {
835 if (!reassign)
836 writel(1, base +
837 entry_nr * PCI_MSIX_ENTRY_SIZE +
838 PCI_MSIX_ENTRY_VECTOR_CTRL_OFFSET);
839
840 if (head == vector) {
841 /*
842 * Detect last MSI-X vector to be released.
843 * Release the MSI-X memory-mapped table.
844 */
845 int pos, nr_entries;
846 u32 phys_addr, table_offset;
847 u16 control;
848 u8 bir;
849
850 pos = pci_find_capability(dev, PCI_CAP_ID_MSIX);
851 pci_read_config_word(dev, msi_control_reg(pos),
852 &control);
853 nr_entries = multi_msix_capable(control);
854 pci_read_config_dword(dev, msix_table_offset_reg(pos),
855 &table_offset);
856 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
857 phys_addr = pci_resource_start (dev, bir);
858 phys_addr += (u32)(table_offset &
859 ~PCI_MSIX_FLAGS_BIRMASK);
860 iounmap((void*)base);
861 release_mem_region(phys_addr,
862 nr_entries * PCI_MSIX_ENTRY_SIZE);
863 }
864 }
865
866 return 0;
867 }
868
869 static int reroute_msix_table(int head, struct msix_entry *entries, int *nvec)
870 {
871 int vector = head, tail = 0;
872 int i = 0, j = 0, nr_entries = 0;
873 unsigned long base = 0L;
874 unsigned long flags;
875
876 spin_lock_irqsave(&msi_lock, flags);
877 while (head != tail) {
878 nr_entries++;
879 tail = msi_desc[vector]->link.tail;
880 if (entries[0].entry == msi_desc[vector]->msi_attrib.entry_nr)
881 j = vector;
882 vector = tail;
883 }
884 if (*nvec > nr_entries) {
885 spin_unlock_irqrestore(&msi_lock, flags);
886 *nvec = nr_entries;
887 return -EINVAL;
888 }
889 vector = ((j > 0) ? j : head);
890 for (i = 0; i < *nvec; i++) {
891 j = msi_desc[vector]->msi_attrib.entry_nr;
892 msi_desc[vector]->msi_attrib.state = 0; /* Mark it not active */
893 vector_irq[vector] = -1; /* Mark it busy */
894 nr_released_vectors--;
895 entries[i].vector = vector;
896 if (j != (entries + i)->entry) {
897 base = msi_desc[vector]->mask_base;
898 msi_desc[vector]->msi_attrib.entry_nr =
899 (entries + i)->entry;
900 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
901 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET), base +
902 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
903 PCI_MSIX_ENTRY_LOWER_ADDR_OFFSET);
904 writel( readl(base + j * PCI_MSIX_ENTRY_SIZE +
905 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET), base +
906 (entries + i)->entry * PCI_MSIX_ENTRY_SIZE +
907 PCI_MSIX_ENTRY_UPPER_ADDR_OFFSET);
908 writel( (readl(base + j * PCI_MSIX_ENTRY_SIZE +
909 PCI_MSIX_ENTRY_DATA_OFFSET) & 0xff00) | vector,
910 base + (entries+i)->entry*PCI_MSIX_ENTRY_SIZE +
911 PCI_MSIX_ENTRY_DATA_OFFSET);
912 }
913 vector = msi_desc[vector]->link.tail;
914 }
915 spin_unlock_irqrestore(&msi_lock, flags);
916
917 return 0;
918 }
919
920 /**
921 * pci_enable_msix - configure device's MSI-X capability structure
922 * @dev: pointer to the pci_dev data structure of MSI-X device function
923 * @data: pointer to an array of MSI-X entries
924 * @nvec: number of MSI-X vectors requested for allocation by device driver
925 *
926 * Setup the MSI-X capability structure of device function with the number
927 * of requested vectors upon its software driver call to request for
928 * MSI-X mode enabled on its hardware device function. A return of zero
929 * indicates the successful configuration of MSI-X capability structure
930 * with new allocated MSI-X vectors. A return of < 0 indicates a failure.
931 * Or a return of > 0 indicates that driver request is exceeding the number
932 * of vectors available. Driver should use the returned value to re-send
933 * its request.
934 **/
935 int pci_enable_msix(struct pci_dev* dev, struct msix_entry *entries, int nvec)
936 {
937 int status, pos, nr_entries, free_vectors;
938 int i, j, temp;
939 u16 control;
940 unsigned long flags;
941
942 if (!pci_msi_enable || !dev || !entries)
943 return -EINVAL;
944
945 if ((status = msi_init()) < 0)
946 return status;
947
948 if (!(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
949 return -EINVAL;
950
951 pci_read_config_word(dev, msi_control_reg(pos), &control);
952 if (control & PCI_MSIX_FLAGS_ENABLE)
953 return -EINVAL; /* Already in MSI-X mode */
954
955 nr_entries = multi_msix_capable(control);
956 if (nvec > nr_entries)
957 return -EINVAL;
958
959 /* Check for any invalid entries */
960 for (i = 0; i < nvec; i++) {
961 if (entries[i].entry >= nr_entries)
962 return -EINVAL; /* invalid entry */
963 for (j = i + 1; j < nvec; j++) {
964 if (entries[i].entry == entries[j].entry)
965 return -EINVAL; /* duplicate entry */
966 }
967 }
968 temp = dev->irq;
969 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
970 /* Lookup Sucess */
971 nr_entries = nvec;
972 /* Reroute MSI-X table */
973 if (reroute_msix_table(dev->irq, entries, &nr_entries)) {
974 /* #requested > #previous-assigned */
975 dev->irq = temp;
976 return nr_entries;
977 }
978 dev->irq = temp;
979 enable_msi_mode(dev, pos, PCI_CAP_ID_MSIX);
980 return 0;
981 }
982 /* Check whether driver already requested for MSI vector */
983 if (pci_find_capability(dev, PCI_CAP_ID_MSI) > 0 &&
984 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
985 printk(KERN_INFO "Can't enable MSI-X. Device already had MSI vector assigned\n");
986 dev->irq = temp;
987 return -EINVAL;
988 }
989
990 spin_lock_irqsave(&msi_lock, flags);
991 /*
992 * msi_lock is provided to ensure that enough vectors resources are
993 * available before granting.
994 */
995 free_vectors = pci_vector_resources(last_alloc_vector,
996 nr_released_vectors);
997 /* Ensure that each MSI/MSI-X device has one vector reserved by
998 default to avoid any MSI-X driver to take all available
999 resources */
1000 free_vectors -= nr_reserved_vectors;
1001 /* Find the average of free vectors among MSI-X devices */
1002 if (nr_msix_devices > 0)
1003 free_vectors /= nr_msix_devices;
1004 spin_unlock_irqrestore(&msi_lock, flags);
1005
1006 if (nvec > free_vectors) {
1007 if (free_vectors > 0)
1008 return free_vectors;
1009 else
1010 return -EBUSY;
1011 }
1012
1013 status = msix_capability_init(dev, entries, nvec);
1014 if (!status && nr_msix_devices > 0)
1015 nr_msix_devices--;
1016
1017 return status;
1018 }
1019
1020 void pci_disable_msix(struct pci_dev* dev)
1021 {
1022 int pos, temp;
1023 u16 control;
1024
1025 if (!dev || !(pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)))
1026 return;
1027
1028 pci_read_config_word(dev, msi_control_reg(pos), &control);
1029 if (!(control & PCI_MSIX_FLAGS_ENABLE))
1030 return;
1031
1032 temp = dev->irq;
1033 if (!msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1034 int state, vector, head, tail = 0, warning = 0;
1035 unsigned long flags;
1036
1037 vector = head = dev->irq;
1038 spin_lock_irqsave(&msi_lock, flags);
1039 while (head != tail) {
1040 state = msi_desc[vector]->msi_attrib.state;
1041 if (state)
1042 warning = 1;
1043 else {
1044 vector_irq[vector] = 0; /* free it */
1045 nr_released_vectors++;
1046 }
1047 tail = msi_desc[vector]->link.tail;
1048 vector = tail;
1049 }
1050 spin_unlock_irqrestore(&msi_lock, flags);
1051 if (warning) {
1052 dev->irq = temp;
1053 printk(KERN_DEBUG "Driver[%d:%d:%d] unloaded wo doing free_irq on all vectors\n",
1054 dev->bus->number, PCI_SLOT(dev->devfn),
1055 PCI_FUNC(dev->devfn));
1056 BUG_ON(warning > 0);
1057 } else {
1058 dev->irq = temp;
1059 disable_msi_mode(dev,
1060 pci_find_capability(dev, PCI_CAP_ID_MSIX),
1061 PCI_CAP_ID_MSIX);
1062
1063 }
1064 }
1065 }
1066
1067 /**
1068 * msi_remove_pci_irq_vectors - reclaim MSI(X) vectors to unused state
1069 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1070 *
1071 * Being called during hotplug remove, from which the device funciton
1072 * is hot-removed. All previous assigned MSI/MSI-X vectors, if
1073 * allocated for this device function, are reclaimed to unused state,
1074 * which may be used later on.
1075 **/
1076 void msi_remove_pci_irq_vectors(struct pci_dev* dev)
1077 {
1078 int state, pos, temp;
1079 unsigned long flags;
1080
1081 if (!pci_msi_enable || !dev)
1082 return;
1083
1084 temp = dev->irq; /* Save IOAPIC IRQ */
1085 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSI)) > 0 &&
1086 !msi_lookup_vector(dev, PCI_CAP_ID_MSI)) {
1087 spin_lock_irqsave(&msi_lock, flags);
1088 state = msi_desc[dev->irq]->msi_attrib.state;
1089 spin_unlock_irqrestore(&msi_lock, flags);
1090 if (state) {
1091 printk(KERN_DEBUG "Driver[%d:%d:%d] unloaded wo doing free_irq on vector->%d\n",
1092 dev->bus->number, PCI_SLOT(dev->devfn),
1093 PCI_FUNC(dev->devfn), dev->irq);
1094 BUG_ON(state > 0);
1095 } else /* Release MSI vector assigned to this device */
1096 msi_free_vector(dev, dev->irq, 0);
1097 dev->irq = temp; /* Restore IOAPIC IRQ */
1098 }
1099 if ((pos = pci_find_capability(dev, PCI_CAP_ID_MSIX)) > 0 &&
1100 !msi_lookup_vector(dev, PCI_CAP_ID_MSIX)) {
1101 int vector, head, tail = 0, warning = 0;
1102 unsigned long base = 0L;
1103
1104 vector = head = dev->irq;
1105 while (head != tail) {
1106 spin_lock_irqsave(&msi_lock, flags);
1107 state = msi_desc[vector]->msi_attrib.state;
1108 tail = msi_desc[vector]->link.tail;
1109 base = msi_desc[vector]->mask_base;
1110 spin_unlock_irqrestore(&msi_lock, flags);
1111 if (state)
1112 warning = 1;
1113 else if (vector != head) /* Release MSI-X vector */
1114 msi_free_vector(dev, vector, 0);
1115 vector = tail;
1116 }
1117 msi_free_vector(dev, vector, 0);
1118 if (warning) {
1119 /* Force to release the MSI-X memory-mapped table */
1120 u32 phys_addr, table_offset;
1121 u16 control;
1122 u8 bir;
1123
1124 pci_read_config_word(dev, msi_control_reg(pos),
1125 &control);
1126 pci_read_config_dword(dev, msix_table_offset_reg(pos),
1127 &table_offset);
1128 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
1129 phys_addr = pci_resource_start (dev, bir);
1130 phys_addr += (u32)(table_offset &
1131 ~PCI_MSIX_FLAGS_BIRMASK);
1132 iounmap((void*)base);
1133 release_mem_region(phys_addr, PCI_MSIX_ENTRY_SIZE *
1134 multi_msix_capable(control));
1135 printk(KERN_DEBUG "Driver[%d:%d:%d] unloaded wo doing free_irq on all vectors\n",
1136 dev->bus->number, PCI_SLOT(dev->devfn),
1137 PCI_FUNC(dev->devfn));
1138 BUG_ON(warning > 0);
1139 }
1140 dev->irq = temp; /* Restore IOAPIC IRQ */
1141 }
1142 }
1143
1144 EXPORT_SYMBOL(pci_enable_msi);
1145 EXPORT_SYMBOL(pci_disable_msi);
1146 EXPORT_SYMBOL(pci_enable_msix);
1147 EXPORT_SYMBOL(pci_disable_msix);
MOXA 2.6.9 from sdlinux-moxaart.tgz