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MOXA linux-2.6.x / linux-2.6.9-uc0 from sdlinux-moxaart.tgz
[linux-2.6.9-moxart.git] / drivers / net / fealnx.c
blob9112ca037315542bab14670d82845fe8f69bae4a
1 /*
2 Written 1998-2000 by Donald Becker.
3
4 This software may be used and distributed according to the terms of
5 the GNU General Public License (GPL), incorporated herein by reference.
6 Drivers based on or derived from this code fall under the GPL and must
7 retain the authorship, copyright and license notice. This file is not
8 a complete program and may only be used when the entire operating
9 system is licensed under the GPL.
10
11 The author may be reached as becker@scyld.com, or C/O
12 Scyld Computing Corporation
13 410 Severn Ave., Suite 210
14 Annapolis MD 21403
15
16 Support information and updates available at
17 http://www.scyld.com/network/pci-skeleton.html
18
19 Linux kernel updates:
20
21 Version 2.51, Nov 17, 2001 (jgarzik):
22 - Add ethtool support
23 - Replace some MII-related magic numbers with constants
24
25 */
26
27 #define DRV_NAME "fealnx"
28 #define DRV_VERSION "2.51"
29 #define DRV_RELDATE "Nov-17-2001"
30
31 static int debug; /* 1-> print debug message */
32 static int max_interrupt_work = 20;
33
34 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). */
35 static int multicast_filter_limit = 32;
36
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme. */
38 /* Setting to > 1518 effectively disables this feature. */
39 static int rx_copybreak;
40
41 /* Used to pass the media type, etc. */
42 /* Both 'options[]' and 'full_duplex[]' should exist for driver */
43 /* interoperability. */
44 /* The media type is usually passed in 'options[]'. */
45 #define MAX_UNITS 8 /* More are supported, limit only on options */
46 static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
47 static int full_duplex[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 };
48
49 /* Operational parameters that are set at compile time. */
50 /* Keep the ring sizes a power of two for compile efficiency. */
51 /* The compiler will convert <unsigned>'%'<2^N> into a bit mask. */
52 /* Making the Tx ring too large decreases the effectiveness of channel */
53 /* bonding and packet priority. */
54 /* There are no ill effects from too-large receive rings. */
55 // 88-12-9 modify,
56 // #define TX_RING_SIZE 16
57 // #define RX_RING_SIZE 32
58 #define TX_RING_SIZE 6
59 #define RX_RING_SIZE 12
60 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct fealnx_desc)
61 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct fealnx_desc)
62
63 /* Operational parameters that usually are not changed. */
64 /* Time in jiffies before concluding the transmitter is hung. */
65 #define TX_TIMEOUT (2*HZ)
66
67 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
68
69
70 /* Include files, designed to support most kernel versions 2.0.0 and later. */
71 #include <linux/module.h>
72 #include <linux/kernel.h>
73 #include <linux/string.h>
74 #include <linux/timer.h>
75 #include <linux/errno.h>
76 #include <linux/ioport.h>
77 #include <linux/slab.h>
78 #include <linux/interrupt.h>
79 #include <linux/pci.h>
80 #include <linux/netdevice.h>
81 #include <linux/etherdevice.h>
82 #include <linux/skbuff.h>
83 #include <linux/init.h>
84 #include <linux/mii.h>
85 #include <linux/ethtool.h>
86 #include <linux/crc32.h>
87 #include <linux/delay.h>
88
89 #include <asm/processor.h> /* Processor type for cache alignment. */
90 #include <asm/bitops.h>
91 #include <asm/io.h>
92 #include <asm/uaccess.h>
93
94 /* These identify the driver base version and may not be removed. */
95 static char version[] __devinitdata =
96 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE "\n";
97
98
99 /* This driver was written to use PCI memory space, however some x86 systems
100 work only with I/O space accesses. */
101 #ifndef __alpha__
102 #define USE_IO_OPS
103 #endif
104
105 #ifdef USE_IO_OPS
106 #undef readb
107 #undef readw
108 #undef readl
109 #undef writeb
110 #undef writew
111 #undef writel
112 #define readb inb
113 #define readw inw
114 #define readl inl
115 #define writeb outb
116 #define writew outw
117 #define writel outl
118 #endif
119
120 /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. */
121 /* This is only in the support-all-kernels source code. */
122
123 #define RUN_AT(x) (jiffies + (x))
124
125 MODULE_AUTHOR("Myson or whoever");
126 MODULE_DESCRIPTION("Myson MTD-8xx 100/10M Ethernet PCI Adapter Driver");
127 MODULE_LICENSE("GPL");
128 MODULE_PARM(max_interrupt_work, "i");
129 //MODULE_PARM(min_pci_latency, "i");
130 MODULE_PARM(debug, "i");
131 MODULE_PARM(rx_copybreak, "i");
132 MODULE_PARM(multicast_filter_limit, "i");
133 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
134 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
135 MODULE_PARM_DESC(max_interrupt_work, "fealnx maximum events handled per interrupt");
136 MODULE_PARM_DESC(debug, "fealnx enable debugging (0-1)");
137 MODULE_PARM_DESC(rx_copybreak, "fealnx copy breakpoint for copy-only-tiny-frames");
138 MODULE_PARM_DESC(multicast_filter_limit, "fealnx maximum number of filtered multicast addresses");
139 MODULE_PARM_DESC(options, "fealnx: Bits 0-3: media type, bit 17: full duplex");
140 MODULE_PARM_DESC(full_duplex, "fealnx full duplex setting(s) (1)");
141
142 #define MIN_REGION_SIZE 136
143
144 enum pci_flags_bit {
145 PCI_USES_IO = 1,
146 PCI_USES_MEM = 2,
147 PCI_USES_MASTER = 4,
148 PCI_ADDR0 = 0x10 << 0,
149 PCI_ADDR1 = 0x10 << 1,
150 PCI_ADDR2 = 0x10 << 2,
151 PCI_ADDR3 = 0x10 << 3,
152 };
153
154 /* A chip capabilities table, matching the entries in pci_tbl[] above. */
155 enum chip_capability_flags {
156 HAS_MII_XCVR,
157 HAS_CHIP_XCVR,
158 };
159
160 /* 89/6/13 add, */
161 /* for different PHY */
162 enum phy_type_flags {
163 MysonPHY = 1,
164 AhdocPHY = 2,
165 SeeqPHY = 3,
166 MarvellPHY = 4,
167 Myson981 = 5,
168 LevelOnePHY = 6,
169 OtherPHY = 10,
170 };
171
172 struct chip_info {
173 char *chip_name;
174 int io_size;
175 int flags;
176 };
177
178 static struct chip_info skel_netdrv_tbl[] = {
179 {"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
180 {"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR},
181 {"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
182 };
183
184 /* Offsets to the Command and Status Registers. */
185 enum fealnx_offsets {
186 PAR0 = 0x0, /* physical address 0-3 */
187 PAR1 = 0x04, /* physical address 4-5 */
188 MAR0 = 0x08, /* multicast address 0-3 */
189 MAR1 = 0x0C, /* multicast address 4-7 */
190 FAR0 = 0x10, /* flow-control address 0-3 */
191 FAR1 = 0x14, /* flow-control address 4-5 */
192 TCRRCR = 0x18, /* receive & transmit configuration */
193 BCR = 0x1C, /* bus command */
194 TXPDR = 0x20, /* transmit polling demand */
195 RXPDR = 0x24, /* receive polling demand */
196 RXCWP = 0x28, /* receive current word pointer */
197 TXLBA = 0x2C, /* transmit list base address */
198 RXLBA = 0x30, /* receive list base address */
199 ISR = 0x34, /* interrupt status */
200 IMR = 0x38, /* interrupt mask */
201 FTH = 0x3C, /* flow control high/low threshold */
202 MANAGEMENT = 0x40, /* bootrom/eeprom and mii management */
203 TALLY = 0x44, /* tally counters for crc and mpa */
204 TSR = 0x48, /* tally counter for transmit status */
205 BMCRSR = 0x4c, /* basic mode control and status */
206 PHYIDENTIFIER = 0x50, /* phy identifier */
207 ANARANLPAR = 0x54, /* auto-negotiation advertisement and link
208 partner ability */
209 ANEROCR = 0x58, /* auto-negotiation expansion and pci conf. */
210 BPREMRPSR = 0x5c, /* bypass & receive error mask and phy status */
211 };
212
213 /* Bits in the interrupt status/enable registers. */
214 /* The bits in the Intr Status/Enable registers, mostly interrupt sources. */
215 enum intr_status_bits {
216 RFCON = 0x00020000, /* receive flow control xon packet */
217 RFCOFF = 0x00010000, /* receive flow control xoff packet */
218 LSCStatus = 0x00008000, /* link status change */
219 ANCStatus = 0x00004000, /* autonegotiation completed */
220 FBE = 0x00002000, /* fatal bus error */
221 FBEMask = 0x00001800, /* mask bit12-11 */
222 ParityErr = 0x00000000, /* parity error */
223 TargetErr = 0x00001000, /* target abort */
224 MasterErr = 0x00000800, /* master error */
225 TUNF = 0x00000400, /* transmit underflow */
226 ROVF = 0x00000200, /* receive overflow */
227 ETI = 0x00000100, /* transmit early int */
228 ERI = 0x00000080, /* receive early int */
229 CNTOVF = 0x00000040, /* counter overflow */
230 RBU = 0x00000020, /* receive buffer unavailable */
231 TBU = 0x00000010, /* transmit buffer unavilable */
232 TI = 0x00000008, /* transmit interrupt */
233 RI = 0x00000004, /* receive interrupt */
234 RxErr = 0x00000002, /* receive error */
235 };
236
237 /* Bits in the NetworkConfig register, W for writing, R for reading */
238 /* FIXME: some names are invented by me. Marked with (name?) */
239 /* If you have docs and know bit names, please fix 'em */
240 enum rx_mode_bits {
241 CR_W_ENH = 0x02000000, /* enhanced mode (name?) */
242 CR_W_FD = 0x00100000, /* full duplex */
243 CR_W_PS10 = 0x00080000, /* 10 mbit */
244 CR_W_TXEN = 0x00040000, /* tx enable (name?) */
245 CR_W_PS1000 = 0x00010000, /* 1000 mbit */
246 /* CR_W_RXBURSTMASK= 0x00000e00, Im unsure about this */
247 CR_W_RXMODEMASK = 0x000000e0,
248 CR_W_PROM = 0x00000080, /* promiscuous mode */
249 CR_W_AB = 0x00000040, /* accept broadcast */
250 CR_W_AM = 0x00000020, /* accept mutlicast */
251 CR_W_ARP = 0x00000008, /* receive runt pkt */
252 CR_W_ALP = 0x00000004, /* receive long pkt */
253 CR_W_SEP = 0x00000002, /* receive error pkt */
254 CR_W_RXEN = 0x00000001, /* rx enable (unicast?) (name?) */
255
256 CR_R_TXSTOP = 0x04000000, /* tx stopped (name?) */
257 CR_R_FD = 0x00100000, /* full duplex detected */
258 CR_R_PS10 = 0x00080000, /* 10 mbit detected */
259 CR_R_RXSTOP = 0x00008000, /* rx stopped (name?) */
260 };
261
262 /* The Tulip Rx and Tx buffer descriptors. */
263 struct fealnx_desc {
264 s32 status;
265 s32 control;
266 u32 buffer;
267 u32 next_desc;
268 struct fealnx_desc *next_desc_logical;
269 struct sk_buff *skbuff;
270 u32 reserved1;
271 u32 reserved2;
272 };
273
274 /* Bits in network_desc.status */
275 enum rx_desc_status_bits {
276 RXOWN = 0x80000000, /* own bit */
277 FLNGMASK = 0x0fff0000, /* frame length */
278 FLNGShift = 16,
279 MARSTATUS = 0x00004000, /* multicast address received */
280 BARSTATUS = 0x00002000, /* broadcast address received */
281 PHYSTATUS = 0x00001000, /* physical address received */
282 RXFSD = 0x00000800, /* first descriptor */
283 RXLSD = 0x00000400, /* last descriptor */
284 ErrorSummary = 0x80, /* error summary */
285 RUNT = 0x40, /* runt packet received */
286 LONG = 0x20, /* long packet received */
287 FAE = 0x10, /* frame align error */
288 CRC = 0x08, /* crc error */
289 RXER = 0x04, /* receive error */
290 };
291
292 enum rx_desc_control_bits {
293 RXIC = 0x00800000, /* interrupt control */
294 RBSShift = 0,
295 };
296
297 enum tx_desc_status_bits {
298 TXOWN = 0x80000000, /* own bit */
299 JABTO = 0x00004000, /* jabber timeout */
300 CSL = 0x00002000, /* carrier sense lost */
301 LC = 0x00001000, /* late collision */
302 EC = 0x00000800, /* excessive collision */
303 UDF = 0x00000400, /* fifo underflow */
304 DFR = 0x00000200, /* deferred */
305 HF = 0x00000100, /* heartbeat fail */
306 NCRMask = 0x000000ff, /* collision retry count */
307 NCRShift = 0,
308 };
309
310 enum tx_desc_control_bits {
311 TXIC = 0x80000000, /* interrupt control */
312 ETIControl = 0x40000000, /* early transmit interrupt */
313 TXLD = 0x20000000, /* last descriptor */
314 TXFD = 0x10000000, /* first descriptor */
315 CRCEnable = 0x08000000, /* crc control */
316 PADEnable = 0x04000000, /* padding control */
317 RetryTxLC = 0x02000000, /* retry late collision */
318 PKTSMask = 0x3ff800, /* packet size bit21-11 */
319 PKTSShift = 11,
320 TBSMask = 0x000007ff, /* transmit buffer bit 10-0 */
321 TBSShift = 0,
322 };
323
324 /* BootROM/EEPROM/MII Management Register */
325 #define MASK_MIIR_MII_READ 0x00000000
326 #define MASK_MIIR_MII_WRITE 0x00000008
327 #define MASK_MIIR_MII_MDO 0x00000004
328 #define MASK_MIIR_MII_MDI 0x00000002
329 #define MASK_MIIR_MII_MDC 0x00000001
330
331 /* ST+OP+PHYAD+REGAD+TA */
332 #define OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */
333 #define OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */
334
335 /* ------------------------------------------------------------------------- */
336 /* Constants for Myson PHY */
337 /* ------------------------------------------------------------------------- */
338 #define MysonPHYID 0xd0000302
339 /* 89-7-27 add, (begin) */
340 #define MysonPHYID0 0x0302
341 #define StatusRegister 18
342 #define SPEED100 0x0400 // bit10
343 #define FULLMODE 0x0800 // bit11
344 /* 89-7-27 add, (end) */
345
346 /* ------------------------------------------------------------------------- */
347 /* Constants for Seeq 80225 PHY */
348 /* ------------------------------------------------------------------------- */
349 #define SeeqPHYID0 0x0016
350
351 #define MIIRegister18 18
352 #define SPD_DET_100 0x80
353 #define DPLX_DET_FULL 0x40
354
355 /* ------------------------------------------------------------------------- */
356 /* Constants for Ahdoc 101 PHY */
357 /* ------------------------------------------------------------------------- */
358 #define AhdocPHYID0 0x0022
359
360 #define DiagnosticReg 18
361 #define DPLX_FULL 0x0800
362 #define Speed_100 0x0400
363
364 /* 89/6/13 add, */
365 /* -------------------------------------------------------------------------- */
366 /* Constants */
367 /* -------------------------------------------------------------------------- */
368 #define MarvellPHYID0 0x0141
369 #define LevelOnePHYID0 0x0013
370
371 #define MII1000BaseTControlReg 9
372 #define MII1000BaseTStatusReg 10
373 #define SpecificReg 17
374
375 /* for 1000BaseT Control Register */
376 #define PHYAbletoPerform1000FullDuplex 0x0200
377 #define PHYAbletoPerform1000HalfDuplex 0x0100
378 #define PHY1000AbilityMask 0x300
379
380 // for phy specific status register, marvell phy.
381 #define SpeedMask 0x0c000
382 #define Speed_1000M 0x08000
383 #define Speed_100M 0x4000
384 #define Speed_10M 0
385 #define Full_Duplex 0x2000
386
387 // 89/12/29 add, for phy specific status register, levelone phy, (begin)
388 #define LXT1000_100M 0x08000
389 #define LXT1000_1000M 0x0c000
390 #define LXT1000_Full 0x200
391 // 89/12/29 add, for phy specific status register, levelone phy, (end)
392
393 /* for 3-in-1 case, BMCRSR register */
394 #define LinkIsUp2 0x00040000
395
396 /* for PHY */
397 #define LinkIsUp 0x0004
398
399
400 struct netdev_private {
401 /* Descriptor rings first for alignment. */
402 struct fealnx_desc *rx_ring;
403 struct fealnx_desc *tx_ring;
404
405 dma_addr_t rx_ring_dma;
406 dma_addr_t tx_ring_dma;
407
408 spinlock_t lock;
409
410 struct net_device_stats stats;
411
412 /* Media monitoring timer. */
413 struct timer_list timer;
414
415 /* Reset timer */
416 struct timer_list reset_timer;
417 int reset_timer_armed;
418 unsigned long crvalue_sv;
419 unsigned long imrvalue_sv;
420
421 /* Frequently used values: keep some adjacent for cache effect. */
422 int flags;
423 struct pci_dev *pci_dev;
424 unsigned long crvalue;
425 unsigned long bcrvalue;
426 unsigned long imrvalue;
427 struct fealnx_desc *cur_rx;
428 struct fealnx_desc *lack_rxbuf;
429 int really_rx_count;
430 struct fealnx_desc *cur_tx;
431 struct fealnx_desc *cur_tx_copy;
432 int really_tx_count;
433 int free_tx_count;
434 unsigned int rx_buf_sz; /* Based on MTU+slack. */
435
436 /* These values are keep track of the transceiver/media in use. */
437 unsigned int linkok;
438 unsigned int line_speed;
439 unsigned int duplexmode;
440 unsigned int default_port:4; /* Last dev->if_port value. */
441 unsigned int PHYType;
442
443 /* MII transceiver section. */
444 int mii_cnt; /* MII device addresses. */
445 unsigned char phys[2]; /* MII device addresses. */
446 struct mii_if_info mii;
447 };
448
449
450 static int mdio_read(struct net_device *dev, int phy_id, int location);
451 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
452 static int netdev_open(struct net_device *dev);
453 static void getlinktype(struct net_device *dev);
454 static void getlinkstatus(struct net_device *dev);
455 static void netdev_timer(unsigned long data);
456 static void reset_timer(unsigned long data);
457 static void tx_timeout(struct net_device *dev);
458 static void init_ring(struct net_device *dev);
459 static int start_tx(struct sk_buff *skb, struct net_device *dev);
460 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *regs);
461 static int netdev_rx(struct net_device *dev);
462 static void set_rx_mode(struct net_device *dev);
463 static void __set_rx_mode(struct net_device *dev);
464 static struct net_device_stats *get_stats(struct net_device *dev);
465 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
466 static struct ethtool_ops netdev_ethtool_ops;
467 static int netdev_close(struct net_device *dev);
468 static void reset_rx_descriptors(struct net_device *dev);
469 static void reset_tx_descriptors(struct net_device *dev);
470
471 static void stop_nic_rx(long ioaddr, long crvalue)
472 {
473 int delay = 0x1000;
474 writel(crvalue & ~(CR_W_RXEN), ioaddr + TCRRCR);
475 while (--delay) {
476 if ( (readl(ioaddr + TCRRCR) & CR_R_RXSTOP) == CR_R_RXSTOP)
477 break;
478 }
479 }
480
481
482 static void stop_nic_rxtx(long ioaddr, long crvalue)
483 {
484 int delay = 0x1000;
485 writel(crvalue & ~(CR_W_RXEN+CR_W_TXEN), ioaddr + TCRRCR);
486 while (--delay) {
487 if ( (readl(ioaddr + TCRRCR) & (CR_R_RXSTOP+CR_R_TXSTOP))
488 == (CR_R_RXSTOP+CR_R_TXSTOP) )
489 break;
490 }
491 }
492
493
494 static int __devinit fealnx_init_one(struct pci_dev *pdev,
495 const struct pci_device_id *ent)
496 {
497 struct netdev_private *np;
498 int i, option, err, irq;
499 static int card_idx = -1;
500 char boardname[12];
501 long ioaddr;
502 unsigned int chip_id = ent->driver_data;
503 struct net_device *dev;
504 void *ring_space;
505 dma_addr_t ring_dma;
506
507 /* when built into the kernel, we only print version if device is found */
508 #ifndef MODULE
509 static int printed_version;
510 if (!printed_version++)
511 printk(version);
512 #endif
513
514 card_idx++;
515 sprintf(boardname, "fealnx%d", card_idx);
516
517 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
518
519 i = pci_enable_device(pdev);
520 if (i) return i;
521 pci_set_master(pdev);
522
523 #ifdef USE_IO_OPS
524 ioaddr = pci_resource_len(pdev, 0);
525 #else
526 ioaddr = pci_resource_len(pdev, 1);
527 #endif
528 if (ioaddr < MIN_REGION_SIZE) {
529 printk(KERN_ERR "%s: region size %ld too small, aborting\n",
530 boardname, ioaddr);
531 return -ENODEV;
532 }
533
534 i = pci_request_regions(pdev, boardname);
535 if (i) return i;
536
537 irq = pdev->irq;
538
539 #ifdef USE_IO_OPS
540 ioaddr = pci_resource_start(pdev, 0);
541 #else
542 ioaddr = (long) ioremap(pci_resource_start(pdev, 1),
543 pci_resource_len(pdev, 1));
544 if (!ioaddr) {
545 err = -ENOMEM;
546 goto err_out_res;
547 }
548 #endif
549
550 dev = alloc_etherdev(sizeof(struct netdev_private));
551 if (!dev) {
552 err = -ENOMEM;
553 goto err_out_unmap;
554 }
555 SET_MODULE_OWNER(dev);
556 SET_NETDEV_DEV(dev, &pdev->dev);
557
558 /* read ethernet id */
559 for (i = 0; i < 6; ++i)
560 dev->dev_addr[i] = readb(ioaddr + PAR0 + i);
561
562 /* Reset the chip to erase previous misconfiguration. */
563 writel(0x00000001, ioaddr + BCR);
564
565 dev->base_addr = ioaddr;
566 dev->irq = irq;
567
568 /* Make certain the descriptor lists are aligned. */
569 np = dev->priv;
570 spin_lock_init(&np->lock);
571 np->pci_dev = pdev;
572 np->flags = skel_netdrv_tbl[chip_id].flags;
573 pci_set_drvdata(pdev, dev);
574 np->mii.dev = dev;
575 np->mii.mdio_read = mdio_read;
576 np->mii.mdio_write = mdio_write;
577 np->mii.phy_id_mask = 0x1f;
578 np->mii.reg_num_mask = 0x1f;
579
580 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
581 if (!ring_space) {
582 err = -ENOMEM;
583 goto err_out_free_dev;
584 }
585 np->rx_ring = (struct fealnx_desc *)ring_space;
586 np->rx_ring_dma = ring_dma;
587
588 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
589 if (!ring_space) {
590 err = -ENOMEM;
591 goto err_out_free_rx;
592 }
593 np->tx_ring = (struct fealnx_desc *)ring_space;
594 np->tx_ring_dma = ring_dma;
595
596 /* find the connected MII xcvrs */
597 if (np->flags == HAS_MII_XCVR) {
598 int phy, phy_idx = 0;
599
600 for (phy = 1; phy < 32 && phy_idx < 4; phy++) {
601 int mii_status = mdio_read(dev, phy, 1);
602
603 if (mii_status != 0xffff && mii_status != 0x0000) {
604 np->phys[phy_idx++] = phy;
605 printk(KERN_INFO
606 "%s: MII PHY found at address %d, status "
607 "0x%4.4x.\n", dev->name, phy, mii_status);
608 /* get phy type */
609 {
610 unsigned int data;
611
612 data = mdio_read(dev, np->phys[0], 2);
613 if (data == SeeqPHYID0)
614 np->PHYType = SeeqPHY;
615 else if (data == AhdocPHYID0)
616 np->PHYType = AhdocPHY;
617 else if (data == MarvellPHYID0)
618 np->PHYType = MarvellPHY;
619 else if (data == MysonPHYID0)
620 np->PHYType = Myson981;
621 else if (data == LevelOnePHYID0)
622 np->PHYType = LevelOnePHY;
623 else
624 np->PHYType = OtherPHY;
625 }
626 }
627 }
628
629 np->mii_cnt = phy_idx;
630 if (phy_idx == 0) {
631 printk(KERN_WARNING "%s: MII PHY not found -- this device may "
632 "not operate correctly.\n", dev->name);
633 }
634 } else {
635 np->phys[0] = 32;
636 /* 89/6/23 add, (begin) */
637 /* get phy type */
638 if (readl(ioaddr + PHYIDENTIFIER) == MysonPHYID)
639 np->PHYType = MysonPHY;
640 else
641 np->PHYType = OtherPHY;
642 }
643 np->mii.phy_id = np->phys[0];
644
645 if (dev->mem_start)
646 option = dev->mem_start;
647
648 /* The lower four bits are the media type. */
649 if (option > 0) {
650 if (option & 0x200)
651 np->mii.full_duplex = 1;
652 np->default_port = option & 15;
653 }
654
655 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
656 np->mii.full_duplex = full_duplex[card_idx];
657
658 if (np->mii.full_duplex) {
659 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
660 /* 89/6/13 add, (begin) */
661 // if (np->PHYType==MarvellPHY)
662 if ((np->PHYType == MarvellPHY) || (np->PHYType == LevelOnePHY)) {
663 unsigned int data;
664
665 data = mdio_read(dev, np->phys[0], 9);
666 data = (data & 0xfcff) | 0x0200;
667 mdio_write(dev, np->phys[0], 9, data);
668 }
669 /* 89/6/13 add, (end) */
670 if (np->flags == HAS_MII_XCVR)
671 mdio_write(dev, np->phys[0], MII_ADVERTISE, ADVERTISE_FULL);
672 else
673 writel(ADVERTISE_FULL, ioaddr + ANARANLPAR);
674 np->mii.force_media = 1;
675 }
676
677 /* The chip-specific entries in the device structure. */
678 dev->open = &netdev_open;
679 dev->hard_start_xmit = &start_tx;
680 dev->stop = &netdev_close;
681 dev->get_stats = &get_stats;
682 dev->set_multicast_list = &set_rx_mode;
683 dev->do_ioctl = &mii_ioctl;
684 dev->ethtool_ops = &netdev_ethtool_ops;
685 dev->tx_timeout = &tx_timeout;
686 dev->watchdog_timeo = TX_TIMEOUT;
687
688 err = register_netdev(dev);
689 if (err)
690 goto err_out_free_tx;
691
692 printk(KERN_INFO "%s: %s at 0x%lx, ",
693 dev->name, skel_netdrv_tbl[chip_id].chip_name, ioaddr);
694 for (i = 0; i < 5; i++)
695 printk("%2.2x:", dev->dev_addr[i]);
696 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
697
698 return 0;
699
700 err_out_free_tx:
701 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
702 err_out_free_rx:
703 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
704 err_out_free_dev:
705 free_netdev(dev);
706 err_out_unmap:
707 #ifndef USE_IO_OPS
708 iounmap((void *)ioaddr);
709 err_out_res:
710 #endif
711 pci_release_regions(pdev);
712 return err;
713 }
714
715
716 static void __devexit fealnx_remove_one(struct pci_dev *pdev)
717 {
718 struct net_device *dev = pci_get_drvdata(pdev);
719
720 if (dev) {
721 struct netdev_private *np = dev->priv;
722
723 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
724 np->tx_ring_dma);
725 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
726 np->rx_ring_dma);
727 unregister_netdev(dev);
728 #ifndef USE_IO_OPS
729 iounmap((void *)dev->base_addr);
730 #endif
731 free_netdev(dev);
732 pci_release_regions(pdev);
733 pci_set_drvdata(pdev, NULL);
734 } else
735 printk(KERN_ERR "fealnx: remove for unknown device\n");
736 }
737
738
739 static ulong m80x_send_cmd_to_phy(long miiport, int opcode, int phyad, int regad)
740 {
741 ulong miir;
742 int i;
743 unsigned int mask, data;
744
745 /* enable MII output */
746 miir = (ulong) readl(miiport);
747 miir &= 0xfffffff0;
748
749 miir |= MASK_MIIR_MII_WRITE + MASK_MIIR_MII_MDO;
750
751 /* send 32 1's preamble */
752 for (i = 0; i < 32; i++) {
753 /* low MDC; MDO is already high (miir) */
754 miir &= ~MASK_MIIR_MII_MDC;
755 writel(miir, miiport);
756
757 /* high MDC */
758 miir |= MASK_MIIR_MII_MDC;
759 writel(miir, miiport);
760 }
761
762 /* calculate ST+OP+PHYAD+REGAD+TA */
763 data = opcode | (phyad << 7) | (regad << 2);
764
765 /* sent out */
766 mask = 0x8000;
767 while (mask) {
768 /* low MDC, prepare MDO */
769 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
770 if (mask & data)
771 miir |= MASK_MIIR_MII_MDO;
772
773 writel(miir, miiport);
774 /* high MDC */
775 miir |= MASK_MIIR_MII_MDC;
776 writel(miir, miiport);
777 udelay(30);
778
779 /* next */
780 mask >>= 1;
781 if (mask == 0x2 && opcode == OP_READ)
782 miir &= ~MASK_MIIR_MII_WRITE;
783 }
784 return miir;
785 }
786
787
788 static int mdio_read(struct net_device *dev, int phyad, int regad)
789 {
790 long miiport = dev->base_addr + MANAGEMENT;
791 ulong miir;
792 unsigned int mask, data;
793
794 miir = m80x_send_cmd_to_phy(miiport, OP_READ, phyad, regad);
795
796 /* read data */
797 mask = 0x8000;
798 data = 0;
799 while (mask) {
800 /* low MDC */
801 miir &= ~MASK_MIIR_MII_MDC;
802 writel(miir, miiport);
803
804 /* read MDI */
805 miir = readl(miiport);
806 if (miir & MASK_MIIR_MII_MDI)
807 data |= mask;
808
809 /* high MDC, and wait */
810 miir |= MASK_MIIR_MII_MDC;
811 writel(miir, miiport);
812 udelay(30);
813
814 /* next */
815 mask >>= 1;
816 }
817
818 /* low MDC */
819 miir &= ~MASK_MIIR_MII_MDC;
820 writel(miir, miiport);
821
822 return data & 0xffff;
823 }
824
825
826 static void mdio_write(struct net_device *dev, int phyad, int regad, int data)
827 {
828 long miiport = dev->base_addr + MANAGEMENT;
829 ulong miir;
830 unsigned int mask;
831
832 miir = m80x_send_cmd_to_phy(miiport, OP_WRITE, phyad, regad);
833
834 /* write data */
835 mask = 0x8000;
836 while (mask) {
837 /* low MDC, prepare MDO */
838 miir &= ~(MASK_MIIR_MII_MDC + MASK_MIIR_MII_MDO);
839 if (mask & data)
840 miir |= MASK_MIIR_MII_MDO;
841 writel(miir, miiport);
842
843 /* high MDC */
844 miir |= MASK_MIIR_MII_MDC;
845 writel(miir, miiport);
846
847 /* next */
848 mask >>= 1;
849 }
850
851 /* low MDC */
852 miir &= ~MASK_MIIR_MII_MDC;
853 writel(miir, miiport);
854 }
855
856
857 static int netdev_open(struct net_device *dev)
858 {
859 struct netdev_private *np = dev->priv;
860 long ioaddr = dev->base_addr;
861 int i;
862
863 writel(0x00000001, ioaddr + BCR); /* Reset */
864
865 if (request_irq(dev->irq, &intr_handler, SA_SHIRQ, dev->name, dev))
866 return -EAGAIN;
867
868 for (i = 0; i < 3; i++)
869 writew(((unsigned short*)dev->dev_addr)[i],
870 ioaddr + PAR0 + i*2);
871
872 init_ring(dev);
873
874 writel(np->rx_ring_dma, ioaddr + RXLBA);
875 writel(np->tx_ring_dma, ioaddr + TXLBA);
876
877 /* Initialize other registers. */
878 /* Configure the PCI bus bursts and FIFO thresholds.
879 486: Set 8 longword burst.
880 586: no burst limit.
881 Burst length 5:3
882 0 0 0 1
883 0 0 1 4
884 0 1 0 8
885 0 1 1 16
886 1 0 0 32
887 1 0 1 64
888 1 1 0 128
889 1 1 1 256
890 Wait the specified 50 PCI cycles after a reset by initializing
891 Tx and Rx queues and the address filter list.
892 FIXME (Ueimor): optimistic for alpha + posted writes ? */
893 #if defined(__powerpc__) || defined(__sparc__)
894 // 89/9/1 modify,
895 // np->bcrvalue=0x04 | 0x0x38; /* big-endian, 256 burst length */
896 np->bcrvalue = 0x04 | 0x10; /* big-endian, tx 8 burst length */
897 np->crvalue = 0xe00; /* rx 128 burst length */
898 #elif defined(__alpha__) || defined(__x86_64__)
899 // 89/9/1 modify,
900 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
901 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
902 np->crvalue = 0xe00; /* rx 128 burst length */
903 #elif defined(__i386__)
904 #if defined(MODULE)
905 // 89/9/1 modify,
906 // np->bcrvalue=0x38; /* little-endian, 256 burst length */
907 np->bcrvalue = 0x10; /* little-endian, 8 burst length */
908 np->crvalue = 0xe00; /* rx 128 burst length */
909 #else
910 /* When not a module we can work around broken '486 PCI boards. */
911 #define x86 boot_cpu_data.x86
912 // 89/9/1 modify,
913 // np->bcrvalue=(x86 <= 4 ? 0x10 : 0x38);
914 np->bcrvalue = 0x10;
915 np->crvalue = (x86 <= 4 ? 0xa00 : 0xe00);
916 if (x86 <= 4)
917 printk(KERN_INFO "%s: This is a 386/486 PCI system, setting burst "
918 "length to %x.\n", dev->name, (x86 <= 4 ? 0x10 : 0x38));
919 #endif
920 #else
921 // 89/9/1 modify,
922 // np->bcrvalue=0x38;
923 np->bcrvalue = 0x10;
924 np->crvalue = 0xe00; /* rx 128 burst length */
925 #warning Processor architecture undefined!
926 #endif
927 // 89/12/29 add,
928 // 90/1/16 modify,
929 // np->imrvalue=FBE|TUNF|CNTOVF|RBU|TI|RI;
930 np->imrvalue = TUNF | CNTOVF | RBU | TI | RI;
931 if (np->pci_dev->device == 0x891) {
932 np->bcrvalue |= 0x200; /* set PROG bit */
933 np->crvalue |= CR_W_ENH; /* set enhanced bit */
934 np->imrvalue |= ETI;
935 }
936 writel(np->bcrvalue, ioaddr + BCR);
937
938 if (dev->if_port == 0)
939 dev->if_port = np->default_port;
940
941 writel(0, ioaddr + RXPDR);
942 // 89/9/1 modify,
943 // np->crvalue = 0x00e40001; /* tx store and forward, tx/rx enable */
944 np->crvalue |= 0x00e40001; /* tx store and forward, tx/rx enable */
945 np->mii.full_duplex = np->mii.force_media;
946 getlinkstatus(dev);
947 if (np->linkok)
948 getlinktype(dev);
949 __set_rx_mode(dev);
950
951 netif_start_queue(dev);
952
953 /* Clear and Enable interrupts by setting the interrupt mask. */
954 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
955 writel(np->imrvalue, ioaddr + IMR);
956
957 if (debug)
958 printk(KERN_DEBUG "%s: Done netdev_open().\n", dev->name);
959
960 /* Set the timer to check for link beat. */
961 init_timer(&np->timer);
962 np->timer.expires = RUN_AT(3 * HZ);
963 np->timer.data = (unsigned long) dev;
964 np->timer.function = &netdev_timer;
965
966 /* timer handler */
967 add_timer(&np->timer);
968
969 init_timer(&np->reset_timer);
970 np->reset_timer.data = (unsigned long) dev;
971 np->reset_timer.function = &reset_timer;
972 np->reset_timer_armed = 0;
973
974 return 0;
975 }
976
977
978 static void getlinkstatus(struct net_device *dev)
979 /* function: Routine will read MII Status Register to get link status. */
980 /* input : dev... pointer to the adapter block. */
981 /* output : none. */
982 {
983 struct netdev_private *np = dev->priv;
984 unsigned int i, DelayTime = 0x1000;
985
986 np->linkok = 0;
987
988 if (np->PHYType == MysonPHY) {
989 for (i = 0; i < DelayTime; ++i) {
990 if (readl(dev->base_addr + BMCRSR) & LinkIsUp2) {
991 np->linkok = 1;
992 return;
993 }
994 udelay(100);
995 }
996 } else {
997 for (i = 0; i < DelayTime; ++i) {
998 if (mdio_read(dev, np->phys[0], MII_BMSR) & BMSR_LSTATUS) {
999 np->linkok = 1;
1000 return;
1001 }
1002 udelay(100);
1003 }
1004 }
1005 }
1006
1007
1008 static void getlinktype(struct net_device *dev)
1009 {
1010 struct netdev_private *np = dev->priv;
1011
1012 if (np->PHYType == MysonPHY) { /* 3-in-1 case */
1013 if (readl(dev->base_addr + TCRRCR) & CR_R_FD)
1014 np->duplexmode = 2; /* full duplex */
1015 else
1016 np->duplexmode = 1; /* half duplex */
1017 if (readl(dev->base_addr + TCRRCR) & CR_R_PS10)
1018 np->line_speed = 1; /* 10M */
1019 else
1020 np->line_speed = 2; /* 100M */
1021 } else {
1022 if (np->PHYType == SeeqPHY) { /* this PHY is SEEQ 80225 */
1023 unsigned int data;
1024
1025 data = mdio_read(dev, np->phys[0], MIIRegister18);
1026 if (data & SPD_DET_100)
1027 np->line_speed = 2; /* 100M */
1028 else
1029 np->line_speed = 1; /* 10M */
1030 if (data & DPLX_DET_FULL)
1031 np->duplexmode = 2; /* full duplex mode */
1032 else
1033 np->duplexmode = 1; /* half duplex mode */
1034 } else if (np->PHYType == AhdocPHY) {
1035 unsigned int data;
1036
1037 data = mdio_read(dev, np->phys[0], DiagnosticReg);
1038 if (data & Speed_100)
1039 np->line_speed = 2; /* 100M */
1040 else
1041 np->line_speed = 1; /* 10M */
1042 if (data & DPLX_FULL)
1043 np->duplexmode = 2; /* full duplex mode */
1044 else
1045 np->duplexmode = 1; /* half duplex mode */
1046 }
1047 /* 89/6/13 add, (begin) */
1048 else if (np->PHYType == MarvellPHY) {
1049 unsigned int data;
1050
1051 data = mdio_read(dev, np->phys[0], SpecificReg);
1052 if (data & Full_Duplex)
1053 np->duplexmode = 2; /* full duplex mode */
1054 else
1055 np->duplexmode = 1; /* half duplex mode */
1056 data &= SpeedMask;
1057 if (data == Speed_1000M)
1058 np->line_speed = 3; /* 1000M */
1059 else if (data == Speed_100M)
1060 np->line_speed = 2; /* 100M */
1061 else
1062 np->line_speed = 1; /* 10M */
1063 }
1064 /* 89/6/13 add, (end) */
1065 /* 89/7/27 add, (begin) */
1066 else if (np->PHYType == Myson981) {
1067 unsigned int data;
1068
1069 data = mdio_read(dev, np->phys[0], StatusRegister);
1070
1071 if (data & SPEED100)
1072 np->line_speed = 2;
1073 else
1074 np->line_speed = 1;
1075
1076 if (data & FULLMODE)
1077 np->duplexmode = 2;
1078 else
1079 np->duplexmode = 1;
1080 }
1081 /* 89/7/27 add, (end) */
1082 /* 89/12/29 add */
1083 else if (np->PHYType == LevelOnePHY) {
1084 unsigned int data;
1085
1086 data = mdio_read(dev, np->phys[0], SpecificReg);
1087 if (data & LXT1000_Full)
1088 np->duplexmode = 2; /* full duplex mode */
1089 else
1090 np->duplexmode = 1; /* half duplex mode */
1091 data &= SpeedMask;
1092 if (data == LXT1000_1000M)
1093 np->line_speed = 3; /* 1000M */
1094 else if (data == LXT1000_100M)
1095 np->line_speed = 2; /* 100M */
1096 else
1097 np->line_speed = 1; /* 10M */
1098 }
1099 np->crvalue &= (~CR_W_PS10) & (~CR_W_FD) & (~CR_W_PS1000);
1100 if (np->line_speed == 1)
1101 np->crvalue |= CR_W_PS10;
1102 else if (np->line_speed == 3)
1103 np->crvalue |= CR_W_PS1000;
1104 if (np->duplexmode == 2)
1105 np->crvalue |= CR_W_FD;
1106 }
1107 }
1108
1109
1110 /* Take lock before calling this */
1111 static void allocate_rx_buffers(struct net_device *dev)
1112 {
1113 struct netdev_private *np = dev->priv;
1114
1115 /* allocate skb for rx buffers */
1116 while (np->really_rx_count != RX_RING_SIZE) {
1117 struct sk_buff *skb;
1118
1119 skb = dev_alloc_skb(np->rx_buf_sz);
1120 if (skb == NULL)
1121 break; /* Better luck next round. */
1122
1123 while (np->lack_rxbuf->skbuff)
1124 np->lack_rxbuf = np->lack_rxbuf->next_desc_logical;
1125
1126 skb->dev = dev; /* Mark as being used by this device. */
1127 np->lack_rxbuf->skbuff = skb;
1128 np->lack_rxbuf->buffer = pci_map_single(np->pci_dev, skb->tail,
1129 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1130 np->lack_rxbuf->status = RXOWN;
1131 ++np->really_rx_count;
1132 }
1133 }
1134
1135
1136 static void netdev_timer(unsigned long data)
1137 {
1138 struct net_device *dev = (struct net_device *) data;
1139 struct netdev_private *np = dev->priv;
1140 long ioaddr = dev->base_addr;
1141 int old_crvalue = np->crvalue;
1142 unsigned int old_linkok = np->linkok;
1143 unsigned long flags;
1144
1145 if (debug)
1146 printk(KERN_DEBUG "%s: Media selection timer tick, status %8.8x "
1147 "config %8.8x.\n", dev->name, readl(ioaddr + ISR),
1148 readl(ioaddr + TCRRCR));
1149
1150 spin_lock_irqsave(&np->lock, flags);
1151
1152 if (np->flags == HAS_MII_XCVR) {
1153 getlinkstatus(dev);
1154 if ((old_linkok == 0) && (np->linkok == 1)) { /* we need to detect the media type again */
1155 getlinktype(dev);
1156 if (np->crvalue != old_crvalue) {
1157 stop_nic_rxtx(ioaddr, np->crvalue);
1158 writel(np->crvalue, ioaddr + TCRRCR);
1159 }
1160 }
1161 }
1162
1163 allocate_rx_buffers(dev);
1164
1165 spin_unlock_irqrestore(&np->lock, flags);
1166
1167 np->timer.expires = RUN_AT(10 * HZ);
1168 add_timer(&np->timer);
1169 }
1170
1171
1172 /* Take lock before calling */
1173 /* Reset chip and disable rx, tx and interrupts */
1174 static void reset_and_disable_rxtx(struct net_device *dev)
1175 {
1176 long ioaddr = dev->base_addr;
1177 int delay=51;
1178
1179 /* Reset the chip's Tx and Rx processes. */
1180 stop_nic_rxtx(ioaddr, 0);
1181
1182 /* Disable interrupts by clearing the interrupt mask. */
1183 writel(0, ioaddr + IMR);
1184
1185 /* Reset the chip to erase previous misconfiguration. */
1186 writel(0x00000001, ioaddr + BCR);
1187
1188 /* Ueimor: wait for 50 PCI cycles (and flush posted writes btw).
1189 We surely wait too long (address+data phase). Who cares? */
1190 while (--delay) {
1191 readl(ioaddr + BCR);
1192 rmb();
1193 }
1194 }
1195
1196
1197 /* Take lock before calling */
1198 /* Restore chip after reset */
1199 static void enable_rxtx(struct net_device *dev)
1200 {
1201 struct netdev_private *np = dev->priv;
1202 long ioaddr = dev->base_addr;
1203
1204 reset_rx_descriptors(dev);
1205
1206 writel(np->tx_ring_dma + ((char*)np->cur_tx - (char*)np->tx_ring),
1207 ioaddr + TXLBA);
1208 writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1209 ioaddr + RXLBA);
1210
1211 writel(np->bcrvalue, ioaddr + BCR);
1212
1213 writel(0, ioaddr + RXPDR);
1214 __set_rx_mode(dev); /* changes np->crvalue, writes it into TCRRCR */
1215
1216 /* Clear and Enable interrupts by setting the interrupt mask. */
1217 writel(FBE | TUNF | CNTOVF | RBU | TI | RI, ioaddr + ISR);
1218 writel(np->imrvalue, ioaddr + IMR);
1219
1220 writel(0, ioaddr + TXPDR);
1221 }
1222
1223
1224 static void reset_timer(unsigned long data)
1225 {
1226 struct net_device *dev = (struct net_device *) data;
1227 struct netdev_private *np = dev->priv;
1228 unsigned long flags;
1229
1230 printk(KERN_WARNING "%s: resetting tx and rx machinery\n", dev->name);
1231
1232 spin_lock_irqsave(&np->lock, flags);
1233 np->crvalue = np->crvalue_sv;
1234 np->imrvalue = np->imrvalue_sv;
1235
1236 reset_and_disable_rxtx(dev);
1237 /* works for me without this:
1238 reset_tx_descriptors(dev); */
1239 enable_rxtx(dev);
1240 netif_start_queue(dev); /* FIXME: or netif_wake_queue(dev); ? */
1241
1242 np->reset_timer_armed = 0;
1243
1244 spin_unlock_irqrestore(&np->lock, flags);
1245 }
1246
1247
1248 static void tx_timeout(struct net_device *dev)
1249 {
1250 struct netdev_private *np = dev->priv;
1251 long ioaddr = dev->base_addr;
1252 unsigned long flags;
1253 int i;
1254
1255 printk(KERN_WARNING "%s: Transmit timed out, status %8.8x,"
1256 " resetting...\n", dev->name, readl(ioaddr + ISR));
1257
1258 {
1259 printk(KERN_DEBUG " Rx ring %p: ", np->rx_ring);
1260 for (i = 0; i < RX_RING_SIZE; i++)
1261 printk(" %8.8x", (unsigned int) np->rx_ring[i].status);
1262 printk("\n" KERN_DEBUG " Tx ring %p: ", np->tx_ring);
1263 for (i = 0; i < TX_RING_SIZE; i++)
1264 printk(" %4.4x", np->tx_ring[i].status);
1265 printk("\n");
1266 }
1267
1268 spin_lock_irqsave(&np->lock, flags);
1269
1270 reset_and_disable_rxtx(dev);
1271 reset_tx_descriptors(dev);
1272 enable_rxtx(dev);
1273
1274 spin_unlock_irqrestore(&np->lock, flags);
1275
1276 dev->trans_start = jiffies;
1277 np->stats.tx_errors++;
1278 netif_wake_queue(dev); /* or .._start_.. ?? */
1279 }
1280
1281
1282 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1283 static void init_ring(struct net_device *dev)
1284 {
1285 struct netdev_private *np = dev->priv;
1286 int i;
1287
1288 /* initialize rx variables */
1289 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1290 np->cur_rx = &np->rx_ring[0];
1291 np->lack_rxbuf = np->rx_ring;
1292 np->really_rx_count = 0;
1293
1294 /* initial rx descriptors. */
1295 for (i = 0; i < RX_RING_SIZE; i++) {
1296 np->rx_ring[i].status = 0;
1297 np->rx_ring[i].control = np->rx_buf_sz << RBSShift;
1298 np->rx_ring[i].next_desc = np->rx_ring_dma +
1299 (i + 1)*sizeof(struct fealnx_desc);
1300 np->rx_ring[i].next_desc_logical = &np->rx_ring[i + 1];
1301 np->rx_ring[i].skbuff = NULL;
1302 }
1303
1304 /* for the last rx descriptor */
1305 np->rx_ring[i - 1].next_desc = np->rx_ring_dma;
1306 np->rx_ring[i - 1].next_desc_logical = np->rx_ring;
1307
1308 /* allocate skb for rx buffers */
1309 for (i = 0; i < RX_RING_SIZE; i++) {
1310 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1311
1312 if (skb == NULL) {
1313 np->lack_rxbuf = &np->rx_ring[i];
1314 break;
1315 }
1316
1317 ++np->really_rx_count;
1318 np->rx_ring[i].skbuff = skb;
1319 skb->dev = dev; /* Mark as being used by this device. */
1320 np->rx_ring[i].buffer = pci_map_single(np->pci_dev, skb->tail,
1321 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1322 np->rx_ring[i].status = RXOWN;
1323 np->rx_ring[i].control |= RXIC;
1324 }
1325
1326 /* initialize tx variables */
1327 np->cur_tx = &np->tx_ring[0];
1328 np->cur_tx_copy = &np->tx_ring[0];
1329 np->really_tx_count = 0;
1330 np->free_tx_count = TX_RING_SIZE;
1331
1332 for (i = 0; i < TX_RING_SIZE; i++) {
1333 np->tx_ring[i].status = 0;
1334 /* do we need np->tx_ring[i].control = XXX; ?? */
1335 np->tx_ring[i].next_desc = np->tx_ring_dma +
1336 (i + 1)*sizeof(struct fealnx_desc);
1337 np->tx_ring[i].next_desc_logical = &np->tx_ring[i + 1];
1338 np->tx_ring[i].skbuff = NULL;
1339 }
1340
1341 /* for the last tx descriptor */
1342 np->tx_ring[i - 1].next_desc = np->tx_ring_dma;
1343 np->tx_ring[i - 1].next_desc_logical = &np->tx_ring[0];
1344 }
1345
1346
1347 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1348 {
1349 struct netdev_private *np = dev->priv;
1350 unsigned long flags;
1351
1352 spin_lock_irqsave(&np->lock, flags);
1353
1354 np->cur_tx_copy->skbuff = skb;
1355
1356 #define one_buffer
1357 #define BPT 1022
1358 #if defined(one_buffer)
1359 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1360 skb->len, PCI_DMA_TODEVICE);
1361 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1362 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1363 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1364 // 89/12/29 add,
1365 if (np->pci_dev->device == 0x891)
1366 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1367 np->cur_tx_copy->status = TXOWN;
1368 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1369 --np->free_tx_count;
1370 #elif defined(two_buffer)
1371 if (skb->len > BPT) {
1372 struct fealnx_desc *next;
1373
1374 /* for the first descriptor */
1375 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1376 BPT, PCI_DMA_TODEVICE);
1377 np->cur_tx_copy->control = TXIC | TXFD | CRCEnable | PADEnable;
1378 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1379 np->cur_tx_copy->control |= (BPT << TBSShift); /* buffer size */
1380
1381 /* for the last descriptor */
1382 next = np->cur_tx_copy->next_desc_logical;
1383 next->skbuff = skb;
1384 next->control = TXIC | TXLD | CRCEnable | PADEnable;
1385 next->control |= (skb->len << PKTSShift); /* pkt size */
1386 next->control |= ((skb->len - BPT) << TBSShift); /* buf size */
1387 // 89/12/29 add,
1388 if (np->pci_dev->device == 0x891)
1389 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1390 next->buffer = pci_map_single(ep->pci_dev, skb->data + BPT,
1391 skb->len - BPT, PCI_DMA_TODEVICE);
1392
1393 next->status = TXOWN;
1394 np->cur_tx_copy->status = TXOWN;
1395
1396 np->cur_tx_copy = next->next_desc_logical;
1397 np->free_tx_count -= 2;
1398 } else {
1399 np->cur_tx_copy->buffer = pci_map_single(np->pci_dev, skb->data,
1400 skb->len, PCI_DMA_TODEVICE);
1401 np->cur_tx_copy->control = TXIC | TXLD | TXFD | CRCEnable | PADEnable;
1402 np->cur_tx_copy->control |= (skb->len << PKTSShift); /* pkt size */
1403 np->cur_tx_copy->control |= (skb->len << TBSShift); /* buffer size */
1404 // 89/12/29 add,
1405 if (np->pci_dev->device == 0x891)
1406 np->cur_tx_copy->control |= ETIControl | RetryTxLC;
1407 np->cur_tx_copy->status = TXOWN;
1408 np->cur_tx_copy = np->cur_tx_copy->next_desc_logical;
1409 --np->free_tx_count;
1410 }
1411 #endif
1412
1413 if (np->free_tx_count < 2)
1414 netif_stop_queue(dev);
1415 ++np->really_tx_count;
1416 writel(0, dev->base_addr + TXPDR);
1417 dev->trans_start = jiffies;
1418
1419 spin_unlock_irqrestore(&np->lock, flags);
1420 return 0;
1421 }
1422
1423
1424 /* Take lock before calling */
1425 /* Chip probably hosed tx ring. Clean up. */
1426 static void reset_tx_descriptors(struct net_device *dev)
1427 {
1428 struct netdev_private *np = dev->priv;
1429 struct fealnx_desc *cur;
1430 int i;
1431
1432 /* initialize tx variables */
1433 np->cur_tx = &np->tx_ring[0];
1434 np->cur_tx_copy = &np->tx_ring[0];
1435 np->really_tx_count = 0;
1436 np->free_tx_count = TX_RING_SIZE;
1437
1438 for (i = 0; i < TX_RING_SIZE; i++) {
1439 cur = &np->tx_ring[i];
1440 if (cur->skbuff) {
1441 pci_unmap_single(np->pci_dev, cur->buffer,
1442 cur->skbuff->len, PCI_DMA_TODEVICE);
1443 dev_kfree_skb(cur->skbuff);
1444 /* or dev_kfree_skb_irq(cur->skbuff); ? */
1445 cur->skbuff = NULL;
1446 }
1447 cur->status = 0;
1448 cur->control = 0; /* needed? */
1449 /* probably not needed. We do it for purely paranoid reasons */
1450 cur->next_desc = np->tx_ring_dma +
1451 (i + 1)*sizeof(struct fealnx_desc);
1452 cur->next_desc_logical = &np->tx_ring[i + 1];
1453 }
1454 /* for the last tx descriptor */
1455 np->tx_ring[TX_RING_SIZE - 1].next_desc = np->tx_ring_dma;
1456 np->tx_ring[TX_RING_SIZE - 1].next_desc_logical = &np->tx_ring[0];
1457 }
1458
1459
1460 /* Take lock and stop rx before calling this */
1461 static void reset_rx_descriptors(struct net_device *dev)
1462 {
1463 struct netdev_private *np = dev->priv;
1464 struct fealnx_desc *cur = np->cur_rx;
1465 int i;
1466
1467 allocate_rx_buffers(dev);
1468
1469 for (i = 0; i < RX_RING_SIZE; i++) {
1470 if (cur->skbuff)
1471 cur->status = RXOWN;
1472 cur = cur->next_desc_logical;
1473 }
1474
1475 writel(np->rx_ring_dma + ((char*)np->cur_rx - (char*)np->rx_ring),
1476 dev->base_addr + RXLBA);
1477 }
1478
1479
1480 /* The interrupt handler does all of the Rx thread work and cleans up
1481 after the Tx thread. */
1482 static irqreturn_t intr_handler(int irq, void *dev_instance, struct pt_regs *rgs)
1483 {
1484 struct net_device *dev = (struct net_device *) dev_instance;
1485 struct netdev_private *np = dev->priv;
1486 long ioaddr = dev->base_addr;
1487 long boguscnt = max_interrupt_work;
1488 unsigned int num_tx = 0;
1489 int handled = 0;
1490
1491 spin_lock(&np->lock);
1492
1493 writel(0, ioaddr + IMR);
1494
1495 do {
1496 u32 intr_status = readl(ioaddr + ISR);
1497
1498 /* Acknowledge all of the current interrupt sources ASAP. */
1499 writel(intr_status, ioaddr + ISR);
1500
1501 if (debug)
1502 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n", dev->name,
1503 intr_status);
1504
1505 if (!(intr_status & np->imrvalue))
1506 break;
1507
1508 handled = 1;
1509
1510 // 90/1/16 delete,
1511 //
1512 // if (intr_status & FBE)
1513 // { /* fatal error */
1514 // stop_nic_tx(ioaddr, 0);
1515 // stop_nic_rx(ioaddr, 0);
1516 // break;
1517 // };
1518
1519 if (intr_status & TUNF)
1520 writel(0, ioaddr + TXPDR);
1521
1522 if (intr_status & CNTOVF) {
1523 /* missed pkts */
1524 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1525
1526 /* crc error */
1527 np->stats.rx_crc_errors +=
1528 (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1529 }
1530
1531 if (intr_status & (RI | RBU)) {
1532 if (intr_status & RI)
1533 netdev_rx(dev);
1534 else {
1535 stop_nic_rx(ioaddr, np->crvalue);
1536 reset_rx_descriptors(dev);
1537 writel(np->crvalue, ioaddr + TCRRCR);
1538 }
1539 }
1540
1541 while (np->really_tx_count) {
1542 long tx_status = np->cur_tx->status;
1543 long tx_control = np->cur_tx->control;
1544
1545 if (!(tx_control & TXLD)) { /* this pkt is combined by two tx descriptors */
1546 struct fealnx_desc *next;
1547
1548 next = np->cur_tx->next_desc_logical;
1549 tx_status = next->status;
1550 tx_control = next->control;
1551 }
1552
1553 if (tx_status & TXOWN)
1554 break;
1555
1556 if (!(np->crvalue & CR_W_ENH)) {
1557 if (tx_status & (CSL | LC | EC | UDF | HF)) {
1558 np->stats.tx_errors++;
1559 if (tx_status & EC)
1560 np->stats.tx_aborted_errors++;
1561 if (tx_status & CSL)
1562 np->stats.tx_carrier_errors++;
1563 if (tx_status & LC)
1564 np->stats.tx_window_errors++;
1565 if (tx_status & UDF)
1566 np->stats.tx_fifo_errors++;
1567 if ((tx_status & HF) && np->mii.full_duplex == 0)
1568 np->stats.tx_heartbeat_errors++;
1569
1570 } else {
1571 np->stats.tx_bytes +=
1572 ((tx_control & PKTSMask) >> PKTSShift);
1573
1574 np->stats.collisions +=
1575 ((tx_status & NCRMask) >> NCRShift);
1576 np->stats.tx_packets++;
1577 }
1578 } else {
1579 np->stats.tx_bytes +=
1580 ((tx_control & PKTSMask) >> PKTSShift);
1581 np->stats.tx_packets++;
1582 }
1583
1584 /* Free the original skb. */
1585 pci_unmap_single(np->pci_dev, np->cur_tx->buffer,
1586 np->cur_tx->skbuff->len, PCI_DMA_TODEVICE);
1587 dev_kfree_skb_irq(np->cur_tx->skbuff);
1588 np->cur_tx->skbuff = NULL;
1589 --np->really_tx_count;
1590 if (np->cur_tx->control & TXLD) {
1591 np->cur_tx = np->cur_tx->next_desc_logical;
1592 ++np->free_tx_count;
1593 } else {
1594 np->cur_tx = np->cur_tx->next_desc_logical;
1595 np->cur_tx = np->cur_tx->next_desc_logical;
1596 np->free_tx_count += 2;
1597 }
1598 num_tx++;
1599 } /* end of for loop */
1600
1601 if (num_tx && np->free_tx_count >= 2)
1602 netif_wake_queue(dev);
1603
1604 /* read transmit status for enhanced mode only */
1605 if (np->crvalue & CR_W_ENH) {
1606 long data;
1607
1608 data = readl(ioaddr + TSR);
1609 np->stats.tx_errors += (data & 0xff000000) >> 24;
1610 np->stats.tx_aborted_errors += (data & 0xff000000) >> 24;
1611 np->stats.tx_window_errors += (data & 0x00ff0000) >> 16;
1612 np->stats.collisions += (data & 0x0000ffff);
1613 }
1614
1615 if (--boguscnt < 0) {
1616 printk(KERN_WARNING "%s: Too much work at interrupt, "
1617 "status=0x%4.4x.\n", dev->name, intr_status);
1618 if (!np->reset_timer_armed) {
1619 np->reset_timer_armed = 1;
1620 np->reset_timer.expires = RUN_AT(HZ/2);
1621 add_timer(&np->reset_timer);
1622 stop_nic_rxtx(ioaddr, 0);
1623 netif_stop_queue(dev);
1624 /* or netif_tx_disable(dev); ?? */
1625 /* Prevent other paths from enabling tx,rx,intrs */
1626 np->crvalue_sv = np->crvalue;
1627 np->imrvalue_sv = np->imrvalue;
1628 np->crvalue &= ~(CR_W_TXEN | CR_W_RXEN); /* or simply = 0? */
1629 np->imrvalue = 0;
1630 }
1631
1632 break;
1633 }
1634 } while (1);
1635
1636 /* read the tally counters */
1637 /* missed pkts */
1638 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1639
1640 /* crc error */
1641 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1642
1643 if (debug)
1644 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1645 dev->name, readl(ioaddr + ISR));
1646
1647 writel(np->imrvalue, ioaddr + IMR);
1648
1649 spin_unlock(&np->lock);
1650
1651 return IRQ_RETVAL(handled);
1652 }
1653
1654
1655 /* This routine is logically part of the interrupt handler, but separated
1656 for clarity and better register allocation. */
1657 static int netdev_rx(struct net_device *dev)
1658 {
1659 struct netdev_private *np = dev->priv;
1660 long ioaddr = dev->base_addr;
1661
1662 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1663 while (!(np->cur_rx->status & RXOWN) && np->cur_rx->skbuff) {
1664 s32 rx_status = np->cur_rx->status;
1665
1666 if (np->really_rx_count == 0)
1667 break;
1668
1669 if (debug)
1670 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n", rx_status);
1671
1672 if ((!((rx_status & RXFSD) && (rx_status & RXLSD)))
1673 || (rx_status & ErrorSummary)) {
1674 if (rx_status & ErrorSummary) { /* there was a fatal error */
1675 if (debug)
1676 printk(KERN_DEBUG
1677 "%s: Receive error, Rx status %8.8x.\n",
1678 dev->name, rx_status);
1679
1680 np->stats.rx_errors++; /* end of a packet. */
1681 if (rx_status & (LONG | RUNT))
1682 np->stats.rx_length_errors++;
1683 if (rx_status & RXER)
1684 np->stats.rx_frame_errors++;
1685 if (rx_status & CRC)
1686 np->stats.rx_crc_errors++;
1687 } else {
1688 int need_to_reset = 0;
1689 int desno = 0;
1690
1691 if (rx_status & RXFSD) { /* this pkt is too long, over one rx buffer */
1692 struct fealnx_desc *cur;
1693
1694 /* check this packet is received completely? */
1695 cur = np->cur_rx;
1696 while (desno <= np->really_rx_count) {
1697 ++desno;
1698 if ((!(cur->status & RXOWN))
1699 && (cur->status & RXLSD))
1700 break;
1701 /* goto next rx descriptor */
1702 cur = cur->next_desc_logical;
1703 }
1704 if (desno > np->really_rx_count)
1705 need_to_reset = 1;
1706 } else /* RXLSD did not find, something error */
1707 need_to_reset = 1;
1708
1709 if (need_to_reset == 0) {
1710 int i;
1711
1712 np->stats.rx_length_errors++;
1713
1714 /* free all rx descriptors related this long pkt */
1715 for (i = 0; i < desno; ++i) {
1716 if (!np->cur_rx->skbuff) {
1717 printk(KERN_DEBUG
1718 "%s: I'm scared\n", dev->name);
1719 break;
1720 }
1721 np->cur_rx->status = RXOWN;
1722 np->cur_rx = np->cur_rx->next_desc_logical;
1723 }
1724 continue;
1725 } else { /* rx error, need to reset this chip */
1726 stop_nic_rx(ioaddr, np->crvalue);
1727 reset_rx_descriptors(dev);
1728 writel(np->crvalue, ioaddr + TCRRCR);
1729 }
1730 break; /* exit the while loop */
1731 }
1732 } else { /* this received pkt is ok */
1733
1734 struct sk_buff *skb;
1735 /* Omit the four octet CRC from the length. */
1736 short pkt_len = ((rx_status & FLNGMASK) >> FLNGShift) - 4;
1737
1738 #ifndef final_version
1739 if (debug)
1740 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1741 " status %x.\n", pkt_len, rx_status);
1742 #endif
1743
1744 /* Check if the packet is long enough to accept without copying
1745 to a minimally-sized skbuff. */
1746 if (pkt_len < rx_copybreak &&
1747 (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1748 skb->dev = dev;
1749 skb_reserve(skb, 2); /* 16 byte align the IP header */
1750 pci_dma_sync_single_for_cpu(np->pci_dev,
1751 np->cur_rx->buffer,
1752 np->rx_buf_sz,
1753 PCI_DMA_FROMDEVICE);
1754 /* Call copy + cksum if available. */
1755
1756 #if ! defined(__alpha__)
1757 eth_copy_and_sum(skb,
1758 np->cur_rx->skbuff->tail, pkt_len, 0);
1759 skb_put(skb, pkt_len);
1760 #else
1761 memcpy(skb_put(skb, pkt_len),
1762 np->cur_rx->skbuff->tail, pkt_len);
1763 #endif
1764 pci_dma_sync_single_for_device(np->pci_dev,
1765 np->cur_rx->buffer,
1766 np->rx_buf_sz,
1767 PCI_DMA_FROMDEVICE);
1768 } else {
1769 pci_unmap_single(np->pci_dev,
1770 np->cur_rx->buffer,
1771 np->rx_buf_sz,
1772 PCI_DMA_FROMDEVICE);
1773 skb_put(skb = np->cur_rx->skbuff, pkt_len);
1774 np->cur_rx->skbuff = NULL;
1775 --np->really_rx_count;
1776 }
1777 skb->protocol = eth_type_trans(skb, dev);
1778 netif_rx(skb);
1779 dev->last_rx = jiffies;
1780 np->stats.rx_packets++;
1781 np->stats.rx_bytes += pkt_len;
1782 }
1783
1784 np->cur_rx = np->cur_rx->next_desc_logical;
1785 } /* end of while loop */
1786
1787 /* allocate skb for rx buffers */
1788 allocate_rx_buffers(dev);
1789
1790 return 0;
1791 }
1792
1793
1794 static struct net_device_stats *get_stats(struct net_device *dev)
1795 {
1796 long ioaddr = dev->base_addr;
1797 struct netdev_private *np = dev->priv;
1798
1799 /* The chip only need report frame silently dropped. */
1800 if (netif_running(dev)) {
1801 np->stats.rx_missed_errors += readl(ioaddr + TALLY) & 0x7fff;
1802 np->stats.rx_crc_errors += (readl(ioaddr + TALLY) & 0x7fff0000) >> 16;
1803 }
1804
1805 return &np->stats;
1806 }
1807
1808
1809 /* for dev->set_multicast_list */
1810 static void set_rx_mode(struct net_device *dev)
1811 {
1812 spinlock_t *lp = &((struct netdev_private *)dev->priv)->lock;
1813 unsigned long flags;
1814 spin_lock_irqsave(lp, flags);
1815 __set_rx_mode(dev);
1816 spin_unlock_irqrestore(lp, flags);
1817 }
1818
1819
1820 /* Take lock before calling */
1821 static void __set_rx_mode(struct net_device *dev)
1822 {
1823 struct netdev_private *np = dev->priv;
1824 long ioaddr = dev->base_addr;
1825 u32 mc_filter[2]; /* Multicast hash filter */
1826 u32 rx_mode;
1827
1828 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1829 /* Unconditionally log net taps. */
1830 printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n", dev->name);
1831 memset(mc_filter, 0xff, sizeof(mc_filter));
1832 rx_mode = CR_W_PROM | CR_W_AB | CR_W_AM;
1833 } else if ((dev->mc_count > multicast_filter_limit)
1834 || (dev->flags & IFF_ALLMULTI)) {
1835 /* Too many to match, or accept all multicasts. */
1836 memset(mc_filter, 0xff, sizeof(mc_filter));
1837 rx_mode = CR_W_AB | CR_W_AM;
1838 } else {
1839 struct dev_mc_list *mclist;
1840 int i;
1841
1842 memset(mc_filter, 0, sizeof(mc_filter));
1843 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1844 i++, mclist = mclist->next) {
1845 unsigned int bit;
1846 bit = (ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26) ^ 0x3F;
1847 mc_filter[bit >> 5] |= (1 << bit);
1848 }
1849 rx_mode = CR_W_AB | CR_W_AM;
1850 }
1851
1852 stop_nic_rxtx(ioaddr, np->crvalue);
1853
1854 writel(mc_filter[0], ioaddr + MAR0);
1855 writel(mc_filter[1], ioaddr + MAR1);
1856 np->crvalue &= ~CR_W_RXMODEMASK;
1857 np->crvalue |= rx_mode;
1858 writel(np->crvalue, ioaddr + TCRRCR);
1859 }
1860
1861 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1862 {
1863 struct netdev_private *np = dev->priv;
1864
1865 strcpy(info->driver, DRV_NAME);
1866 strcpy(info->version, DRV_VERSION);
1867 strcpy(info->bus_info, pci_name(np->pci_dev));
1868 }
1869
1870 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1871 {
1872 struct netdev_private *np = dev->priv;
1873 int rc;
1874
1875 spin_lock_irq(&np->lock);
1876 rc = mii_ethtool_gset(&np->mii, cmd);
1877 spin_unlock_irq(&np->lock);
1878
1879 return rc;
1880 }
1881
1882 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1883 {
1884 struct netdev_private *np = dev->priv;
1885 int rc;
1886
1887 spin_lock_irq(&np->lock);
1888 rc = mii_ethtool_sset(&np->mii, cmd);
1889 spin_unlock_irq(&np->lock);
1890
1891 return rc;
1892 }
1893
1894 static int netdev_nway_reset(struct net_device *dev)
1895 {
1896 struct netdev_private *np = dev->priv;
1897 return mii_nway_restart(&np->mii);
1898 }
1899
1900 static u32 netdev_get_link(struct net_device *dev)
1901 {
1902 struct netdev_private *np = dev->priv;
1903 return mii_link_ok(&np->mii);
1904 }
1905
1906 static u32 netdev_get_msglevel(struct net_device *dev)
1907 {
1908 return debug;
1909 }
1910
1911 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1912 {
1913 debug = value;
1914 }
1915
1916 static struct ethtool_ops netdev_ethtool_ops = {
1917 .get_drvinfo = netdev_get_drvinfo,
1918 .get_settings = netdev_get_settings,
1919 .set_settings = netdev_set_settings,
1920 .nway_reset = netdev_nway_reset,
1921 .get_link = netdev_get_link,
1922 .get_msglevel = netdev_get_msglevel,
1923 .set_msglevel = netdev_set_msglevel,
1924 .get_sg = ethtool_op_get_sg,
1925 .get_tx_csum = ethtool_op_get_tx_csum,
1926 };
1927
1928 static int mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1929 {
1930 struct netdev_private *np = dev->priv;
1931 int rc;
1932
1933 if (!netif_running(dev))
1934 return -EINVAL;
1935
1936 spin_lock_irq(&np->lock);
1937 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
1938 spin_unlock_irq(&np->lock);
1939
1940 return rc;
1941 }
1942
1943
1944 static int netdev_close(struct net_device *dev)
1945 {
1946 long ioaddr = dev->base_addr;
1947 struct netdev_private *np = dev->priv;
1948 int i;
1949
1950 netif_stop_queue(dev);
1951
1952 /* Disable interrupts by clearing the interrupt mask. */
1953 writel(0x0000, ioaddr + IMR);
1954
1955 /* Stop the chip's Tx and Rx processes. */
1956 stop_nic_rxtx(ioaddr, 0);
1957
1958 del_timer_sync(&np->timer);
1959 del_timer_sync(&np->reset_timer);
1960
1961 free_irq(dev->irq, dev);
1962
1963 /* Free all the skbuffs in the Rx queue. */
1964 for (i = 0; i < RX_RING_SIZE; i++) {
1965 struct sk_buff *skb = np->rx_ring[i].skbuff;
1966
1967 np->rx_ring[i].status = 0;
1968 if (skb) {
1969 pci_unmap_single(np->pci_dev, np->rx_ring[i].buffer,
1970 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1971 dev_kfree_skb(skb);
1972 np->rx_ring[i].skbuff = NULL;
1973 }
1974 }
1975
1976 for (i = 0; i < TX_RING_SIZE; i++) {
1977 struct sk_buff *skb = np->tx_ring[i].skbuff;
1978
1979 if (skb) {
1980 pci_unmap_single(np->pci_dev, np->tx_ring[i].buffer,
1981 skb->len, PCI_DMA_TODEVICE);
1982 dev_kfree_skb(skb);
1983 np->tx_ring[i].skbuff = NULL;
1984 }
1985 }
1986
1987 return 0;
1988 }
1989
1990 static struct pci_device_id fealnx_pci_tbl[] = {
1991 {0x1516, 0x0800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1992 {0x1516, 0x0803, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1993 {0x1516, 0x0891, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1994 {} /* terminate list */
1995 };
1996 MODULE_DEVICE_TABLE(pci, fealnx_pci_tbl);
1997
1998
1999 static struct pci_driver fealnx_driver = {
2000 .name = "fealnx",
2001 .id_table = fealnx_pci_tbl,
2002 .probe = fealnx_init_one,
2003 .remove = __devexit_p(fealnx_remove_one),
2004 };
2005
2006 static int __init fealnx_init(void)
2007 {
2008 /* when a module, this is printed whether or not devices are found in probe */
2009 #ifdef MODULE
2010 printk(version);
2011 #endif
2012
2013 return pci_module_init(&fealnx_driver);
2014 }
2015
2016 static void __exit fealnx_exit(void)
2017 {
2018 pci_unregister_driver(&fealnx_driver);
2019 }
2020
2021 module_init(fealnx_init);
2022 module_exit(fealnx_exit);
MOXA 2.6.9 from sdlinux-moxaart.tgz