2 * arch/m68k/q40/config.c
4 * Copyright (C) 1999 Richard Zidlicky
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file README.legal in the main directory of this archive
15 #include <linux/config.h>
16 #include <linux/types.h>
17 #include <linux/kernel.h>
19 #include <linux/tty.h>
20 #include <linux/console.h>
21 #include <linux/linkage.h>
22 #include <linux/init.h>
23 #include <linux/major.h>
24 #include <linux/serial_reg.h>
25 #include <linux/rtc.h>
26 #include <linux/vt_kern.h>
30 #include <asm/bootinfo.h>
31 #include <asm/system.h>
32 #include <asm/pgtable.h>
33 #include <asm/setup.h>
35 #include <asm/traps.h>
37 #include <asm/machdep.h>
38 #include <asm/q40_master.h>
40 extern void floppy_setup(char *str
, int *ints
);
42 extern irqreturn_t
q40_process_int (int level
, struct pt_regs
*regs
);
43 extern irqreturn_t (*q40_default_handler
[]) (int, void *, struct pt_regs
*); /* added just for debugging */
44 extern void q40_init_IRQ (void);
45 extern void q40_free_irq (unsigned int, void *);
46 extern int show_q40_interrupts (struct seq_file
*, void *);
47 extern void q40_enable_irq (unsigned int);
48 extern void q40_disable_irq (unsigned int);
49 static void q40_get_model(char *model
);
50 static int q40_get_hardware_list(char *buffer
);
51 extern int q40_request_irq(unsigned int irq
, irqreturn_t (*handler
)(int, void *, struct pt_regs
*), unsigned long flags
, const char *devname
, void *dev_id
);
52 extern void q40_sched_init(irqreturn_t (*handler
)(int, void *, struct pt_regs
*));
54 extern unsigned long q40_gettimeoffset (void);
55 extern int q40_hwclk (int, struct rtc_time
*);
56 extern unsigned int q40_get_ss (void);
57 extern int q40_set_clock_mmss (unsigned long);
58 static int q40_get_rtc_pll(struct rtc_pll_info
*pll
);
59 static int q40_set_rtc_pll(struct rtc_pll_info
*pll
);
60 extern void q40_reset (void);
62 extern void q40_waitbut(void);
63 void q40_set_vectors (void);
65 extern void q40_mksound(unsigned int /*freq*/, unsigned int /*ticks*/ );
67 extern char m68k_debug_device
[];
68 static void q40_mem_console_write(struct console
*co
, const char *b
,
73 static struct console q40_console_driver
= {
75 .flags
= CON_PRINTBUFFER
,
80 /* early debugging function:*/
81 extern char *q40_mem_cptr
; /*=(char *)0xff020000;*/
84 static void q40_mem_console_write(struct console
*co
, const char *s
,
97 void printq40(char *str
)
100 char *p
=q40_mem_cptr
;
102 while (l
-- >0 && _cpleft
-- >0)
113 #ifdef CONFIG_HEARTBEAT
114 static void q40_heartbeat(int on
)
128 printk ("\n\n*******************************************\n"
129 "Called q40_reset : press the RESET button!! \n"
130 "*******************************************\n");
137 printk ("\n\n*******************\n"
139 "*******************\n");
144 static void q40_get_model(char *model
)
146 sprintf(model
, "Q40");
149 /* No hardware options on Q40? */
151 static int q40_get_hardware_list(char *buffer
)
157 static unsigned int serports
[]={0x3f8,0x2f8,0x3e8,0x2e8,0};
158 void q40_disable_irqs(void)
163 while((i
=serports
[j
++])) outb(0,i
+UART_IER
);
164 master_outb(0,EXT_ENABLE_REG
);
165 master_outb(0,KEY_IRQ_ENABLE_REG
);
168 void __init
config_q40(void)
170 mach_sched_init
= q40_sched_init
;
172 mach_init_IRQ
= q40_init_IRQ
;
173 mach_gettimeoffset
= q40_gettimeoffset
;
174 mach_hwclk
= q40_hwclk
;
175 mach_get_ss
= q40_get_ss
;
176 mach_get_rtc_pll
= q40_get_rtc_pll
;
177 mach_set_rtc_pll
= q40_set_rtc_pll
;
178 mach_set_clock_mmss
= q40_set_clock_mmss
;
180 mach_reset
= q40_reset
;
181 mach_free_irq
= q40_free_irq
;
182 mach_process_int
= q40_process_int
;
183 mach_get_irq_list
= show_q40_interrupts
;
184 mach_request_irq
= q40_request_irq
;
185 enable_irq
= q40_enable_irq
;
186 disable_irq
= q40_disable_irq
;
187 mach_default_handler
= &q40_default_handler
;
188 mach_get_model
= q40_get_model
;
189 mach_get_hardware_list
= q40_get_hardware_list
;
191 #if defined(CONFIG_INPUT_M68K_BEEP) || defined(CONFIG_INPUT_M68K_BEEP_MODULE)
192 mach_beep
= q40_mksound
;
194 #ifdef CONFIG_HEARTBEAT
195 mach_heartbeat
= q40_heartbeat
;
197 mach_halt
= q40_halt
;
198 #ifdef CONFIG_DUMMY_CONSOLE
199 conswitchp
= &dummy_con
;
202 /* disable a few things that SMSQ might have left enabled */
205 /* no DMA at all, but ide-scsi requires it.. make sure
206 * all physical RAM fits into the boundary - otherwise
207 * allocator may play costly and useless tricks */
208 mach_max_dma_address
= 1024*1024*1024;
210 /* useful for early debugging stages - writes kernel messages into SRAM */
211 if (!strncmp( m68k_debug_device
,"mem",3 ))
213 /*printk("using NVRAM debug, q40_mem_cptr=%p\n",q40_mem_cptr);*/
214 _cpleft
=2000-((long)q40_mem_cptr
-0xff020000)/4;
215 q40_console_driver
.write
= q40_mem_console_write
;
216 register_console(&q40_console_driver
);
221 int q40_parse_bootinfo(const struct bi_record
*rec
)
227 static inline unsigned char bcd2bin (unsigned char b
)
229 return ((b
>>4)*10 + (b
&15));
232 static inline unsigned char bin2bcd (unsigned char b
)
234 return (((b
/10)*16) + (b
%10));
238 unsigned long q40_gettimeoffset (void)
240 return 5000*(ql_ticks
!=0);
245 * Looks like op is non-zero for setting the clock, and zero for
248 * struct hwclk_time {
249 * unsigned sec; 0..59
250 * unsigned min; 0..59
251 * unsigned hour; 0..23
252 * unsigned day; 1..31
253 * unsigned mon; 0..11
254 * unsigned year; 00...
255 * int wday; 0..6, 0 is Sunday, -1 means unknown/don't set
259 int q40_hwclk(int op
, struct rtc_time
*t
)
263 Q40_RTC_CTRL
|= Q40_RTC_WRITE
;
265 Q40_RTC_SECS
= bin2bcd(t
->tm_sec
);
266 Q40_RTC_MINS
= bin2bcd(t
->tm_min
);
267 Q40_RTC_HOUR
= bin2bcd(t
->tm_hour
);
268 Q40_RTC_DATE
= bin2bcd(t
->tm_mday
);
269 Q40_RTC_MNTH
= bin2bcd(t
->tm_mon
+ 1);
270 Q40_RTC_YEAR
= bin2bcd(t
->tm_year
%100);
272 Q40_RTC_DOW
= bin2bcd(t
->tm_wday
+1);
274 Q40_RTC_CTRL
&= ~(Q40_RTC_WRITE
);
278 Q40_RTC_CTRL
|= Q40_RTC_READ
;
280 t
->tm_year
= bcd2bin (Q40_RTC_YEAR
);
281 t
->tm_mon
= bcd2bin (Q40_RTC_MNTH
)-1;
282 t
->tm_mday
= bcd2bin (Q40_RTC_DATE
);
283 t
->tm_hour
= bcd2bin (Q40_RTC_HOUR
);
284 t
->tm_min
= bcd2bin (Q40_RTC_MINS
);
285 t
->tm_sec
= bcd2bin (Q40_RTC_SECS
);
287 Q40_RTC_CTRL
&= ~(Q40_RTC_READ
);
291 t
->tm_wday
= bcd2bin(Q40_RTC_DOW
)-1;
298 unsigned int q40_get_ss(void)
300 return bcd2bin(Q40_RTC_SECS
);
304 * Set the minutes and seconds from seconds value 'nowtime'. Fail if
305 * clock is out by > 30 minutes. Logic lifted from atari code.
308 int q40_set_clock_mmss (unsigned long nowtime
)
311 short real_seconds
= nowtime
% 60, real_minutes
= (nowtime
/ 60) % 60;
316 rtc_minutes
= bcd2bin (Q40_RTC_MINS
);
318 if ((rtc_minutes
< real_minutes
319 ? real_minutes
- rtc_minutes
320 : rtc_minutes
- real_minutes
) < 30)
322 Q40_RTC_CTRL
|= Q40_RTC_WRITE
;
323 Q40_RTC_MINS
= bin2bcd(real_minutes
);
324 Q40_RTC_SECS
= bin2bcd(real_seconds
);
325 Q40_RTC_CTRL
&= ~(Q40_RTC_WRITE
);
335 /* get and set PLL calibration of RTC clock */
336 #define Q40_RTC_PLL_MASK ((1<<5)-1)
337 #define Q40_RTC_PLL_SIGN (1<<5)
339 static int q40_get_rtc_pll(struct rtc_pll_info
*pll
)
341 int tmp
=Q40_RTC_CTRL
;
342 pll
->pll_value
= tmp
& Q40_RTC_PLL_MASK
;
343 if (tmp
& Q40_RTC_PLL_SIGN
)
344 pll
->pll_value
= -pll
->pll_value
;
347 pll
->pll_posmult
=512;
348 pll
->pll_negmult
=256;
349 pll
->pll_clock
=125829120;
353 static int q40_set_rtc_pll(struct rtc_pll_info
*pll
)
356 /* the docs are a bit unclear so I am doublesetting */
357 /* RTC_WRITE here ... */
358 int tmp
= (pll
->pll_value
& 31) | (pll
->pll_value
<0 ? 32 : 0) |
360 Q40_RTC_CTRL
|= Q40_RTC_WRITE
;
362 Q40_RTC_CTRL
&= ~(Q40_RTC_WRITE
);