2 * linux/arch/arm/mm/proc-fa526.S: MMU functions for FA526
4 * Copyright (C) 2005 Faraday Corp.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * These are the low level assembler for performing cache and TLB
22 * functions on the fa526.
24 * Written by : Luke Lee
26 #include <linux/linkage.h>
27 #include <linux/config.h>
28 #include <linux/init.h>
29 #include <asm/assembler.h>
30 #include <asm/pgtable.h>
31 #include <asm/procinfo.h>
32 #include <asm/hardware.h>
34 #include <asm/ptrace.h>
35 #include <asm/system.h>
36 #include "proc-macros.S"
38 #define CACHE_DLINESIZE 16
42 * cpu_fa526_proc_init()
44 ENTRY(cpu_fa526_proc_init)
45 /* MMU is already ON here, ICACHE, DCACHE conditionally disabled */
50 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
54 mrc p15, 0, r0, c1, c0, 0 @ read ctrl register
56 #ifdef CONFIG_CPU_FA_BTB
61 #ifdef CONFIG_CPU_FA_WB_DISABLE
63 mcr p15, 0, r1, c7, c10, 4 @ drain write buffer
70 #ifdef CONFIG_CPU_DCACHE_DISABLE
75 #ifdef CONFIG_CPU_ICACHE_DISABLE
83 mcr p15, 0, r0, c1, c0, 0
88 bl fa_initialize_cache_info @ destroy r0~r4
93 * cpu_fa526_proc_fin()
95 ENTRY(cpu_fa526_proc_fin)
97 mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE
100 bl fa_flush_kern_cache_all
101 mrc p15, 0, r0, c1, c0, 0 @ ctrl register
102 bic r0, r0, #0x1000 @ ...i............
103 bic r0, r0, #0x000e @ ............wca.
104 mcr p15, 0, r0, c1, c0, 0 @ disable caches
111 * cpu_fa526_reset(loc)
113 * Perform a soft reset of the system. Put the CPU into the
114 * same state as it would be if it had been reset, and branch
115 * to what would be the reset vector.
117 * loc: location to jump to for soft reset
120 ENTRY(cpu_fa526_reset)
122 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
123 #ifndef CONFIG_CPU_FA_WB_DISABLE
124 mcr p15, 0, ip, c7, c10, 4 @ drain WB
126 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
127 mrc p15, 0, ip, c1, c0, 0 @ ctrl register
128 bic ip, ip, #0x000f @ ............wcam
129 bic ip, ip, #0x1100 @ ...i...s........
131 bic ip, ip, #0x0800 @ BTB off
132 mcr p15, 0, ip, c1, c0, 0 @ ctrl register
138 * cpu_fa526_do_idle()
141 ENTRY(cpu_fa526_do_idle)
143 #ifdef CONFIG_CPU_FA_IDLE
146 mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt (IDLE mode)
151 ENTRY(cpu_fa526_dcache_clean_area)
153 #ifndef CONFIG_CPU_DCACHE_DISABLE
154 #ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
155 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
156 add r0, r0, #CACHE_DLINESIZE
157 subs r1, r1, #CACHE_DLINESIZE
164 /* =============================== PageTable ============================== */
167 * cpu_fa526_switch_mm(pgd)
169 * Set the translation base pointer to be as described by pgd.
171 * pgd: new page tables
179 ENTRY(cpu_fa526_switch_mm)
182 #ifndef CONFIG_CPU_DCACHE_DISABLE
183 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
184 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
186 mcr p15, 0, ip, c7, c14, 0 @ Clean and invalidate whole DCache
188 #endif /*CONFIG_CPU_DCACHE_DISABLE*/
190 #ifndef CONFIG_CPU_ICACHE_DISABLE
191 mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
194 #ifndef CONFIG_CPU_FA_WB_DISABLE
195 mcr p15, 0, ip, c7, c10, 4 @ drain WB
198 #ifdef CONFIG_CPU_FA_BTB
199 mcr p15, 0, ip, c7, c5, 6 @ invalidate BTB since mm changed
203 bic r0, r0, #0xff @ clear bits [7:0]
204 bic r0, r0, #0x3f00 @ clear bits [13:8]
205 mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
206 mcr p15, 0, ip, c8, c7, 0 @ invalidate UTLB
212 * cpu_fa526_set_pte(ptep, pte)
214 * Set a PTE and flush it out
217 ENTRY(cpu_fa526_set_pte)
218 str r1, [r0], #-2048 @ linux version
220 eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY
222 bic r2, r1, #PTE_SMALL_AP_MASK
223 bic r2, r2, #PTE_TYPE_MASK
224 orr r2, r2, #PTE_TYPE_SMALL
226 tst r1, #L_PTE_USER @ User?
227 orrne r2, r2, #PTE_SMALL_AP_URO_SRW
229 tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty?
230 orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
232 tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young?
235 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
236 eor r3, r2, #0x0a @ C & small page? 1010
240 str r2, [r0] @ hardware version
243 mcr p15, 0, r2, c7, c10, 0 @ clean D cache all
245 #ifndef CONFIG_CPU_FA_WB_DISABLE
246 mcr p15, 0, r2, c7, c10, 4 @ drain WB
248 #ifdef CONFIG_CPU_FA_BTB
249 mcr p15, 0, r2, c7, c5, 6 @ invalidate BTB
257 .type __fa526_setup, #function
259 /* On return of this routine, r0 must carry correct flags for CFG register */
261 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
262 mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
263 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
265 mcr p15, 0, r0, c7, c5, 5 @ invalidate IScratchpad RAM
268 mcr p15, 0, r0, c1, c1, 0 @ turn-on ECR
270 mrc p15, 0, r0, c9, c1, 0 @ DScratchpad
272 mcr p15, 0, r0, c9, c1, 0
273 mrc p15, 0, r0, c9, c1, 1 @ IScratchpad
275 mcr p15, 0, r0, c9, c1, 1
278 mcr p15, 0, r0, c1, c1, 0 @ turn-off ECR
280 #ifdef CONFIG_CPU_FA_BTB
281 mcr p15, 0, r0, c7, c5, 6 @ invalidate BTB All
286 mov r0, #0x1f @ Domains 0, 1 = manager, 2 = client
287 mcr p15, 0, r0, c3, c0 @ load domain access register
289 mrc p15, 0, r0, c1, c0 @ get control register v4
292 ldr r5, fa526_cr1_clear
294 ldr r5, fa526_cr1_set
297 ldr r0, fa526_victor_set
302 bic r0, r0, #0x1000 @ ...0 000. .... 000.
304 orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1
306 #ifndef CONFIG_CPU_DCACHE_DISABLE
307 orr r0, r0, #0x0004 @ .... .... .... .1..
309 #ifndef CONFIG_CPU_ICACHE_DISABLE
310 orr r0, r0, #0x1000 @ ...1 .... .... ....
314 #ifdef CONFIG_CPU_FA_BTB
320 #ifdef CONFIG_CPU_FA_WB_DISABLE
322 mcr p15, 0, r12, c7, c10, 4 @ drain write buffer
325 bic r0, r0, #CR_W @ .... .... .... 1...
332 .size __fa526_setup, . - __fa526_setup
335 * .RVI ZFRS BLDP WCAM
336 * ..11 0001 .111 1101
339 .type fa526_cr1_clear, #object
340 .type fa526_cr1_set, #object
351 * Purpose : Function pointers used to access above functions - all calls
354 .type fa526_processor_functions, #object
355 fa526_processor_functions:
357 .word cpu_fa526_proc_init
358 .word cpu_fa526_proc_fin
359 .word cpu_fa526_reset
360 .word cpu_fa526_do_idle
361 .word cpu_fa526_dcache_clean_area
362 .word cpu_fa526_switch_mm
363 .word cpu_fa526_set_pte
364 .size fa526_processor_functions, . - fa526_processor_functions
368 .type cpu_arch_name, #object
371 .size cpu_arch_name, . - cpu_arch_name
373 .type cpu_elf_name, #object
376 .size cpu_elf_name, . - cpu_elf_name
378 .type cpu_fa526_name, #object
381 #ifndef CONFIG_CPU_ICACHE_DISABLE
384 #ifndef CONFIG_CPU_DCACHE_DISABLE
386 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
393 .size cpu_fa526_name, . - cpu_fa526_name
397 .section ".proc.info", #alloc, #execinstr
399 #ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
400 #define __PMD_SECT_BUFFERABLE 0
402 #define __PMD_SECT_BUFFERABLE PMD_SECT_BUFFERABLE
405 .type __fa526_proc_info,#object
410 .long PMD_TYPE_SECT | \
411 __PMD_SECT_BUFFERABLE | \
412 PMD_SECT_CACHEABLE | \
414 PMD_SECT_AP_WRITE | \
422 .long HWCAP_SWP | HWCAP_HALF
424 .long fa526_processor_functions
428 .size __fa526_proc_info, . - __fa526_proc_info