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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / sound / pci / emu10k1 / emu10k1_main.c
blob4f7a0ea6075454bc3e219b6a50150c2d3c14f99c
1 /*
2 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
3 * Creative Labs, Inc.
4 * Routines for control of EMU10K1 chips
5 *
6 * BUGS:
7 * --
8 *
9 * TODO:
10 * --
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 #include <sound/driver.h>
29 #include <linux/delay.h>
30 #include <linux/init.h>
31 #include <linux/interrupt.h>
32 #include <linux/pci.h>
33 #include <linux/slab.h>
34 #include <linux/vmalloc.h>
35
36 #include <sound/core.h>
37 #include <sound/emu10k1.h>
38
39 #if 0
40 MODULE_AUTHOR("Jaroslav Kysela <perex@suse.cz>, Creative Labs, Inc.");
41 MODULE_DESCRIPTION("Routines for control of EMU10K1 chips");
42 MODULE_LICENSE("GPL");
43 #endif
44
45 /*************************************************************************
46 * EMU10K1 init / done
47 *************************************************************************/
48
49 void snd_emu10k1_voice_init(emu10k1_t * emu, int ch)
50 {
51 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
52 snd_emu10k1_ptr_write(emu, IP, ch, 0);
53 snd_emu10k1_ptr_write(emu, VTFT, ch, 0xffff);
54 snd_emu10k1_ptr_write(emu, CVCF, ch, 0xffff);
55 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
56 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
57 snd_emu10k1_ptr_write(emu, CCR, ch, 0);
58
59 snd_emu10k1_ptr_write(emu, PSST, ch, 0);
60 snd_emu10k1_ptr_write(emu, DSL, ch, 0x10);
61 snd_emu10k1_ptr_write(emu, CCCA, ch, 0);
62 snd_emu10k1_ptr_write(emu, Z1, ch, 0);
63 snd_emu10k1_ptr_write(emu, Z2, ch, 0);
64 snd_emu10k1_ptr_write(emu, FXRT, ch, 0x32100000);
65
66 snd_emu10k1_ptr_write(emu, ATKHLDM, ch, 0);
67 snd_emu10k1_ptr_write(emu, DCYSUSM, ch, 0);
68 snd_emu10k1_ptr_write(emu, IFATN, ch, 0xffff);
69 snd_emu10k1_ptr_write(emu, PEFE, ch, 0);
70 snd_emu10k1_ptr_write(emu, FMMOD, ch, 0);
71 snd_emu10k1_ptr_write(emu, TREMFRQ, ch, 24); /* 1 Hz */
72 snd_emu10k1_ptr_write(emu, FM2FRQ2, ch, 24); /* 1 Hz */
73 snd_emu10k1_ptr_write(emu, TEMPENV, ch, 0);
74
75 /*** these are last so OFF prevents writing ***/
76 snd_emu10k1_ptr_write(emu, LFOVAL2, ch, 0);
77 snd_emu10k1_ptr_write(emu, LFOVAL1, ch, 0);
78 snd_emu10k1_ptr_write(emu, ATKHLDV, ch, 0);
79 snd_emu10k1_ptr_write(emu, ENVVOL, ch, 0);
80 snd_emu10k1_ptr_write(emu, ENVVAL, ch, 0);
81
82 /* Audigy extra stuffs */
83 if (emu->audigy) {
84 snd_emu10k1_ptr_write(emu, 0x4c, ch, 0); /* ?? */
85 snd_emu10k1_ptr_write(emu, 0x4d, ch, 0); /* ?? */
86 snd_emu10k1_ptr_write(emu, 0x4e, ch, 0); /* ?? */
87 snd_emu10k1_ptr_write(emu, 0x4f, ch, 0); /* ?? */
88 snd_emu10k1_ptr_write(emu, A_FXRT1, ch, 0x03020100);
89 snd_emu10k1_ptr_write(emu, A_FXRT2, ch, 0x3f3f3f3f);
90 snd_emu10k1_ptr_write(emu, A_SENDAMOUNTS, ch, 0);
91 }
92 }
93
94 static int __devinit snd_emu10k1_init(emu10k1_t * emu, int enable_ir)
95 {
96 int ch, idx, err;
97 unsigned int silent_page;
98
99 emu->fx8010.itram_size = (16 * 1024)/2;
100 emu->fx8010.etram_pages.area = NULL;
101 emu->fx8010.etram_pages.bytes = 0;
102
103 /* disable audio and lock cache */
104 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
105
106 /* reset recording buffers */
107 snd_emu10k1_ptr_write(emu, MICBS, 0, ADCBS_BUFSIZE_NONE);
108 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
109 snd_emu10k1_ptr_write(emu, FXBS, 0, ADCBS_BUFSIZE_NONE);
110 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
111 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
112 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
113
114 /* disable channel interrupt */
115 outl(0, emu->port + INTE);
116 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
117 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
118 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
119 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
120
121 if (emu->audigy){
122 /* set SPDIF bypass mode */
123 snd_emu10k1_ptr_write(emu, SPBYPASS, 0, SPBYPASS_FORMAT);
124 /* enable rear left + rear right AC97 slots */
125 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_REAR_RIGHT | AC97SLOT_REAR_LEFT);
126 }
127
128 /* init envelope engine */
129 for (ch = 0; ch < NUM_G; ch++) {
130 emu->voices[ch].emu = emu;
131 emu->voices[ch].number = ch;
132 snd_emu10k1_voice_init(emu, ch);
133 }
134
135 /*
136 * Init to 0x02109204 :
137 * Clock accuracy = 0 (1000ppm)
138 * Sample Rate = 2 (48kHz)
139 * Audio Channel = 1 (Left of 2)
140 * Source Number = 0 (Unspecified)
141 * Generation Status = 1 (Original for Cat Code 12)
142 * Cat Code = 12 (Digital Signal Mixer)
143 * Mode = 0 (Mode 0)
144 * Emphasis = 0 (None)
145 * CP = 1 (Copyright unasserted)
146 * AN = 0 (Audio data)
147 * P = 0 (Consumer)
148 */
149 snd_emu10k1_ptr_write(emu, SPCS0, 0,
150 emu->spdif_bits[0] =
151 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
152 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
153 SPCS_GENERATIONSTATUS | 0x00001200 |
154 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
155 snd_emu10k1_ptr_write(emu, SPCS1, 0,
156 emu->spdif_bits[1] =
157 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
158 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
159 SPCS_GENERATIONSTATUS | 0x00001200 |
160 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
161 snd_emu10k1_ptr_write(emu, SPCS2, 0,
162 emu->spdif_bits[2] =
163 SPCS_CLKACCY_1000PPM | SPCS_SAMPLERATE_48 |
164 SPCS_CHANNELNUM_LEFT | SPCS_SOURCENUM_UNSPEC |
165 SPCS_GENERATIONSTATUS | 0x00001200 |
166 0x00000000 | SPCS_EMPHASIS_NONE | SPCS_COPYRIGHT);
167
168 if (emu->audigy && emu->revision == 4) { /* audigy2 */
169 /* Hacks for Alice3 to work independent of haP16V driver */
170 u32 tmp;
171
172 //Setup SRCMulti_I2S SamplingRate
173 tmp = snd_emu10k1_ptr_read(emu, A_SPDIF_SAMPLERATE, 0);
174 tmp &= 0xfffff1ff;
175 tmp |= (0x2<<9);
176 snd_emu10k1_ptr_write(emu, A_SPDIF_SAMPLERATE, 0, tmp);
177
178 /* Setup SRCSel (Enable Spdif,I2S SRCMulti) */
179 outl(0x600000, emu->port + 0x20);
180 outl(0x14, emu->port + 0x24);
181
182 /* Setup SRCMulti Input Audio Enable */
183 outl(0x6E0000, emu->port + 0x20);
184 outl(0xFF00FF00, emu->port + 0x24);
185 }
186
187 /*
188 * Clear page with silence & setup all pointers to this page
189 */
190 memset(emu->silent_page.area, 0, PAGE_SIZE);
191 silent_page = emu->silent_page.addr << 1;
192 for (idx = 0; idx < MAXPAGES; idx++)
193 ((u32 *)emu->ptb_pages.area)[idx] = cpu_to_le32(silent_page | idx);
194 snd_emu10k1_ptr_write(emu, PTB, 0, emu->ptb_pages.addr);
195 snd_emu10k1_ptr_write(emu, TCB, 0, 0); /* taken from original driver */
196 snd_emu10k1_ptr_write(emu, TCBS, 0, 4); /* taken from original driver */
197
198 silent_page = (emu->silent_page.addr << 1) | MAP_PTI_MASK;
199 for (ch = 0; ch < NUM_G; ch++) {
200 snd_emu10k1_ptr_write(emu, MAPA, ch, silent_page);
201 snd_emu10k1_ptr_write(emu, MAPB, ch, silent_page);
202 }
203
204 /*
205 * Hokay, setup HCFG
206 * Mute Disable Audio = 0
207 * Lock Tank Memory = 1
208 * Lock Sound Memory = 0
209 * Auto Mute = 1
210 */
211 if (emu->audigy) {
212 if (emu->revision == 4) /* audigy2 */
213 outl(HCFG_AUDIOENABLE |
214 HCFG_AC3ENABLE_CDSPDIF |
215 HCFG_AC3ENABLE_GPSPDIF |
216 HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
217 else
218 outl(HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
219 } else if (emu->model == 0x20 ||
220 emu->model == 0xc400 ||
221 (emu->model == 0x21 && emu->revision < 6))
222 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE, emu->port + HCFG);
223 else
224 // With on-chip joystick
225 outl(HCFG_LOCKTANKCACHE_MASK | HCFG_AUTOMUTE | HCFG_JOYENABLE, emu->port + HCFG);
226
227 if (enable_ir) { /* enable IR for SB Live */
228 if (emu->audigy) {
229 unsigned int reg = inl(emu->port + A_IOCFG);
230 outl(reg | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
231 udelay(500);
232 outl(reg | A_IOCFG_GPOUT1 | A_IOCFG_GPOUT2, emu->port + A_IOCFG);
233 udelay(100);
234 outl(reg, emu->port + A_IOCFG);
235 } else {
236 unsigned int reg = inl(emu->port + HCFG);
237 outl(reg | HCFG_GPOUT2, emu->port + HCFG);
238 udelay(500);
239 outl(reg | HCFG_GPOUT1 | HCFG_GPOUT2, emu->port + HCFG);
240 udelay(100);
241 outl(reg, emu->port + HCFG);
242 }
243 }
244
245 if (emu->audigy) { /* enable analog output */
246 unsigned int reg = inl(emu->port + A_IOCFG);
247 outl(reg | A_IOCFG_GPOUT0, emu->port + A_IOCFG);
248 }
249
250 /*
251 * Initialize the effect engine
252 */
253 if ((err = snd_emu10k1_init_efx(emu)) < 0)
254 return err;
255
256 /*
257 * Enable the audio bit
258 */
259 outl(inl(emu->port + HCFG) | HCFG_AUDIOENABLE, emu->port + HCFG);
260
261 /* Enable analog/digital outs on audigy */
262 if (emu->audigy) {
263 outl(inl(emu->port + A_IOCFG) & ~0x44, emu->port + A_IOCFG);
264
265 if (emu->revision == 4) { /* audigy2 */
266 /* Unmute Analog now. Set GPO6 to 1 for Apollo.
267 * This has to be done after init ALice3 I2SOut beyond 48KHz.
268 * So, sequence is important. */
269 outl(inl(emu->port + A_IOCFG) | 0x0040, emu->port + A_IOCFG);
270 } else {
271 /* Disable routing from AC97 line out to Front speakers */
272 outl(inl(emu->port + A_IOCFG) | 0x0080, emu->port + A_IOCFG);
273 }
274 }
275
276 #if 0
277 {
278 unsigned int tmp;
279 /* FIXME: the following routine disables LiveDrive-II !! */
280 // TOSLink detection
281 emu->tos_link = 0;
282 tmp = inl(emu->port + HCFG);
283 if (tmp & (HCFG_GPINPUT0 | HCFG_GPINPUT1)) {
284 outl(tmp|0x800, emu->port + HCFG);
285 udelay(50);
286 if (tmp != (inl(emu->port + HCFG) & ~0x800)) {
287 emu->tos_link = 1;
288 outl(tmp, emu->port + HCFG);
289 }
290 }
291 }
292 #endif
293
294 snd_emu10k1_intr_enable(emu, INTE_PCIERRORENABLE);
295
296 emu->reserved_page = (emu10k1_memblk_t *)snd_emu10k1_synth_alloc(emu, 4096);
297 if (emu->reserved_page)
298 emu->reserved_page->map_locked = 1;
299
300 return 0;
301 }
302
303 static int snd_emu10k1_done(emu10k1_t * emu)
304 {
305 int ch;
306
307 outl(0, emu->port + INTE);
308
309 /*
310 * Shutdown the chip
311 */
312 for (ch = 0; ch < NUM_G; ch++)
313 snd_emu10k1_ptr_write(emu, DCYSUSV, ch, 0);
314 for (ch = 0; ch < NUM_G; ch++) {
315 snd_emu10k1_ptr_write(emu, VTFT, ch, 0);
316 snd_emu10k1_ptr_write(emu, CVCF, ch, 0);
317 snd_emu10k1_ptr_write(emu, PTRX, ch, 0);
318 snd_emu10k1_ptr_write(emu, CPF, ch, 0);
319 }
320
321 /* reset recording buffers */
322 snd_emu10k1_ptr_write(emu, MICBS, 0, 0);
323 snd_emu10k1_ptr_write(emu, MICBA, 0, 0);
324 snd_emu10k1_ptr_write(emu, FXBS, 0, 0);
325 snd_emu10k1_ptr_write(emu, FXBA, 0, 0);
326 snd_emu10k1_ptr_write(emu, FXWC, 0, 0);
327 snd_emu10k1_ptr_write(emu, ADCBS, 0, ADCBS_BUFSIZE_NONE);
328 snd_emu10k1_ptr_write(emu, ADCBA, 0, 0);
329 snd_emu10k1_ptr_write(emu, TCBS, 0, TCBS_BUFFSIZE_16K);
330 snd_emu10k1_ptr_write(emu, TCB, 0, 0);
331 if (emu->audigy)
332 snd_emu10k1_ptr_write(emu, A_DBG, 0, A_DBG_SINGLE_STEP);
333 else
334 snd_emu10k1_ptr_write(emu, DBG, 0, EMU10K1_DBG_SINGLE_STEP);
335
336 /* disable channel interrupt */
337 snd_emu10k1_ptr_write(emu, CLIEL, 0, 0);
338 snd_emu10k1_ptr_write(emu, CLIEH, 0, 0);
339 snd_emu10k1_ptr_write(emu, SOLEL, 0, 0);
340 snd_emu10k1_ptr_write(emu, SOLEH, 0, 0);
341
342 /* remove reserved page */
343 if (emu->reserved_page != NULL) {
344 snd_emu10k1_synth_free(emu, (snd_util_memblk_t *)emu->reserved_page);
345 emu->reserved_page = NULL;
346 }
347
348 /* disable audio and lock cache */
349 outl(HCFG_LOCKSOUNDCACHE | HCFG_LOCKTANKCACHE_MASK | HCFG_MUTEBUTTONENABLE, emu->port + HCFG);
350 snd_emu10k1_ptr_write(emu, PTB, 0, 0);
351
352 snd_emu10k1_free_efx(emu);
353
354 return 0;
355 }
356
357 /*************************************************************************
358 * ECARD functional implementation
359 *************************************************************************/
360
361 /* In A1 Silicon, these bits are in the HC register */
362 #define HOOKN_BIT (1L << 12)
363 #define HANDN_BIT (1L << 11)
364 #define PULSEN_BIT (1L << 10)
365
366 #define EC_GDI1 (1 << 13)
367 #define EC_GDI0 (1 << 14)
368
369 #define EC_NUM_CONTROL_BITS 20
370
371 #define EC_AC3_DATA_SELN 0x0001L
372 #define EC_EE_DATA_SEL 0x0002L
373 #define EC_EE_CNTRL_SELN 0x0004L
374 #define EC_EECLK 0x0008L
375 #define EC_EECS 0x0010L
376 #define EC_EESDO 0x0020L
377 #define EC_TRIM_CSN 0x0040L
378 #define EC_TRIM_SCLK 0x0080L
379 #define EC_TRIM_SDATA 0x0100L
380 #define EC_TRIM_MUTEN 0x0200L
381 #define EC_ADCCAL 0x0400L
382 #define EC_ADCRSTN 0x0800L
383 #define EC_DACCAL 0x1000L
384 #define EC_DACMUTEN 0x2000L
385 #define EC_LEDN 0x4000L
386
387 #define EC_SPDIF0_SEL_SHIFT 15
388 #define EC_SPDIF1_SEL_SHIFT 17
389 #define EC_SPDIF0_SEL_MASK (0x3L << EC_SPDIF0_SEL_SHIFT)
390 #define EC_SPDIF1_SEL_MASK (0x7L << EC_SPDIF1_SEL_SHIFT)
391 #define EC_SPDIF0_SELECT(_x) (((_x) << EC_SPDIF0_SEL_SHIFT) & EC_SPDIF0_SEL_MASK)
392 #define EC_SPDIF1_SELECT(_x) (((_x) << EC_SPDIF1_SEL_SHIFT) & EC_SPDIF1_SEL_MASK)
393 #define EC_CURRENT_PROM_VERSION 0x01 /* Self-explanatory. This should
394 * be incremented any time the EEPROM's
395 * format is changed. */
396
397 #define EC_EEPROM_SIZE 0x40 /* ECARD EEPROM has 64 16-bit words */
398
399 /* Addresses for special values stored in to EEPROM */
400 #define EC_PROM_VERSION_ADDR 0x20 /* Address of the current prom version */
401 #define EC_BOARDREV0_ADDR 0x21 /* LSW of board rev */
402 #define EC_BOARDREV1_ADDR 0x22 /* MSW of board rev */
403
404 #define EC_LAST_PROMFILE_ADDR 0x2f
405
406 #define EC_SERIALNUM_ADDR 0x30 /* First word of serial number. The
407 * can be up to 30 characters in length
408 * and is stored as a NULL-terminated
409 * ASCII string. Any unused bytes must be
410 * filled with zeros */
411 #define EC_CHECKSUM_ADDR 0x3f /* Location at which checksum is stored */
412
413
414 /* Most of this stuff is pretty self-evident. According to the hardware
415 * dudes, we need to leave the ADCCAL bit low in order to avoid a DC
416 * offset problem. Weird.
417 */
418 #define EC_RAW_RUN_MODE (EC_DACMUTEN | EC_ADCRSTN | EC_TRIM_MUTEN | \
419 EC_TRIM_CSN)
420
421
422 #define EC_DEFAULT_ADC_GAIN 0xC4C4
423 #define EC_DEFAULT_SPDIF0_SEL 0x0
424 #define EC_DEFAULT_SPDIF1_SEL 0x4
425
426 /**************************************************************************
427 * @func Clock bits into the Ecard's control latch. The Ecard uses a
428 * control latch will is loaded bit-serially by toggling the Modem control
429 * lines from function 2 on the E8010. This function hides these details
430 * and presents the illusion that we are actually writing to a distinct
431 * register.
432 */
433
434 static void snd_emu10k1_ecard_write(emu10k1_t * emu, unsigned int value)
435 {
436 unsigned short count;
437 unsigned int data;
438 unsigned long hc_port;
439 unsigned int hc_value;
440
441 hc_port = emu->port + HCFG;
442 hc_value = inl(hc_port) & ~(HOOKN_BIT | HANDN_BIT | PULSEN_BIT);
443 outl(hc_value, hc_port);
444
445 for (count = 0; count < EC_NUM_CONTROL_BITS; count++) {
446
447 /* Set up the value */
448 data = ((value & 0x1) ? PULSEN_BIT : 0);
449 value >>= 1;
450
451 outl(hc_value | data, hc_port);
452
453 /* Clock the shift register */
454 outl(hc_value | data | HANDN_BIT, hc_port);
455 outl(hc_value | data, hc_port);
456 }
457
458 /* Latch the bits */
459 outl(hc_value | HOOKN_BIT, hc_port);
460 outl(hc_value, hc_port);
461 }
462
463 /**************************************************************************
464 * @func Set the gain of the ECARD's CS3310 Trim/gain controller. The
465 * trim value consists of a 16bit value which is composed of two
466 * 8 bit gain/trim values, one for the left channel and one for the
467 * right channel. The following table maps from the Gain/Attenuation
468 * value in decibels into the corresponding bit pattern for a single
469 * channel.
470 */
471
472 static void snd_emu10k1_ecard_setadcgain(emu10k1_t * emu,
473 unsigned short gain)
474 {
475 unsigned int bit;
476
477 /* Enable writing to the TRIM registers */
478 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
479
480 /* Do it again to insure that we meet hold time requirements */
481 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl & ~EC_TRIM_CSN);
482
483 for (bit = (1 << 15); bit; bit >>= 1) {
484 unsigned int value;
485
486 value = emu->ecard_ctrl & ~(EC_TRIM_CSN | EC_TRIM_SDATA);
487
488 if (gain & bit)
489 value |= EC_TRIM_SDATA;
490
491 /* Clock the bit */
492 snd_emu10k1_ecard_write(emu, value);
493 snd_emu10k1_ecard_write(emu, value | EC_TRIM_SCLK);
494 snd_emu10k1_ecard_write(emu, value);
495 }
496
497 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
498 }
499
500 static int __devinit snd_emu10k1_ecard_init(emu10k1_t * emu)
501 {
502 unsigned int hc_value;
503
504 /* Set up the initial settings */
505 emu->ecard_ctrl = EC_RAW_RUN_MODE |
506 EC_SPDIF0_SELECT(EC_DEFAULT_SPDIF0_SEL) |
507 EC_SPDIF1_SELECT(EC_DEFAULT_SPDIF1_SEL);
508
509 /* Step 0: Set the codec type in the hardware control register
510 * and enable audio output */
511 hc_value = inl(emu->port + HCFG);
512 outl(hc_value | HCFG_AUDIOENABLE | HCFG_CODECFORMAT_I2S, emu->port + HCFG);
513 inl(emu->port + HCFG);
514
515 /* Step 1: Turn off the led and deassert TRIM_CS */
516 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
517
518 /* Step 2: Calibrate the ADC and DAC */
519 snd_emu10k1_ecard_write(emu, EC_DACCAL | EC_LEDN | EC_TRIM_CSN);
520
521 /* Step 3: Wait for awhile; XXX We can't get away with this
522 * under a real operating system; we'll need to block and wait that
523 * way. */
524 snd_emu10k1_wait(emu, 48000);
525
526 /* Step 4: Switch off the DAC and ADC calibration. Note
527 * That ADC_CAL is actually an inverted signal, so we assert
528 * it here to stop calibration. */
529 snd_emu10k1_ecard_write(emu, EC_ADCCAL | EC_LEDN | EC_TRIM_CSN);
530
531 /* Step 4: Switch into run mode */
532 snd_emu10k1_ecard_write(emu, emu->ecard_ctrl);
533
534 /* Step 5: Set the analog input gain */
535 snd_emu10k1_ecard_setadcgain(emu, EC_DEFAULT_ADC_GAIN);
536
537 return 0;
538 }
539
540 /*
541 * Create the EMU10K1 instance
542 */
543
544 static int snd_emu10k1_free(emu10k1_t *emu)
545 {
546 if (emu->port) { /* avoid access to already used hardware */
547 snd_emu10k1_fx8010_tram_setup(emu, 0);
548 snd_emu10k1_done(emu);
549 }
550 if (emu->memhdr)
551 snd_util_memhdr_free(emu->memhdr);
552 if (emu->silent_page.area)
553 snd_dma_free_pages(&emu->silent_page);
554 if (emu->ptb_pages.area)
555 snd_dma_free_pages(&emu->ptb_pages);
556 if (emu->page_ptr_table)
557 vfree(emu->page_ptr_table);
558 if (emu->page_addr_table)
559 vfree(emu->page_addr_table);
560 if (emu->irq >= 0)
561 free_irq(emu->irq, (void *)emu);
562 if (emu->port)
563 pci_release_regions(emu->pci);
564 kfree(emu);
565 return 0;
566 }
567
568 static int snd_emu10k1_dev_free(snd_device_t *device)
569 {
570 emu10k1_t *emu = device->device_data;
571 return snd_emu10k1_free(emu);
572 }
573
574 int __devinit snd_emu10k1_create(snd_card_t * card,
575 struct pci_dev * pci,
576 unsigned short extin_mask,
577 unsigned short extout_mask,
578 long max_cache_bytes,
579 int enable_ir,
580 emu10k1_t ** remu)
581 {
582 emu10k1_t *emu;
583 int err;
584 int is_audigy;
585 static snd_device_ops_t ops = {
586 .dev_free = snd_emu10k1_dev_free,
587 };
588
589 *remu = NULL;
590
591 // is_audigy = (int)pci->driver_data;
592 is_audigy = (pci->device == 0x0004);
593
594 /* enable PCI device */
595 if ((err = pci_enable_device(pci)) < 0)
596 return err;
597
598 emu = kcalloc(1, sizeof(*emu), GFP_KERNEL);
599 if (emu == NULL)
600 return -ENOMEM;
601 /* set the DMA transfer mask */
602 emu->dma_mask = is_audigy ? AUDIGY_DMA_MASK : EMU10K1_DMA_MASK;
603 if (pci_set_dma_mask(pci, emu->dma_mask) < 0 ||
604 pci_set_consistent_dma_mask(pci, emu->dma_mask) < 0) {
605 snd_printk(KERN_ERR "architecture does not support PCI busmaster DMA with mask 0x%lx\n", emu->dma_mask);
606 kfree(emu);
607 return -ENXIO;
608 }
609 emu->card = card;
610 spin_lock_init(&emu->reg_lock);
611 spin_lock_init(&emu->emu_lock);
612 spin_lock_init(&emu->voice_lock);
613 spin_lock_init(&emu->synth_lock);
614 spin_lock_init(&emu->memblk_lock);
615 init_MUTEX(&emu->ptb_lock);
616 init_MUTEX(&emu->fx8010.lock);
617 INIT_LIST_HEAD(&emu->mapped_link_head);
618 INIT_LIST_HEAD(&emu->mapped_order_link_head);
619 emu->pci = pci;
620 emu->irq = -1;
621 emu->synth = NULL;
622 emu->get_synth_voice = NULL;
623
624 emu->audigy = is_audigy;
625 if (is_audigy)
626 emu->gpr_base = A_FXGPREGBASE;
627 else
628 emu->gpr_base = FXGPREGBASE;
629
630 if ((err = pci_request_regions(pci, "EMU10K1")) < 0) {
631 kfree(emu);
632 return err;
633 }
634 emu->port = pci_resource_start(pci, 0);
635
636 if (request_irq(pci->irq, snd_emu10k1_interrupt, SA_INTERRUPT|SA_SHIRQ, "EMU10K1", (void *)emu)) {
637 snd_emu10k1_free(emu);
638 return -EBUSY;
639 }
640 emu->irq = pci->irq;
641
642 emu->max_cache_pages = max_cache_bytes >> PAGE_SHIFT;
643 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
644 32 * 1024, &emu->ptb_pages) < 0) {
645 snd_emu10k1_free(emu);
646 return -ENOMEM;
647 }
648
649 emu->page_ptr_table = (void **)vmalloc(emu->max_cache_pages * sizeof(void*));
650 emu->page_addr_table = (unsigned long*)vmalloc(emu->max_cache_pages * sizeof(unsigned long));
651 if (emu->page_ptr_table == NULL || emu->page_addr_table == NULL) {
652 snd_emu10k1_free(emu);
653 return -ENOMEM;
654 }
655
656 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(pci),
657 EMUPAGESIZE, &emu->silent_page) < 0) {
658 snd_emu10k1_free(emu);
659 return -ENOMEM;
660 }
661 emu->memhdr = snd_util_memhdr_new(emu->max_cache_pages * PAGE_SIZE);
662 if (emu->memhdr == NULL) {
663 snd_emu10k1_free(emu);
664 return -ENOMEM;
665 }
666 emu->memhdr->block_extra_size = sizeof(emu10k1_memblk_t) - sizeof(snd_util_memblk_t);
667
668 pci_set_master(pci);
669 /* read revision & serial */
670 pci_read_config_byte(pci, PCI_REVISION_ID, (char *)&emu->revision);
671 pci_read_config_dword(pci, PCI_SUBSYSTEM_VENDOR_ID, &emu->serial);
672 pci_read_config_word(pci, PCI_SUBSYSTEM_ID, &emu->model);
673 emu->card_type = EMU10K1_CARD_CREATIVE;
674 if (emu->serial == 0x40011102) {
675 emu->card_type = EMU10K1_CARD_EMUAPS;
676 emu->APS = 1;
677 emu->no_ac97 = 1; /* APS has no AC97 chip */
678 }
679 else if (emu->revision == 4 && emu->serial == 0x10051102) {
680 /* Audigy 2 EX has apparently no effective AC97 controls
681 * (for both input and output), so we skip the AC97 detections
682 */
683 snd_printdd(KERN_INFO "Audigy2 EX is detected. skipping ac97.\n");
684 emu->no_ac97 = 1;
685 }
686
687 if (emu->revision == 4 && emu->model == 0x2002) {
688 /* Audigy 2 ZS */
689 snd_printdd(KERN_INFO "Audigy2 ZS is detected. setting 7.1 mode.\n");
690 emu->spk71 = 1;
691 }
692
693
694 emu->fx8010.fxbus_mask = 0x303f;
695 if (extin_mask == 0)
696 extin_mask = 0x3fcf;
697 if (extout_mask == 0)
698 extout_mask = 0x7fff;
699 emu->fx8010.extin_mask = extin_mask;
700 emu->fx8010.extout_mask = extout_mask;
701
702 if (emu->APS) {
703 if ((err = snd_emu10k1_ecard_init(emu)) < 0) {
704 snd_emu10k1_free(emu);
705 return err;
706 }
707 } else {
708 /* 5.1: Enable the additional AC97 Slots. If the emu10k1 version
709 does not support this, it shouldn't do any harm */
710 snd_emu10k1_ptr_write(emu, AC97SLOT, 0, AC97SLOT_CNTR|AC97SLOT_LFE);
711 }
712
713 if ((err = snd_emu10k1_init(emu, enable_ir)) < 0) {
714 snd_emu10k1_free(emu);
715 return err;
716 }
717
718 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, emu, &ops)) < 0) {
719 snd_emu10k1_free(emu);
720 return err;
721 }
722
723 snd_emu10k1_proc_init(emu);
724
725 snd_card_set_dev(card, &pci->dev);
726 *remu = emu;
727 return 0;
728 }
729
730 /* memory.c */
731 EXPORT_SYMBOL(snd_emu10k1_synth_alloc);
732 EXPORT_SYMBOL(snd_emu10k1_synth_free);
733 EXPORT_SYMBOL(snd_emu10k1_synth_bzero);
734 EXPORT_SYMBOL(snd_emu10k1_synth_copy_from_user);
735 EXPORT_SYMBOL(snd_emu10k1_memblk_map);
736 /* voice.c */
737 EXPORT_SYMBOL(snd_emu10k1_voice_alloc);
738 EXPORT_SYMBOL(snd_emu10k1_voice_free);
739 /* io.c */
740 EXPORT_SYMBOL(snd_emu10k1_ptr_read);
741 EXPORT_SYMBOL(snd_emu10k1_ptr_write);
MOXA 2.6.9 from sdlinux-moxaart.tgz