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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / sound / pci / atiixp_modem.c
blobbec2052ab337405ff9c8b57201d70edd952c37d7
1 /*
2 * ALSA driver for ATI IXP 150/200/250 AC97 modem controllers
3 *
4 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <sound/driver.h>
23 #include <asm/io.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/pci.h>
28 #include <linux/slab.h>
29 #include <linux/moduleparam.h>
30 #include <sound/core.h>
31 #include <sound/pcm.h>
32 #include <sound/pcm_params.h>
33 #include <sound/info.h>
34 #include <sound/ac97_codec.h>
35 #include <sound/initval.h>
36
37 MODULE_AUTHOR("Takashi Iwai <tiwai@suse.de>");
38 MODULE_DESCRIPTION("ATI IXP MC97 controller");
39 MODULE_LICENSE("GPL");
40 MODULE_SUPPORTED_DEVICE("{{ATI,IXP150/200/250}}");
41
42 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
43 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
44 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
45 static int ac97_clock[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 48000};
46 static int boot_devs;
47
48 module_param_array(index, int, boot_devs, 0444);
49 MODULE_PARM_DESC(index, "Index value for ATI IXP controller.");
50 module_param_array(id, charp, boot_devs, 0444);
51 MODULE_PARM_DESC(id, "ID string for ATI IXP controller.");
52 module_param_array(enable, bool, boot_devs, 0444);
53 MODULE_PARM_DESC(enable, "Enable audio part of ATI IXP controller.");
54 module_param_array(ac97_clock, int, boot_devs, 0444);
55 MODULE_PARM_DESC(ac97_clock, "AC'97 codec clock (default 48000Hz).");
56
57
58 /*
59 */
60
61 #define ATI_REG_ISR 0x00 /* interrupt source */
62 #define ATI_REG_ISR_MODEM_IN_XRUN (1U<<0)
63 #define ATI_REG_ISR_MODEM_IN_STATUS (1U<<1)
64 #define ATI_REG_ISR_MODEM_OUT1_XRUN (1U<<2)
65 #define ATI_REG_ISR_MODEM_OUT1_STATUS (1U<<3)
66 #define ATI_REG_ISR_MODEM_OUT2_XRUN (1U<<4)
67 #define ATI_REG_ISR_MODEM_OUT2_STATUS (1U<<5)
68 #define ATI_REG_ISR_MODEM_OUT3_XRUN (1U<<6)
69 #define ATI_REG_ISR_MODEM_OUT3_STATUS (1U<<7)
70 #define ATI_REG_ISR_PHYS_INTR (1U<<8)
71 #define ATI_REG_ISR_PHYS_MISMATCH (1U<<9)
72 #define ATI_REG_ISR_CODEC0_NOT_READY (1U<<10)
73 #define ATI_REG_ISR_CODEC1_NOT_READY (1U<<11)
74 #define ATI_REG_ISR_CODEC2_NOT_READY (1U<<12)
75 #define ATI_REG_ISR_NEW_FRAME (1U<<13)
76 #define ATI_REG_ISR_MODEM_GPIO_DATA (1U<<14)
77
78 #define ATI_REG_IER 0x04 /* interrupt enable */
79 #define ATI_REG_IER_MODEM_IN_XRUN_EN (1U<<0)
80 #define ATI_REG_IER_MODEM_STATUS_EN (1U<<1)
81 #define ATI_REG_IER_MODEM_OUT1_XRUN_EN (1U<<2)
82 #define ATI_REG_IER_MODEM_OUT2_XRUN_EN (1U<<4)
83 #define ATI_REG_IER_MODEM_OUT3_XRUN_EN (1U<<6)
84 #define ATI_REG_IER_PHYS_INTR_EN (1U<<8)
85 #define ATI_REG_IER_PHYS_MISMATCH_EN (1U<<9)
86 #define ATI_REG_IER_CODEC0_INTR_EN (1U<<10)
87 #define ATI_REG_IER_CODEC1_INTR_EN (1U<<11)
88 #define ATI_REG_IER_CODEC2_INTR_EN (1U<<12)
89 #define ATI_REG_IER_NEW_FRAME_EN (1U<<13) /* (RO */
90 #define ATI_REG_IER_MODEM_GPIO_DATA_EN (1U<<14) /* (WO) modem is running */
91 #define ATI_REG_IER_MODEM_SET_BUS_BUSY (1U<<15)
92
93 #define ATI_REG_CMD 0x08 /* command */
94 #define ATI_REG_CMD_POWERDOWN (1U<<0)
95 #define ATI_REG_CMD_MODEM_RECEIVE_EN (1U<<1) /* modem only */
96 #define ATI_REG_CMD_MODEM_SEND1_EN (1U<<2) /* modem only */
97 #define ATI_REG_CMD_MODEM_SEND2_EN (1U<<3) /* modem only */
98 #define ATI_REG_CMD_MODEM_SEND3_EN (1U<<4) /* modem only */
99 #define ATI_REG_CMD_MODEM_STATUS_MEM (1U<<5) /* modem only */
100 #define ATI_REG_CMD_MODEM_IN_DMA_EN (1U<<8) /* modem only */
101 #define ATI_REG_CMD_MODEM_OUT_DMA1_EN (1U<<9) /* modem only */
102 #define ATI_REG_CMD_MODEM_OUT_DMA2_EN (1U<<10) /* modem only */
103 #define ATI_REG_CMD_MODEM_OUT_DMA3_EN (1U<<11) /* modem only */
104 #define ATI_REG_CMD_AUDIO_PRESENT (1U<<20)
105 #define ATI_REG_CMD_MODEM_GPIO_THRU_DMA (1U<<22) /* modem only */
106 #define ATI_REG_CMD_LOOPBACK_EN (1U<<23)
107 #define ATI_REG_CMD_PACKED_DIS (1U<<24)
108 #define ATI_REG_CMD_BURST_EN (1U<<25)
109 #define ATI_REG_CMD_PANIC_EN (1U<<26)
110 #define ATI_REG_CMD_MODEM_PRESENT (1U<<27)
111 #define ATI_REG_CMD_ACLINK_ACTIVE (1U<<28)
112 #define ATI_REG_CMD_AC_SOFT_RESET (1U<<29)
113 #define ATI_REG_CMD_AC_SYNC (1U<<30)
114 #define ATI_REG_CMD_AC_RESET (1U<<31)
115
116 #define ATI_REG_PHYS_OUT_ADDR 0x0c
117 #define ATI_REG_PHYS_OUT_CODEC_MASK (3U<<0)
118 #define ATI_REG_PHYS_OUT_RW (1U<<2)
119 #define ATI_REG_PHYS_OUT_ADDR_EN (1U<<8)
120 #define ATI_REG_PHYS_OUT_ADDR_SHIFT 9
121 #define ATI_REG_PHYS_OUT_DATA_SHIFT 16
122
123 #define ATI_REG_PHYS_IN_ADDR 0x10
124 #define ATI_REG_PHYS_IN_READ_FLAG (1U<<8)
125 #define ATI_REG_PHYS_IN_ADDR_SHIFT 9
126 #define ATI_REG_PHYS_IN_DATA_SHIFT 16
127
128 #define ATI_REG_SLOTREQ 0x14
129
130 #define ATI_REG_COUNTER 0x18
131 #define ATI_REG_COUNTER_SLOT (3U<<0) /* slot # */
132 #define ATI_REG_COUNTER_BITCLOCK (31U<<8)
133
134 #define ATI_REG_IN_FIFO_THRESHOLD 0x1c
135
136 #define ATI_REG_MODEM_IN_DMA_LINKPTR 0x20
137 #define ATI_REG_MODEM_IN_DMA_DT_START 0x24 /* RO */
138 #define ATI_REG_MODEM_IN_DMA_DT_NEXT 0x28 /* RO */
139 #define ATI_REG_MODEM_IN_DMA_DT_CUR 0x2c /* RO */
140 #define ATI_REG_MODEM_IN_DMA_DT_SIZE 0x30
141 #define ATI_REG_MODEM_OUT_FIFO 0x34 /* output threshold */
142 #define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK (0xf<<16)
143 #define ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT 16
144 #define ATI_REG_MODEM_OUT_DMA1_LINKPTR 0x38
145 #define ATI_REG_MODEM_OUT_DMA2_LINKPTR 0x3c
146 #define ATI_REG_MODEM_OUT_DMA3_LINKPTR 0x40
147 #define ATI_REG_MODEM_OUT_DMA1_DT_START 0x44
148 #define ATI_REG_MODEM_OUT_DMA1_DT_NEXT 0x48
149 #define ATI_REG_MODEM_OUT_DMA1_DT_CUR 0x4c
150 #define ATI_REG_MODEM_OUT_DMA2_DT_START 0x50
151 #define ATI_REG_MODEM_OUT_DMA2_DT_NEXT 0x54
152 #define ATI_REG_MODEM_OUT_DMA2_DT_CUR 0x58
153 #define ATI_REG_MODEM_OUT_DMA3_DT_START 0x5c
154 #define ATI_REG_MODEM_OUT_DMA3_DT_NEXT 0x60
155 #define ATI_REG_MODEM_OUT_DMA3_DT_CUR 0x64
156 #define ATI_REG_MODEM_OUT_DMA12_DT_SIZE 0x68
157 #define ATI_REG_MODEM_OUT_DMA3_DT_SIZE 0x6c
158 #define ATI_REG_MODEM_OUT_FIFO_USED 0x70
159 #define ATI_REG_MODEM_OUT_GPIO 0x74
160 #define ATI_REG_MODEM_OUT_GPIO_EN 1
161 #define ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT 5
162 #define ATI_REG_MODEM_IN_GPIO 0x78
163
164 #define ATI_REG_MODEM_MIRROR 0x7c
165 #define ATI_REG_AUDIO_MIRROR 0x80
166
167 #define ATI_REG_MODEM_FIFO_FLUSH 0x88
168 #define ATI_REG_MODEM_FIFO_OUT1_FLUSH (1U<<0)
169 #define ATI_REG_MODEM_FIFO_OUT2_FLUSH (1U<<1)
170 #define ATI_REG_MODEM_FIFO_OUT3_FLUSH (1U<<2)
171 #define ATI_REG_MODEM_FIFO_IN_FLUSH (1U<<3)
172
173 /* LINKPTR */
174 #define ATI_REG_LINKPTR_EN (1U<<0)
175
176 #define ATI_MAX_DESCRIPTORS 256 /* max number of descriptor packets */
177
178
179 /*
180 */
181
182 typedef struct snd_atiixp atiixp_t;
183 typedef struct snd_atiixp_dma atiixp_dma_t;
184 typedef struct snd_atiixp_dma_ops atiixp_dma_ops_t;
185
186
187 /*
188 * DMA packate descriptor
189 */
190
191 typedef struct atiixp_dma_desc {
192 u32 addr; /* DMA buffer address */
193 u16 status; /* status bits */
194 u16 size; /* size of the packet in dwords */
195 u32 next; /* address of the next packet descriptor */
196 } atiixp_dma_desc_t;
197
198 /*
199 * stream enum
200 */
201 enum { ATI_DMA_PLAYBACK, ATI_DMA_CAPTURE, NUM_ATI_DMAS }; /* DMAs */
202 enum { ATI_PCM_OUT, ATI_PCM_IN, NUM_ATI_PCMS }; /* AC97 pcm slots */
203 enum { ATI_PCMDEV_ANALOG, NUM_ATI_PCMDEVS }; /* pcm devices */
204
205 #define NUM_ATI_CODECS 3
206
207
208 /*
209 * constants and callbacks for each DMA type
210 */
211 struct snd_atiixp_dma_ops {
212 int type; /* ATI_DMA_XXX */
213 unsigned int llp_offset; /* LINKPTR offset */
214 unsigned int dt_cur; /* DT_CUR offset */
215 void (*enable_dma)(atiixp_t *chip, int on); /* called from open callback */
216 void (*enable_transfer)(atiixp_t *chip, int on); /* called from trigger (START/STOP) */
217 void (*flush_dma)(atiixp_t *chip); /* called from trigger (STOP only) */
218 };
219
220 /*
221 * DMA stream
222 */
223 struct snd_atiixp_dma {
224 const atiixp_dma_ops_t *ops;
225 struct snd_dma_buffer desc_buf;
226 snd_pcm_substream_t *substream; /* assigned PCM substream */
227 unsigned int buf_addr, buf_bytes; /* DMA buffer address, bytes */
228 unsigned int period_bytes, periods;
229 int opened;
230 int running;
231 int pcm_open_flag;
232 int ac97_pcm_type; /* index # of ac97_pcm to access, -1 = not used */
233 };
234
235 /*
236 * ATI IXP chip
237 */
238 struct snd_atiixp {
239 snd_card_t *card;
240 struct pci_dev *pci;
241
242 struct resource *res; /* memory i/o */
243 unsigned long addr;
244 void __iomem *remap_addr;
245 int irq;
246
247 ac97_bus_t *ac97_bus;
248 ac97_t *ac97[NUM_ATI_CODECS];
249
250 spinlock_t reg_lock;
251 spinlock_t ac97_lock;
252
253 atiixp_dma_t dmas[NUM_ATI_DMAS];
254 struct ac97_pcm *pcms[NUM_ATI_PCMS];
255 snd_pcm_t *pcmdevs[NUM_ATI_PCMDEVS];
256
257 int max_channels; /* max. channels for PCM out */
258
259 unsigned int codec_not_ready_bits; /* for codec detection */
260
261 int spdif_over_aclink; /* passed from the module option */
262 struct semaphore open_mutex; /* playback open mutex */
263 };
264
265
266 /*
267 */
268 static struct pci_device_id snd_atiixp_ids[] = {
269 { 0x1002, 0x434d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* SB200 */
270 { 0, }
271 };
272
273 MODULE_DEVICE_TABLE(pci, snd_atiixp_ids);
274
275
276 /*
277 * lowlevel functions
278 */
279
280 /*
281 * update the bits of the given register.
282 * return 1 if the bits changed.
283 */
284 static int snd_atiixp_update_bits(atiixp_t *chip, unsigned int reg,
285 unsigned int mask, unsigned int value)
286 {
287 void __iomem *addr = chip->remap_addr + reg;
288 unsigned int data, old_data;
289 old_data = data = readl(addr);
290 data &= ~mask;
291 data |= value;
292 if (old_data == data)
293 return 0;
294 writel(data, addr);
295 return 1;
296 }
297
298 /*
299 * macros for easy use
300 */
301 #define atiixp_write(chip,reg,value) \
302 writel(value, chip->remap_addr + ATI_REG_##reg)
303 #define atiixp_read(chip,reg) \
304 readl(chip->remap_addr + ATI_REG_##reg)
305 #define atiixp_update(chip,reg,mask,val) \
306 snd_atiixp_update_bits(chip, ATI_REG_##reg, mask, val)
307
308 /* delay for one tick */
309 #define do_delay() do { \
310 set_current_state(TASK_UNINTERRUPTIBLE); \
311 schedule_timeout(1); \
312 } while (0)
313
314
315 /*
316 * handling DMA packets
317 *
318 * we allocate a linear buffer for the DMA, and split it to each packet.
319 * in a future version, a scatter-gather buffer should be implemented.
320 */
321
322 #define ATI_DESC_LIST_SIZE \
323 PAGE_ALIGN(ATI_MAX_DESCRIPTORS * sizeof(atiixp_dma_desc_t))
324
325 /*
326 * build packets ring for the given buffer size.
327 *
328 * IXP handles the buffer descriptors, which are connected as a linked
329 * list. although we can change the list dynamically, in this version,
330 * a static RING of buffer descriptors is used.
331 *
332 * the ring is built in this function, and is set up to the hardware.
333 */
334 static int atiixp_build_dma_packets(atiixp_t *chip, atiixp_dma_t *dma,
335 snd_pcm_substream_t *substream,
336 unsigned int periods,
337 unsigned int period_bytes)
338 {
339 unsigned int i;
340 u32 addr, desc_addr;
341 unsigned long flags;
342
343 if (periods > ATI_MAX_DESCRIPTORS)
344 return -ENOMEM;
345
346 if (dma->desc_buf.area == NULL) {
347 if (snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, snd_dma_pci_data(chip->pci),
348 ATI_DESC_LIST_SIZE, &dma->desc_buf) < 0)
349 return -ENOMEM;
350 dma->period_bytes = dma->periods = 0; /* clear */
351 }
352
353 if (dma->periods == periods && dma->period_bytes == period_bytes)
354 return 0;
355
356 /* reset DMA before changing the descriptor table */
357 spin_lock_irqsave(&chip->reg_lock, flags);
358 writel(0, chip->remap_addr + dma->ops->llp_offset);
359 dma->ops->enable_dma(chip, 0);
360 dma->ops->enable_dma(chip, 1);
361 spin_unlock_irqrestore(&chip->reg_lock, flags);
362
363 /* fill the entries */
364 addr = (u32)substream->runtime->dma_addr;
365 desc_addr = (u32)dma->desc_buf.addr;
366 for (i = 0; i < periods; i++) {
367 atiixp_dma_desc_t *desc = &((atiixp_dma_desc_t *)dma->desc_buf.area)[i];
368 desc->addr = cpu_to_le32(addr);
369 desc->status = 0;
370 desc->size = period_bytes >> 2; /* in dwords */
371 desc_addr += sizeof(atiixp_dma_desc_t);
372 if (i == periods - 1)
373 desc->next = cpu_to_le32((u32)dma->desc_buf.addr);
374 else
375 desc->next = cpu_to_le32(desc_addr);
376 addr += period_bytes;
377 }
378
379 writel((u32)dma->desc_buf.addr | ATI_REG_LINKPTR_EN,
380 chip->remap_addr + dma->ops->llp_offset);
381
382 dma->period_bytes = period_bytes;
383 dma->periods = periods;
384
385 return 0;
386 }
387
388 /*
389 * remove the ring buffer and release it if assigned
390 */
391 static void atiixp_clear_dma_packets(atiixp_t *chip, atiixp_dma_t *dma, snd_pcm_substream_t *substream)
392 {
393 if (dma->desc_buf.area) {
394 writel(0, chip->remap_addr + dma->ops->llp_offset);
395 snd_dma_free_pages(&dma->desc_buf);
396 dma->desc_buf.area = NULL;
397 }
398 }
399
400 /*
401 * AC97 interface
402 */
403 static int snd_atiixp_acquire_codec(atiixp_t *chip)
404 {
405 int timeout = 1000;
406
407 while (atiixp_read(chip, PHYS_OUT_ADDR) & ATI_REG_PHYS_OUT_ADDR_EN) {
408 if (! timeout--) {
409 snd_printk(KERN_WARNING "atiixp: codec acquire timeout\n");
410 return -EBUSY;
411 }
412 udelay(1);
413 }
414 return 0;
415 }
416
417 static unsigned short snd_atiixp_codec_read(atiixp_t *chip, unsigned short codec, unsigned short reg)
418 {
419 unsigned int data;
420 int timeout;
421
422 if (snd_atiixp_acquire_codec(chip) < 0)
423 return 0xffff;
424 data = (reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
425 ATI_REG_PHYS_OUT_ADDR_EN |
426 ATI_REG_PHYS_OUT_RW |
427 codec;
428 atiixp_write(chip, PHYS_OUT_ADDR, data);
429 if (snd_atiixp_acquire_codec(chip) < 0)
430 return 0xffff;
431 timeout = 1000;
432 do {
433 data = atiixp_read(chip, PHYS_IN_ADDR);
434 if (data & ATI_REG_PHYS_IN_READ_FLAG)
435 return data >> ATI_REG_PHYS_IN_DATA_SHIFT;
436 udelay(1);
437 } while (--timeout);
438 /* time out may happen during reset */
439 if (reg < 0x7c)
440 snd_printk(KERN_WARNING "atiixp: codec read timeout (reg %x)\n", reg);
441 return 0xffff;
442 }
443
444
445 static void snd_atiixp_codec_write(atiixp_t *chip, unsigned short codec, unsigned short reg, unsigned short val)
446 {
447 unsigned int data;
448
449 if (snd_atiixp_acquire_codec(chip) < 0)
450 return;
451 data = ((unsigned int)val << ATI_REG_PHYS_OUT_DATA_SHIFT) |
452 ((unsigned int)reg << ATI_REG_PHYS_OUT_ADDR_SHIFT) |
453 ATI_REG_PHYS_OUT_ADDR_EN | codec;
454 atiixp_write(chip, PHYS_OUT_ADDR, data);
455 }
456
457
458 static unsigned short snd_atiixp_ac97_read(ac97_t *ac97, unsigned short reg)
459 {
460 atiixp_t *chip = ac97->private_data;
461 unsigned short data;
462 spin_lock(&chip->ac97_lock);
463 data = snd_atiixp_codec_read(chip, ac97->num, reg);
464 spin_unlock(&chip->ac97_lock);
465 return data;
466
467 }
468
469 static void snd_atiixp_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short val)
470 {
471 atiixp_t *chip = ac97->private_data;
472 spin_lock(&chip->ac97_lock);
473 snd_atiixp_codec_write(chip, ac97->num, reg, val);
474 spin_unlock(&chip->ac97_lock);
475 }
476
477 /*
478 * reset AC link
479 */
480 static int snd_atiixp_aclink_reset(atiixp_t *chip)
481 {
482 int timeout;
483
484 /* reset powerdoewn */
485 if (atiixp_update(chip, CMD, ATI_REG_CMD_POWERDOWN, 0))
486 udelay(10);
487
488 /* perform a software reset */
489 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, ATI_REG_CMD_AC_SOFT_RESET);
490 atiixp_read(chip, CMD);
491 udelay(10);
492 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SOFT_RESET, 0);
493
494 timeout = 10;
495 while (! (atiixp_read(chip, CMD) & ATI_REG_CMD_ACLINK_ACTIVE)) {
496 /* do a hard reset */
497 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
498 ATI_REG_CMD_AC_SYNC);
499 atiixp_read(chip, CMD);
500 do_delay();
501 atiixp_update(chip, CMD, ATI_REG_CMD_AC_RESET, ATI_REG_CMD_AC_RESET);
502 if (--timeout) {
503 snd_printk(KERN_ERR "atiixp: codec reset timeout\n");
504 break;
505 }
506 }
507
508 /* deassert RESET and assert SYNC to make sure */
509 atiixp_update(chip, CMD, ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET,
510 ATI_REG_CMD_AC_SYNC|ATI_REG_CMD_AC_RESET);
511
512 return 0;
513 }
514
515 #ifdef CONFIG_PM
516 static int snd_atiixp_aclink_down(atiixp_t *chip)
517 {
518 // if (atiixp_read(chip, MODEM_MIRROR) & 0x1) /* modem running, too? */
519 // return -EBUSY;
520 atiixp_update(chip, CMD,
521 ATI_REG_CMD_POWERDOWN | ATI_REG_CMD_AC_RESET,
522 ATI_REG_CMD_POWERDOWN);
523 return 0;
524 }
525 #endif
526
527 /*
528 * auto-detection of codecs
529 *
530 * the IXP chip can generate interrupts for the non-existing codecs.
531 * NEW_FRAME interrupt is used to make sure that the interrupt is generated
532 * even if all three codecs are connected.
533 */
534
535 #define ALL_CODEC_NOT_READY \
536 (ATI_REG_ISR_CODEC0_NOT_READY |\
537 ATI_REG_ISR_CODEC1_NOT_READY |\
538 ATI_REG_ISR_CODEC2_NOT_READY)
539 #define CODEC_CHECK_BITS (ALL_CODEC_NOT_READY|ATI_REG_ISR_NEW_FRAME)
540
541 static int snd_atiixp_codec_detect(atiixp_t *chip)
542 {
543 int timeout;
544
545 chip->codec_not_ready_bits = 0;
546 atiixp_write(chip, IER, CODEC_CHECK_BITS);
547 /* wait for the interrupts */
548 timeout = HZ / 10;
549 while (timeout-- > 0) {
550 do_delay();
551 if (chip->codec_not_ready_bits)
552 break;
553 }
554 atiixp_write(chip, IER, 0); /* disable irqs */
555
556 if ((chip->codec_not_ready_bits & ALL_CODEC_NOT_READY) == ALL_CODEC_NOT_READY) {
557 snd_printk(KERN_ERR "atiixp: no codec detected!\n");
558 return -ENXIO;
559 }
560 return 0;
561 }
562
563
564 /*
565 * enable DMA and irqs
566 */
567 static int snd_atiixp_chip_start(atiixp_t *chip)
568 {
569 unsigned int reg;
570
571 /* set up spdif, enable burst mode */
572 reg = atiixp_read(chip, CMD);
573 reg |= ATI_REG_CMD_BURST_EN;
574 if(!(reg & ATI_REG_CMD_MODEM_PRESENT))
575 reg |= ATI_REG_CMD_MODEM_PRESENT;
576 atiixp_write(chip, CMD, reg);
577
578 /* clear all interrupt source */
579 atiixp_write(chip, ISR, 0xffffffff);
580 /* enable irqs */
581 atiixp_write(chip, IER,
582 ATI_REG_IER_MODEM_STATUS_EN |
583 ATI_REG_IER_MODEM_IN_XRUN_EN |
584 ATI_REG_IER_MODEM_OUT1_XRUN_EN);
585 return 0;
586 }
587
588
589 /*
590 * disable DMA and IRQs
591 */
592 static int snd_atiixp_chip_stop(atiixp_t *chip)
593 {
594 /* clear interrupt source */
595 atiixp_write(chip, ISR, atiixp_read(chip, ISR));
596 /* disable irqs */
597 atiixp_write(chip, IER, 0);
598 return 0;
599 }
600
601
602 /*
603 * PCM section
604 */
605
606 /*
607 * pointer callback simplly reads XXX_DMA_DT_CUR register as the current
608 * position. when SG-buffer is implemented, the offset must be calculated
609 * correctly...
610 */
611 static snd_pcm_uframes_t snd_atiixp_pcm_pointer(snd_pcm_substream_t *substream)
612 {
613 atiixp_t *chip = snd_pcm_substream_chip(substream);
614 snd_pcm_runtime_t *runtime = substream->runtime;
615 atiixp_dma_t *dma = (atiixp_dma_t *)runtime->private_data;
616 unsigned int curptr;
617
618 spin_lock(&chip->reg_lock);
619 curptr = readl(chip->remap_addr + dma->ops->dt_cur);
620 if (curptr < dma->buf_addr) {
621 snd_printdd("curptr = %x, base = %x\n", curptr, dma->buf_addr);
622 curptr = 0;
623 } else {
624 curptr -= dma->buf_addr;
625 if (curptr >= dma->buf_bytes) {
626 snd_printdd("curptr = %x, size = %x\n", curptr, dma->buf_bytes);
627 curptr = 0;
628 }
629 }
630 spin_unlock(&chip->reg_lock);
631 return bytes_to_frames(runtime, curptr);
632 }
633
634 /*
635 * XRUN detected, and stop the PCM substream
636 */
637 static void snd_atiixp_xrun_dma(atiixp_t *chip, atiixp_dma_t *dma)
638 {
639 if (! dma->substream || ! dma->running)
640 return;
641 snd_printdd("atiixp: XRUN detected (DMA %d)\n", dma->ops->type);
642 snd_pcm_stop(dma->substream, SNDRV_PCM_STATE_XRUN);
643 }
644
645 /*
646 * the period ack. update the substream.
647 */
648 static void snd_atiixp_update_dma(atiixp_t *chip, atiixp_dma_t *dma)
649 {
650 if (! dma->substream || ! dma->running)
651 return;
652 snd_pcm_period_elapsed(dma->substream);
653 }
654
655 /* set BUS_BUSY interrupt bit if any DMA is running */
656 /* call with spinlock held */
657 static void snd_atiixp_check_bus_busy(atiixp_t *chip)
658 {
659 unsigned int bus_busy;
660 if (atiixp_read(chip, CMD) & (ATI_REG_CMD_MODEM_SEND1_EN |
661 ATI_REG_CMD_MODEM_RECEIVE_EN))
662 bus_busy = ATI_REG_IER_MODEM_SET_BUS_BUSY;
663 else
664 bus_busy = 0;
665 atiixp_update(chip, IER, ATI_REG_IER_MODEM_SET_BUS_BUSY, bus_busy);
666 }
667
668 /* common trigger callback
669 * calling the lowlevel callbacks in it
670 */
671 static int snd_atiixp_pcm_trigger(snd_pcm_substream_t *substream, int cmd)
672 {
673 atiixp_t *chip = snd_pcm_substream_chip(substream);
674 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
675 unsigned int reg = 0;
676 int i;
677
678 snd_assert(dma->ops->enable_transfer && dma->ops->flush_dma, return -EINVAL);
679
680 if (cmd != SNDRV_PCM_TRIGGER_START && cmd != SNDRV_PCM_TRIGGER_STOP)
681 return -EINVAL;
682
683 spin_lock(&chip->reg_lock);
684
685 /* hook off/on: via GPIO_OUT */
686 for (i = 0; i < NUM_ATI_CODECS; i++) {
687 if (chip->ac97[i]) {
688 reg = snd_ac97_read(chip->ac97[i], AC97_GPIO_STATUS);
689 break;
690 }
691 }
692 if(cmd == SNDRV_PCM_TRIGGER_START)
693 reg |= AC97_GPIO_LINE1_OH;
694 else
695 reg &= ~AC97_GPIO_LINE1_OH;
696 reg = (reg << ATI_REG_MODEM_OUT_GPIO_DATA_SHIFT) | ATI_REG_MODEM_OUT_GPIO_EN ;
697 atiixp_write(chip, MODEM_OUT_GPIO, reg);
698
699 if (cmd == SNDRV_PCM_TRIGGER_START) {
700 dma->ops->enable_transfer(chip, 1);
701 dma->running = 1;
702 } else {
703 dma->ops->enable_transfer(chip, 0);
704 dma->running = 0;
705 }
706 snd_atiixp_check_bus_busy(chip);
707 if (cmd == SNDRV_PCM_TRIGGER_STOP) {
708 dma->ops->flush_dma(chip);
709 snd_atiixp_check_bus_busy(chip);
710 }
711 spin_unlock(&chip->reg_lock);
712 return 0;
713 }
714
715
716 /*
717 * lowlevel callbacks for each DMA type
718 *
719 * every callback is supposed to be called in chip->reg_lock spinlock
720 */
721
722 /* flush FIFO of analog OUT DMA */
723 static void atiixp_out_flush_dma(atiixp_t *chip)
724 {
725 atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_OUT1_FLUSH);
726 }
727
728 /* enable/disable analog OUT DMA */
729 static void atiixp_out_enable_dma(atiixp_t *chip, int on)
730 {
731 unsigned int data;
732 data = atiixp_read(chip, CMD);
733 if (on) {
734 if (data & ATI_REG_CMD_MODEM_OUT_DMA1_EN)
735 return;
736 atiixp_out_flush_dma(chip);
737 data |= ATI_REG_CMD_MODEM_OUT_DMA1_EN;
738 } else
739 data &= ~ATI_REG_CMD_MODEM_OUT_DMA1_EN;
740 atiixp_write(chip, CMD, data);
741 }
742
743 /* start/stop transfer over OUT DMA */
744 static void atiixp_out_enable_transfer(atiixp_t *chip, int on)
745 {
746 atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_SEND1_EN,
747 on ? ATI_REG_CMD_MODEM_SEND1_EN : 0);
748 }
749
750 /* enable/disable analog IN DMA */
751 static void atiixp_in_enable_dma(atiixp_t *chip, int on)
752 {
753 atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_IN_DMA_EN,
754 on ? ATI_REG_CMD_MODEM_IN_DMA_EN : 0);
755 }
756
757 /* start/stop analog IN DMA */
758 static void atiixp_in_enable_transfer(atiixp_t *chip, int on)
759 {
760 if (on) {
761 unsigned int data = atiixp_read(chip, CMD);
762 if (! (data & ATI_REG_CMD_MODEM_RECEIVE_EN)) {
763 data |= ATI_REG_CMD_MODEM_RECEIVE_EN;
764 atiixp_write(chip, CMD, data);
765 }
766 } else
767 atiixp_update(chip, CMD, ATI_REG_CMD_MODEM_RECEIVE_EN, 0);
768 }
769
770 /* flush FIFO of analog IN DMA */
771 static void atiixp_in_flush_dma(atiixp_t *chip)
772 {
773 atiixp_write(chip, MODEM_FIFO_FLUSH, ATI_REG_MODEM_FIFO_IN_FLUSH);
774 }
775
776 /* set up slots and formats for analog OUT */
777 static int snd_atiixp_playback_prepare(snd_pcm_substream_t *substream)
778 {
779 atiixp_t *chip = snd_pcm_substream_chip(substream);
780 unsigned int data;
781
782 spin_lock_irq(&chip->reg_lock);
783 /* set output threshold */
784 data = atiixp_read(chip, MODEM_OUT_FIFO);
785 data &= ~ATI_REG_MODEM_OUT1_DMA_THRESHOLD_MASK;
786 data |= 0x04 << ATI_REG_MODEM_OUT1_DMA_THRESHOLD_SHIFT;
787 atiixp_write(chip, MODEM_OUT_FIFO, data);
788 spin_unlock_irq(&chip->reg_lock);
789 return 0;
790 }
791
792 /* set up slots and formats for analog IN */
793 static int snd_atiixp_capture_prepare(snd_pcm_substream_t *substream)
794 {
795 return 0;
796 }
797
798 /*
799 * hw_params - allocate the buffer and set up buffer descriptors
800 */
801 static int snd_atiixp_pcm_hw_params(snd_pcm_substream_t *substream,
802 snd_pcm_hw_params_t *hw_params)
803 {
804 atiixp_t *chip = snd_pcm_substream_chip(substream);
805 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
806 int err;
807 int i;
808
809 err = snd_pcm_lib_malloc_pages(substream, params_buffer_bytes(hw_params));
810 if (err < 0)
811 return err;
812 dma->buf_addr = substream->runtime->dma_addr;
813 dma->buf_bytes = params_buffer_bytes(hw_params);
814
815 err = atiixp_build_dma_packets(chip, dma, substream,
816 params_periods(hw_params),
817 params_period_bytes(hw_params));
818 if (err < 0)
819 return err;
820
821 /* set up modem rate */
822 for (i = 0; i < NUM_ATI_CODECS; i++) {
823 if (! chip->ac97[i])
824 continue;
825 snd_ac97_write(chip->ac97[i], AC97_LINE1_RATE, params_rate(hw_params));
826 snd_ac97_write(chip->ac97[i], AC97_LINE1_LEVEL, 0);
827 }
828
829 return err;
830 }
831
832 static int snd_atiixp_pcm_hw_free(snd_pcm_substream_t * substream)
833 {
834 atiixp_t *chip = snd_pcm_substream_chip(substream);
835 atiixp_dma_t *dma = (atiixp_dma_t *)substream->runtime->private_data;
836
837 atiixp_clear_dma_packets(chip, dma, substream);
838 snd_pcm_lib_free_pages(substream);
839 return 0;
840 }
841
842
843 /*
844 * pcm hardware definition, identical for all DMA types
845 */
846 static snd_pcm_hardware_t snd_atiixp_pcm_hw =
847 {
848 .info = (SNDRV_PCM_INFO_MMAP | SNDRV_PCM_INFO_INTERLEAVED |
849 SNDRV_PCM_INFO_BLOCK_TRANSFER |
850 SNDRV_PCM_INFO_MMAP_VALID),
851 .formats = SNDRV_PCM_FMTBIT_S16_LE,
852 .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_KNOT,
853 .rate_min = 8000,
854 .rate_max = 16000,
855 .channels_min = 2,
856 .channels_max = 2,
857 .buffer_bytes_max = 256 * 1024,
858 .period_bytes_min = 32,
859 .period_bytes_max = 128 * 1024,
860 .periods_min = 2,
861 .periods_max = ATI_MAX_DESCRIPTORS,
862 };
863
864 static int snd_atiixp_pcm_open(snd_pcm_substream_t *substream, atiixp_dma_t *dma, int pcm_type)
865 {
866 atiixp_t *chip = snd_pcm_substream_chip(substream);
867 snd_pcm_runtime_t *runtime = substream->runtime;
868 int err;
869 static unsigned int rates[] = { 8000, 9600, 12000, 16000 };
870 static snd_pcm_hw_constraint_list_t hw_constraints_rates = {
871 .count = ARRAY_SIZE(rates),
872 .list = rates,
873 .mask = 0,
874 };
875
876 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
877
878 if (dma->opened)
879 return -EBUSY;
880 dma->substream = substream;
881 runtime->hw = snd_atiixp_pcm_hw;
882 dma->ac97_pcm_type = pcm_type;
883 if ((err = snd_pcm_hw_constraint_list(runtime, 0, SNDRV_PCM_HW_PARAM_RATE, &hw_constraints_rates)) < 0)
884 return err;
885 if ((err = snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS)) < 0)
886 return err;
887 runtime->private_data = dma;
888
889 /* enable DMA bits */
890 spin_lock_irq(&chip->reg_lock);
891 dma->ops->enable_dma(chip, 1);
892 spin_unlock_irq(&chip->reg_lock);
893 dma->opened = 1;
894
895 return 0;
896 }
897
898 static int snd_atiixp_pcm_close(snd_pcm_substream_t *substream, atiixp_dma_t *dma)
899 {
900 atiixp_t *chip = snd_pcm_substream_chip(substream);
901 /* disable DMA bits */
902 snd_assert(dma->ops && dma->ops->enable_dma, return -EINVAL);
903 spin_lock_irq(&chip->reg_lock);
904 dma->ops->enable_dma(chip, 0);
905 spin_unlock_irq(&chip->reg_lock);
906 dma->substream = NULL;
907 dma->opened = 0;
908 return 0;
909 }
910
911 /*
912 */
913 static int snd_atiixp_playback_open(snd_pcm_substream_t *substream)
914 {
915 atiixp_t *chip = snd_pcm_substream_chip(substream);
916 int err;
917
918 down(&chip->open_mutex);
919 err = snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_PLAYBACK], 0);
920 up(&chip->open_mutex);
921 if (err < 0)
922 return err;
923 return 0;
924 }
925
926 static int snd_atiixp_playback_close(snd_pcm_substream_t *substream)
927 {
928 atiixp_t *chip = snd_pcm_substream_chip(substream);
929 int err;
930 down(&chip->open_mutex);
931 err = snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_PLAYBACK]);
932 up(&chip->open_mutex);
933 return err;
934 }
935
936 static int snd_atiixp_capture_open(snd_pcm_substream_t *substream)
937 {
938 atiixp_t *chip = snd_pcm_substream_chip(substream);
939 return snd_atiixp_pcm_open(substream, &chip->dmas[ATI_DMA_CAPTURE], 1);
940 }
941
942 static int snd_atiixp_capture_close(snd_pcm_substream_t *substream)
943 {
944 atiixp_t *chip = snd_pcm_substream_chip(substream);
945 return snd_atiixp_pcm_close(substream, &chip->dmas[ATI_DMA_CAPTURE]);
946 }
947
948
949 /* AC97 playback */
950 static snd_pcm_ops_t snd_atiixp_playback_ops = {
951 .open = snd_atiixp_playback_open,
952 .close = snd_atiixp_playback_close,
953 .ioctl = snd_pcm_lib_ioctl,
954 .hw_params = snd_atiixp_pcm_hw_params,
955 .hw_free = snd_atiixp_pcm_hw_free,
956 .prepare = snd_atiixp_playback_prepare,
957 .trigger = snd_atiixp_pcm_trigger,
958 .pointer = snd_atiixp_pcm_pointer,
959 };
960
961 /* AC97 capture */
962 static snd_pcm_ops_t snd_atiixp_capture_ops = {
963 .open = snd_atiixp_capture_open,
964 .close = snd_atiixp_capture_close,
965 .ioctl = snd_pcm_lib_ioctl,
966 .hw_params = snd_atiixp_pcm_hw_params,
967 .hw_free = snd_atiixp_pcm_hw_free,
968 .prepare = snd_atiixp_capture_prepare,
969 .trigger = snd_atiixp_pcm_trigger,
970 .pointer = snd_atiixp_pcm_pointer,
971 };
972
973 static atiixp_dma_ops_t snd_atiixp_playback_dma_ops = {
974 .type = ATI_DMA_PLAYBACK,
975 .llp_offset = ATI_REG_MODEM_OUT_DMA1_LINKPTR,
976 .dt_cur = ATI_REG_MODEM_OUT_DMA1_DT_CUR,
977 .enable_dma = atiixp_out_enable_dma,
978 .enable_transfer = atiixp_out_enable_transfer,
979 .flush_dma = atiixp_out_flush_dma,
980 };
981
982 static atiixp_dma_ops_t snd_atiixp_capture_dma_ops = {
983 .type = ATI_DMA_CAPTURE,
984 .llp_offset = ATI_REG_MODEM_IN_DMA_LINKPTR,
985 .dt_cur = ATI_REG_MODEM_IN_DMA_DT_CUR,
986 .enable_dma = atiixp_in_enable_dma,
987 .enable_transfer = atiixp_in_enable_transfer,
988 .flush_dma = atiixp_in_flush_dma,
989 };
990
991 static int __devinit snd_atiixp_pcm_new(atiixp_t *chip)
992 {
993 snd_pcm_t *pcm;
994 int err;
995
996 /* initialize constants */
997 chip->dmas[ATI_DMA_PLAYBACK].ops = &snd_atiixp_playback_dma_ops;
998 chip->dmas[ATI_DMA_CAPTURE].ops = &snd_atiixp_capture_dma_ops;
999
1000 /* PCM #0: analog I/O */
1001 err = snd_pcm_new(chip->card, "ATI IXP MC97", ATI_PCMDEV_ANALOG, 1, 1, &pcm);
1002 if (err < 0)
1003 return err;
1004 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_atiixp_playback_ops);
1005 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_atiixp_capture_ops);
1006 pcm->private_data = chip;
1007 strcpy(pcm->name, "ATI IXP MC97");
1008 chip->pcmdevs[ATI_PCMDEV_ANALOG] = pcm;
1009
1010 snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV,
1011 snd_dma_pci_data(chip->pci), 64*1024, 128*1024);
1012
1013 return 0;
1014 }
1015
1016
1017
1018 /*
1019 * interrupt handler
1020 */
1021 static irqreturn_t snd_atiixp_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1022 {
1023 atiixp_t *chip = dev_id;
1024 unsigned int status;
1025
1026 status = atiixp_read(chip, ISR);
1027
1028 if (! status)
1029 return IRQ_NONE;
1030
1031 /* process audio DMA */
1032 if (status & ATI_REG_ISR_MODEM_OUT1_XRUN)
1033 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1034 else if (status & ATI_REG_ISR_MODEM_OUT1_STATUS)
1035 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_PLAYBACK]);
1036 if (status & ATI_REG_ISR_MODEM_IN_XRUN)
1037 snd_atiixp_xrun_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1038 else if (status & ATI_REG_ISR_MODEM_IN_STATUS)
1039 snd_atiixp_update_dma(chip, &chip->dmas[ATI_DMA_CAPTURE]);
1040
1041 /* for codec detection */
1042 if (status & CODEC_CHECK_BITS) {
1043 unsigned int detected;
1044 detected = status & CODEC_CHECK_BITS;
1045 spin_lock(&chip->reg_lock);
1046 chip->codec_not_ready_bits |= detected;
1047 atiixp_update(chip, IER, detected, 0); /* disable the detected irqs */
1048 spin_unlock(&chip->reg_lock);
1049 }
1050
1051 /* ack */
1052 atiixp_write(chip, ISR, status);
1053
1054 return IRQ_HANDLED;
1055 }
1056
1057
1058 /*
1059 * ac97 mixer section
1060 */
1061
1062 static int __devinit snd_atiixp_mixer_new(atiixp_t *chip, int clock)
1063 {
1064 ac97_bus_t *pbus;
1065 ac97_template_t ac97;
1066 int i, err;
1067 int codec_count;
1068 static ac97_bus_ops_t ops = {
1069 .write = snd_atiixp_ac97_write,
1070 .read = snd_atiixp_ac97_read,
1071 };
1072 static unsigned int codec_skip[NUM_ATI_CODECS] = {
1073 ATI_REG_ISR_CODEC0_NOT_READY,
1074 ATI_REG_ISR_CODEC1_NOT_READY,
1075 ATI_REG_ISR_CODEC2_NOT_READY,
1076 };
1077
1078 if (snd_atiixp_codec_detect(chip) < 0)
1079 return -ENXIO;
1080
1081 if ((err = snd_ac97_bus(chip->card, 0, &ops, chip, &pbus)) < 0)
1082 return err;
1083 pbus->clock = clock;
1084 pbus->shared_type = AC97_SHARED_TYPE_ATIIXP; /* shared with audio driver */
1085 chip->ac97_bus = pbus;
1086
1087 codec_count = 0;
1088 for (i = 0; i < NUM_ATI_CODECS; i++) {
1089 if (chip->codec_not_ready_bits & codec_skip[i])
1090 continue;
1091 memset(&ac97, 0, sizeof(ac97));
1092 ac97.private_data = chip;
1093 ac97.pci = chip->pci;
1094 ac97.num = i;
1095 ac97.scaps = AC97_SCAP_SKIP_AUDIO;
1096 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97[i])) < 0) {
1097 chip->ac97[i] = NULL; /* to be sure */
1098 snd_printdd("atiixp: codec %d not available for modem\n", i);
1099 continue;
1100 }
1101 codec_count++;
1102 }
1103
1104 if (! codec_count) {
1105 snd_printk(KERN_ERR "atiixp: no codec available\n");
1106 return -ENODEV;
1107 }
1108
1109 /* snd_ac97_tune_hardware(chip->ac97, ac97_quirks); */
1110
1111 return 0;
1112 }
1113
1114
1115 #ifdef CONFIG_PM
1116 /*
1117 * power management
1118 */
1119 static int snd_atiixp_suspend(snd_card_t *card, unsigned int state)
1120 {
1121 atiixp_t *chip = card->pm_private_data;
1122 int i;
1123
1124 for (i = 0; i < NUM_ATI_PCMDEVS; i++)
1125 if (chip->pcmdevs[i])
1126 snd_pcm_suspend_all(chip->pcmdevs[i]);
1127 for (i = 0; i < NUM_ATI_CODECS; i++)
1128 if (chip->ac97[i])
1129 snd_ac97_suspend(chip->ac97[i]);
1130 snd_atiixp_aclink_down(chip);
1131 snd_atiixp_chip_stop(chip);
1132
1133 pci_set_power_state(chip->pci, 3);
1134 pci_disable_device(chip->pci);
1135 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1136 return 0;
1137 }
1138
1139 static int snd_atiixp_resume(snd_card_t *card, unsigned int state)
1140 {
1141 atiixp_t *chip = card->pm_private_data;
1142 int i;
1143
1144 pci_enable_device(chip->pci);
1145 pci_set_power_state(chip->pci, 0);
1146
1147 snd_atiixp_aclink_reset(chip);
1148 snd_atiixp_chip_start(chip);
1149
1150 for (i = 0; i < NUM_ATI_CODECS; i++)
1151 if (chip->ac97[i])
1152 snd_ac97_resume(chip->ac97[i]);
1153
1154 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1155 return 0;
1156 }
1157 #endif /* CONFIG_PM */
1158
1159
1160 /*
1161 * proc interface for register dump
1162 */
1163
1164 static void snd_atiixp_proc_read(snd_info_entry_t *entry, snd_info_buffer_t *buffer)
1165 {
1166 atiixp_t *chip = entry->private_data;
1167 int i;
1168
1169 for (i = 0; i < 256; i += 4)
1170 snd_iprintf(buffer, "%02x: %08x\n", i, readl(chip->remap_addr + i));
1171 }
1172
1173 static void __devinit snd_atiixp_proc_init(atiixp_t *chip)
1174 {
1175 snd_info_entry_t *entry;
1176
1177 if (! snd_card_proc_new(chip->card, "atiixp", &entry))
1178 snd_info_set_text_ops(entry, chip, 1024, snd_atiixp_proc_read);
1179 }
1180
1181
1182
1183 /*
1184 * destructor
1185 */
1186
1187 static int snd_atiixp_free(atiixp_t *chip)
1188 {
1189 if (chip->irq < 0)
1190 goto __hw_end;
1191 snd_atiixp_chip_stop(chip);
1192 synchronize_irq(chip->irq);
1193 __hw_end:
1194 if (chip->irq >= 0)
1195 free_irq(chip->irq, (void *)chip);
1196 if (chip->remap_addr)
1197 iounmap(chip->remap_addr);
1198 pci_release_regions(chip->pci);
1199 kfree(chip);
1200 return 0;
1201 }
1202
1203 static int snd_atiixp_dev_free(snd_device_t *device)
1204 {
1205 atiixp_t *chip = device->device_data;
1206 return snd_atiixp_free(chip);
1207 }
1208
1209 /*
1210 * constructor for chip instance
1211 */
1212 static int __devinit snd_atiixp_create(snd_card_t *card,
1213 struct pci_dev *pci,
1214 atiixp_t **r_chip)
1215 {
1216 static snd_device_ops_t ops = {
1217 .dev_free = snd_atiixp_dev_free,
1218 };
1219 atiixp_t *chip;
1220 int err;
1221
1222 if ((err = pci_enable_device(pci)) < 0)
1223 return err;
1224
1225 chip = kcalloc(1, sizeof(*chip), GFP_KERNEL);
1226 if (chip == NULL)
1227 return -ENOMEM;
1228
1229 spin_lock_init(&chip->reg_lock);
1230 spin_lock_init(&chip->ac97_lock);
1231 init_MUTEX(&chip->open_mutex);
1232 chip->card = card;
1233 chip->pci = pci;
1234 chip->irq = -1;
1235 if ((err = pci_request_regions(pci, "ATI IXP MC97")) < 0) {
1236 kfree(chip);
1237 return err;
1238 }
1239 chip->addr = pci_resource_start(pci, 0);
1240 chip->remap_addr = ioremap_nocache(chip->addr, pci_resource_len(pci, 0));
1241 if (chip->remap_addr == 0) {
1242 snd_printk(KERN_ERR "AC'97 space ioremap problem\n");
1243 snd_atiixp_free(chip);
1244 return -EIO;
1245 }
1246
1247 if (request_irq(pci->irq, snd_atiixp_interrupt, SA_INTERRUPT|SA_SHIRQ, card->shortname, (void *)chip)) {
1248 snd_printk(KERN_ERR "unable to grab IRQ %d\n", pci->irq);
1249 snd_atiixp_free(chip);
1250 return -EBUSY;
1251 }
1252 chip->irq = pci->irq;
1253 pci_set_master(pci);
1254 synchronize_irq(chip->irq);
1255
1256 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
1257 snd_atiixp_free(chip);
1258 return err;
1259 }
1260
1261 snd_card_set_dev(card, &pci->dev);
1262
1263 *r_chip = chip;
1264 return 0;
1265 }
1266
1267
1268 static int __devinit snd_atiixp_probe(struct pci_dev *pci,
1269 const struct pci_device_id *pci_id)
1270 {
1271 static int dev;
1272 snd_card_t *card;
1273 atiixp_t *chip;
1274 unsigned char revision;
1275 int err;
1276
1277 if (dev >= SNDRV_CARDS)
1278 return -ENODEV;
1279 if (!enable[dev]) {
1280 dev++;
1281 return -ENOENT;
1282 }
1283
1284 card = snd_card_new(index[dev], id[dev], THIS_MODULE, 0);
1285 if (card == NULL)
1286 return -ENOMEM;
1287
1288 pci_read_config_byte(pci, PCI_REVISION_ID, &revision);
1289
1290 strcpy(card->driver, "ATIIXP-MODEM");
1291 strcpy(card->shortname, "ATI IXP Modem");
1292 if ((err = snd_atiixp_create(card, pci, &chip)) < 0)
1293 goto __error;
1294
1295 if ((err = snd_atiixp_aclink_reset(chip)) < 0)
1296 goto __error;
1297
1298 if ((err = snd_atiixp_mixer_new(chip, ac97_clock[dev])) < 0)
1299 goto __error;
1300
1301 if ((err = snd_atiixp_pcm_new(chip)) < 0)
1302 goto __error;
1303
1304 snd_atiixp_proc_init(chip);
1305
1306 snd_atiixp_chip_start(chip);
1307
1308 sprintf(card->longname, "%s rev %x at 0x%lx, irq %i",
1309 card->shortname, revision, chip->addr, chip->irq);
1310
1311 snd_card_set_pm_callback(card, snd_atiixp_suspend, snd_atiixp_resume, chip);
1312
1313 if ((err = snd_card_register(card)) < 0)
1314 goto __error;
1315
1316 pci_set_drvdata(pci, card);
1317 dev++;
1318 return 0;
1319
1320 __error:
1321 snd_card_free(card);
1322 return err;
1323 }
1324
1325 static void __devexit snd_atiixp_remove(struct pci_dev *pci)
1326 {
1327 snd_card_free(pci_get_drvdata(pci));
1328 pci_set_drvdata(pci, NULL);
1329 }
1330
1331 static struct pci_driver driver = {
1332 .name = "ATI IXP MC97 controller",
1333 .id_table = snd_atiixp_ids,
1334 .probe = snd_atiixp_probe,
1335 .remove = __devexit_p(snd_atiixp_remove),
1336 SND_PCI_PM_CALLBACKS
1337 };
1338
1339
1340 static int __init alsa_card_atiixp_init(void)
1341 {
1342 return pci_module_init(&driver);
1343 }
1344
1345 static void __exit alsa_card_atiixp_exit(void)
1346 {
1347 pci_unregister_driver(&driver);
1348 }
1349
1350 module_init(alsa_card_atiixp_init)
1351 module_exit(alsa_card_atiixp_exit)
MOXA 2.6.9 from sdlinux-moxaart.tgz