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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / include / sound / ac97_codec.h
blobbcdda71ac3a59cbd96bede0c4be3969267c14f1e
1 #ifndef __SOUND_AC97_CODEC_H
2 #define __SOUND_AC97_CODEC_H
3
4 /*
5 * Copyright (c) by Jaroslav Kysela <perex@suse.cz>
6 * Universal interface for Audio Codec '97
7 *
8 * For more details look to AC '97 component specification revision 2.1
9 * by Intel Corporation (http://developer.intel.com).
10 *
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
28 #include <linux/bitops.h>
29 #include "control.h"
30 #include "info.h"
31
32 /*
33 * AC'97 codec registers
34 */
35
36 #define AC97_RESET 0x00 /* Reset */
37 #define AC97_MASTER 0x02 /* Master Volume */
38 #define AC97_HEADPHONE 0x04 /* Headphone Volume (optional) */
39 #define AC97_MASTER_MONO 0x06 /* Master Volume Mono (optional) */
40 #define AC97_MASTER_TONE 0x08 /* Master Tone (Bass & Treble) (optional) */
41 #define AC97_PC_BEEP 0x0a /* PC Beep Volume (optinal) */
42 #define AC97_PHONE 0x0c /* Phone Volume (optional) */
43 #define AC97_MIC 0x0e /* MIC Volume */
44 #define AC97_LINE 0x10 /* Line In Volume */
45 #define AC97_CD 0x12 /* CD Volume */
46 #define AC97_VIDEO 0x14 /* Video Volume (optional) */
47 #define AC97_AUX 0x16 /* AUX Volume (optional) */
48 #define AC97_PCM 0x18 /* PCM Volume */
49 #define AC97_REC_SEL 0x1a /* Record Select */
50 #define AC97_REC_GAIN 0x1c /* Record Gain */
51 #define AC97_REC_GAIN_MIC 0x1e /* Record Gain MIC (optional) */
52 #define AC97_GENERAL_PURPOSE 0x20 /* General Purpose (optional) */
53 #define AC97_3D_CONTROL 0x22 /* 3D Control (optional) */
54 #define AC97_INT_PAGING 0x24 /* Audio Interrupt & Paging (AC'97 2.3) */
55 #define AC97_POWERDOWN 0x26 /* Powerdown control / status */
56 /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
57 #define AC97_EXTENDED_ID 0x28 /* Extended Audio ID */
58 #define AC97_EXTENDED_STATUS 0x2a /* Extended Audio Status and Control */
59 #define AC97_PCM_FRONT_DAC_RATE 0x2c /* PCM Front DAC Rate */
60 #define AC97_PCM_SURR_DAC_RATE 0x2e /* PCM Surround DAC Rate */
61 #define AC97_PCM_LFE_DAC_RATE 0x30 /* PCM LFE DAC Rate */
62 #define AC97_PCM_LR_ADC_RATE 0x32 /* PCM LR ADC Rate */
63 #define AC97_PCM_MIC_ADC_RATE 0x34 /* PCM MIC ADC Rate */
64 #define AC97_CENTER_LFE_MASTER 0x36 /* Center + LFE Master Volume */
65 #define AC97_SURROUND_MASTER 0x38 /* Surround (Rear) Master Volume */
66 #define AC97_SPDIF 0x3a /* S/PDIF control */
67 /* range 0x3c-0x58 - MODEM */
68 #define AC97_EXTENDED_MID 0x3c /* Extended Modem ID */
69 #define AC97_EXTENDED_MSTATUS 0x3e /* Extended Modem Status and Control */
70 #define AC97_LINE1_RATE 0x40 /* Line1 DAC/ADC Rate */
71 #define AC97_LINE2_RATE 0x42 /* Line2 DAC/ADC Rate */
72 #define AC97_HANDSET_RATE 0x44 /* Handset DAC/ADC Rate */
73 #define AC97_LINE1_LEVEL 0x46 /* Line1 DAC/ADC Level */
74 #define AC97_LINE2_LEVEL 0x48 /* Line2 DAC/ADC Level */
75 #define AC97_HANDSET_LEVEL 0x4a /* Handset DAC/ADC Level */
76 #define AC97_GPIO_CFG 0x4c /* GPIO Configuration */
77 #define AC97_GPIO_POLARITY 0x4e /* GPIO Pin Polarity/Type, 0=low, 1=high active */
78 #define AC97_GPIO_STICKY 0x50 /* GPIO Pin Sticky, 0=not, 1=sticky */
79 #define AC97_GPIO_WAKEUP 0x52 /* GPIO Pin Wakeup, 0=no int, 1=yes int */
80 #define AC97_GPIO_STATUS 0x54 /* GPIO Pin Status, slot 12 */
81 #define AC97_MISC_AFE 0x56 /* Miscellaneous Modem AFE Status and Control */
82 /* range 0x5a-0x7b - Vendor Specific */
83 #define AC97_VENDOR_ID1 0x7c /* Vendor ID1 */
84 #define AC97_VENDOR_ID2 0x7e /* Vendor ID2 / revision */
85 /* range 0x60-0x6f (page 1) - extended codec registers */
86 #define AC97_CODEC_CLASS_REV 0x60 /* Codec Class/Revision */
87 #define AC97_PCI_SVID 0x62 /* PCI Subsystem Vendor ID */
88 #define AC97_PCI_SID 0x64 /* PCI Subsystem ID */
89 #define AC97_FUNC_SELECT 0x66 /* Function Select */
90 #define AC97_FUNC_INFO 0x68 /* Function Information */
91 #define AC97_SENSE_INFO 0x6a /* Sense Details */
92
93 /* slot allocation */
94 #define AC97_SLOT_TAG 0
95 #define AC97_SLOT_CMD_ADDR 1
96 #define AC97_SLOT_CMD_DATA 2
97 #define AC97_SLOT_PCM_LEFT 3
98 #define AC97_SLOT_PCM_RIGHT 4
99 #define AC97_SLOT_MODEM_LINE1 5
100 #define AC97_SLOT_PCM_CENTER 6
101 #define AC97_SLOT_MIC 6 /* input */
102 #define AC97_SLOT_SPDIF_LEFT1 6
103 #define AC97_SLOT_PCM_SLEFT 7 /* surround left */
104 #define AC97_SLOT_PCM_LEFT_0 7 /* double rate operation */
105 #define AC97_SLOT_SPDIF_LEFT 7
106 #define AC97_SLOT_PCM_SRIGHT 8 /* surround right */
107 #define AC97_SLOT_PCM_RIGHT_0 8 /* double rate operation */
108 #define AC97_SLOT_SPDIF_RIGHT 8
109 #define AC97_SLOT_LFE 9
110 #define AC97_SLOT_SPDIF_RIGHT1 9
111 #define AC97_SLOT_MODEM_LINE2 10
112 #define AC97_SLOT_PCM_LEFT_1 10 /* double rate operation */
113 #define AC97_SLOT_SPDIF_LEFT2 10
114 #define AC97_SLOT_HANDSET 11 /* output */
115 #define AC97_SLOT_PCM_RIGHT_1 11 /* double rate operation */
116 #define AC97_SLOT_SPDIF_RIGHT2 11
117 #define AC97_SLOT_MODEM_GPIO 12 /* modem GPIO */
118 #define AC97_SLOT_PCM_CENTER_1 12 /* double rate operation */
119
120 /* basic capabilities (reset register) */
121 #define AC97_BC_DEDICATED_MIC 0x0001 /* Dedicated Mic PCM In Channel */
122 #define AC97_BC_RESERVED1 0x0002 /* Reserved (was Modem Line Codec support) */
123 #define AC97_BC_BASS_TREBLE 0x0004 /* Bass & Treble Control */
124 #define AC97_BC_SIM_STEREO 0x0008 /* Simulated stereo */
125 #define AC97_BC_HEADPHONE 0x0010 /* Headphone Out Support */
126 #define AC97_BC_LOUDNESS 0x0020 /* Loudness (bass boost) Support */
127 #define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
128 #define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
129 #define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
130 #define AC97_BC_DAC_MASK 0x00c0
131 #define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
132 #define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
133 #define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */
134 #define AC97_BC_ADC_MASK 0x0300
135
136 /* extended audio ID bit defines */
137 #define AC97_EI_VRA 0x0001 /* Variable bit rate supported */
138 #define AC97_EI_DRA 0x0002 /* Double rate supported */
139 #define AC97_EI_SPDIF 0x0004 /* S/PDIF out supported */
140 #define AC97_EI_VRM 0x0008 /* Variable bit rate supported for MIC */
141 #define AC97_EI_DACS_SLOT_MASK 0x0030 /* DACs slot assignment */
142 #define AC97_EI_DACS_SLOT_SHIFT 4
143 #define AC97_EI_CDAC 0x0040 /* PCM Center DAC available */
144 #define AC97_EI_SDAC 0x0080 /* PCM Surround DACs available */
145 #define AC97_EI_LDAC 0x0100 /* PCM LFE DAC available */
146 #define AC97_EI_AMAP 0x0200 /* indicates optional slot/DAC mapping based on codec ID */
147 #define AC97_EI_REV_MASK 0x0c00 /* AC'97 revision mask */
148 #define AC97_EI_REV_22 0x0400 /* AC'97 revision 2.2 */
149 #define AC97_EI_REV_23 0x0800 /* AC'97 revision 2.3 */
150 #define AC97_EI_REV_SHIFT 10
151 #define AC97_EI_ADDR_MASK 0xc000 /* physical codec ID (address) */
152 #define AC97_EI_ADDR_SHIFT 14
153
154 /* extended audio status and control bit defines */
155 #define AC97_EA_VRA 0x0001 /* Variable bit rate enable bit */
156 #define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */
157 #define AC97_EA_SPDIF 0x0004 /* S/PDIF out enable bit */
158 #define AC97_EA_VRM 0x0008 /* Variable bit rate for MIC enable bit */
159 #define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */
160 #define AC97_EA_SPSA_SLOT_SHIFT 4
161 #define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */
162 #define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */
163 #define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */
164 #define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */
165 #define AC97_EA_CDAC 0x0040 /* PCM Center DAC is ready (Read only) */
166 #define AC97_EA_SDAC 0x0080 /* PCM Surround DACs are ready (Read only) */
167 #define AC97_EA_LDAC 0x0100 /* PCM LFE DAC is ready (Read only) */
168 #define AC97_EA_MDAC 0x0200 /* MIC ADC is ready (Read only) */
169 #define AC97_EA_SPCV 0x0400 /* S/PDIF configuration valid (Read only) */
170 #define AC97_EA_PRI 0x0800 /* Turns the PCM Center DAC off */
171 #define AC97_EA_PRJ 0x1000 /* Turns the PCM Surround DACs off */
172 #define AC97_EA_PRK 0x2000 /* Turns the PCM LFE DAC off */
173 #define AC97_EA_PRL 0x4000 /* Turns the MIC ADC off */
174
175 /* S/PDIF control bit defines */
176 #define AC97_SC_PRO 0x0001 /* Professional status */
177 #define AC97_SC_NAUDIO 0x0002 /* Non audio stream */
178 #define AC97_SC_COPY 0x0004 /* Copyright status */
179 #define AC97_SC_PRE 0x0008 /* Preemphasis status */
180 #define AC97_SC_CC_MASK 0x07f0 /* Category Code mask */
181 #define AC97_SC_CC_SHIFT 4
182 #define AC97_SC_L 0x0800 /* Generation Level status */
183 #define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */
184 #define AC97_SC_SPSR_SHIFT 12
185 #define AC97_SC_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
186 #define AC97_SC_SPSR_48K 0x2000 /* Use 48kHz Sample rate */
187 #define AC97_SC_SPSR_32K 0x3000 /* Use 32kHz Sample rate */
188 #define AC97_SC_DRS 0x4000 /* Double Rate S/PDIF */
189 #define AC97_SC_V 0x8000 /* Validity status */
190
191 /* Interrupt and Paging bit defines (AC'97 2.3) */
192 #define AC97_PAGE_MASK 0x000f /* Page Selector */
193 #define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */
194 #define AC97_PAGE_1 1 /* Extended Codec Registers page 1 */
195 #define AC97_INT_ENABLE 0x0800 /* Interrupt Enable */
196 #define AC97_INT_SENSE 0x1000 /* Sense Cycle */
197 #define AC97_INT_CAUSE_SENSE 0x2000 /* Sense Cycle Completed (RO) */
198 #define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */
199 #define AC97_INT_STATUS 0x8000 /* Interrupt Status */
200
201 /* extended modem ID bit defines */
202 #define AC97_MEI_LINE1 0x0001 /* Line1 present */
203 #define AC97_MEI_LINE2 0x0002 /* Line2 present */
204 #define AC97_MEI_HANDSET 0x0004 /* Handset present */
205 #define AC97_MEI_CID1 0x0008 /* caller ID decode for Line1 is supported */
206 #define AC97_MEI_CID2 0x0010 /* caller ID decode for Line2 is supported */
207 #define AC97_MEI_ADDR_MASK 0xc000 /* physical codec ID (address) */
208 #define AC97_MEI_ADDR_SHIFT 14
209
210 /* extended modem status and control bit defines */
211 #define AC97_MEA_GPIO 0x0001 /* GPIO is ready (ro) */
212 #define AC97_MEA_MREF 0x0002 /* Vref is up to nominal level (ro) */
213 #define AC97_MEA_ADC1 0x0004 /* ADC1 operational (ro) */
214 #define AC97_MEA_DAC1 0x0008 /* DAC1 operational (ro) */
215 #define AC97_MEA_ADC2 0x0010 /* ADC2 operational (ro) */
216 #define AC97_MEA_DAC2 0x0020 /* DAC2 operational (ro) */
217 #define AC97_MEA_HADC 0x0040 /* HADC operational (ro) */
218 #define AC97_MEA_HDAC 0x0080 /* HDAC operational (ro) */
219 #define AC97_MEA_PRA 0x0100 /* GPIO power down (high) */
220 #define AC97_MEA_PRB 0x0200 /* reserved */
221 #define AC97_MEA_PRC 0x0400 /* ADC1 power down (high) */
222 #define AC97_MEA_PRD 0x0800 /* DAC1 power down (high) */
223 #define AC97_MEA_PRE 0x1000 /* ADC2 power down (high) */
224 #define AC97_MEA_PRF 0x2000 /* DAC2 power down (high) */
225 #define AC97_MEA_PRG 0x4000 /* HADC power down (high) */
226 #define AC97_MEA_PRH 0x8000 /* HDAC power down (high) */
227
228 /* modem gpio status defines */
229 #define AC97_GPIO_LINE1_OH 0x0001 /* Off Hook Line1 */
230 #define AC97_GPIO_LINE1_RI 0x0002 /* Ring Detect Line1 */
231 #define AC97_GPIO_LINE1_CID 0x0004 /* Caller ID path enable Line1 */
232 #define AC97_GPIO_LINE1_LCS 0x0008 /* Loop Current Sense Line1 */
233 #define AC97_GPIO_LINE1_PULSE 0x0010 /* Opt./ Pulse Dial Line1 (out) */
234 #define AC97_GPIO_LINE1_HL1R 0x0020 /* Opt./ Handset to Line1 relay control (out) */
235 #define AC97_GPIO_LINE1_HOHD 0x0040 /* Opt./ Handset off hook detect Line1 (in) */
236 #define AC97_GPIO_LINE12_AC 0x0080 /* Opt./ Int.bit 1 / Line1/2 AC (out) */
237 #define AC97_GPIO_LINE12_DC 0x0100 /* Opt./ Int.bit 2 / Line1/2 DC (out) */
238 #define AC97_GPIO_LINE12_RS 0x0200 /* Opt./ Int.bit 3 / Line1/2 RS (out) */
239 #define AC97_GPIO_LINE2_OH 0x0400 /* Off Hook Line2 */
240 #define AC97_GPIO_LINE2_RI 0x0800 /* Ring Detect Line2 */
241 #define AC97_GPIO_LINE2_CID 0x1000 /* Caller ID path enable Line2 */
242 #define AC97_GPIO_LINE2_LCS 0x2000 /* Loop Current Sense Line2 */
243 #define AC97_GPIO_LINE2_PULSE 0x4000 /* Opt./ Pulse Dial Line2 (out) */
244 #define AC97_GPIO_LINE2_HL1R 0x8000 /* Opt./ Handset to Line2 relay control (out) */
245
246 /* specific - SigmaTel */
247 #define AC97_SIGMATEL_OUTSEL 0x64 /* Output Select, STAC9758 */
248 #define AC97_SIGMATEL_INSEL 0x66 /* Input Select, STAC9758 */
249 #define AC97_SIGMATEL_IOMISC 0x68 /* STAC9758 */
250 #define AC97_SIGMATEL_ANALOG 0x6c /* Analog Special */
251 #define AC97_SIGMATEL_DAC2INVERT 0x6e
252 #define AC97_SIGMATEL_BIAS1 0x70
253 #define AC97_SIGMATEL_BIAS2 0x72
254 #define AC97_SIGMATEL_VARIOUS 0x72 /* STAC9758 */
255 #define AC97_SIGMATEL_MULTICHN 0x74 /* Multi-Channel programming */
256 #define AC97_SIGMATEL_CIC1 0x76
257 #define AC97_SIGMATEL_CIC2 0x78
258
259 /* specific - Analog Devices */
260 #define AC97_AD_TEST 0x5a /* test register */
261 #define AC97_AD_CODEC_CFG 0x70 /* codec configuration */
262 #define AC97_AD_JACK_SPDIF 0x72 /* Jack Sense & S/PDIF */
263 #define AC97_AD_SERIAL_CFG 0x74 /* Serial Configuration */
264 #define AC97_AD_MISC 0x76 /* Misc Control Bits */
265
266 /* specific - Cirrus Logic */
267 #define AC97_CSR_ACMODE 0x5e /* AC Mode Register */
268 #define AC97_CSR_MISC_CRYSTAL 0x60 /* Misc Crystal Control */
269 #define AC97_CSR_SPDIF 0x68 /* S/PDIF Register */
270 #define AC97_CSR_SERIAL 0x6a /* Serial Port Control */
271 #define AC97_CSR_SPECF_ADDR 0x6c /* Special Feature Address */
272 #define AC97_CSR_SPECF_DATA 0x6e /* Special Feature Data */
273 #define AC97_CSR_BDI_STATUS 0x7a /* BDI Status */
274
275 /* specific - Conexant */
276 #define AC97_CXR_AUDIO_MISC 0x5c
277 #define AC97_CXR_SPDIFEN (1<<3)
278 #define AC97_CXR_COPYRGT (1<<2)
279 #define AC97_CXR_SPDIF_MASK (3<<0)
280 #define AC97_CXR_SPDIF_PCM 0x0
281 #define AC97_CXR_SPDIF_AC3 0x2
282
283 /* specific - ALC */
284 #define AC97_ALC650_SPDIF_INPUT_STATUS1 0x60
285 /* S/PDIF input status 1 bit defines */
286 #define AC97_ALC650_PRO 0x0001 /* Professional status */
287 #define AC97_ALC650_NAUDIO 0x0002 /* Non audio stream */
288 #define AC97_ALC650_COPY 0x0004 /* Copyright status */
289 #define AC97_ALC650_PRE 0x0038 /* Preemphasis status */
290 #define AC97_ALC650_PRE_SHIFT 3
291 #define AC97_ALC650_MODE 0x00C0 /* Preemphasis status */
292 #define AC97_ALC650_MODE_SHIFT 6
293 #define AC97_ALC650_CC_MASK 0x7f00 /* Category Code mask */
294 #define AC97_ALC650_CC_SHIFT 8
295 #define AC97_ALC650_L 0x8000 /* Generation Level status */
296
297 #define AC97_ALC650_SPDIF_INPUT_STATUS2 0x62
298 /* S/PDIF input status 2 bit defines */
299 #define AC97_ALC650_SOUCE_MASK 0x000f /* Source number */
300 #define AC97_ALC650_CHANNEL_MASK 0x00f0 /* Channel number */
301 #define AC97_ALC650_CHANNEL_SHIFT 4
302 #define AC97_ALC650_SPSR_MASK 0x0f00 /* S/PDIF Sample Rate bits */
303 #define AC97_ALC650_SPSR_SHIFT 8
304 #define AC97_ALC650_SPSR_44K 0x0000 /* Use 44.1kHz Sample rate */
305 #define AC97_ALC650_SPSR_48K 0x0200 /* Use 48kHz Sample rate */
306 #define AC97_ALC650_SPSR_32K 0x0300 /* Use 32kHz Sample rate */
307 #define AC97_ALC650_CLOCK_ACCURACY 0x3000 /* Clock accuracy */
308 #define AC97_ALC650_CLOCK_SHIFT 12
309 #define AC97_ALC650_CLOCK_LOCK 0x4000 /* Clock locked status */
310 #define AC97_ALC650_V 0x8000 /* Validity status */
311
312 #define AC97_ALC650_SURR_DAC_VOL 0x64
313 #define AC97_ALC650_LFE_DAC_VOL 0x66
314 #define AC97_ALC650_UNKNOWN1 0x68
315 #define AC97_ALC650_MULTICH 0x6a
316 #define AC97_ALC650_UNKNOWN2 0x6c
317 #define AC97_ALC650_REVISION 0x6e
318 #define AC97_ALC650_UNKNOWN3 0x70
319 #define AC97_ALC650_UNKNOWN4 0x72
320 #define AC97_ALC650_MISC 0x74
321 #define AC97_ALC650_GPIO_SETUP 0x76
322 #define AC97_ALC650_GPIO_STATUS 0x78
323 #define AC97_ALC650_CLOCK 0x7a
324
325 /* specific - Yamaha YMF753 */
326 #define AC97_YMF753_DIT_CTRL2 0x66 /* DIT Control 2 */
327 #define AC97_YMF753_3D_MODE_SEL 0x68 /* 3D Mode Select */
328
329 /* specific - C-Media */
330 #define AC97_CM9738_VENDOR_CTRL 0x5a
331 #define AC97_CM9739_MULTI_CHAN 0x64
332 #define AC97_CM9739_SPDIF_IN_STATUS 0x68 /* 32bit */
333 #define AC97_CM9739_SPDIF_CTRL 0x6c
334
335 /* specific - wolfson */
336 #define AC97_WM97XX_FMIXER_VOL 0x72
337 #define AC97_WM9704_RMIXER_VOL 0x74
338 #define AC97_WM9704_TEST 0x5a
339 #define AC97_WM9704_RPCM_VOL 0x70
340 #define AC97_WM9711_OUT3VOL 0x16
341
342
343 /* ac97->scaps */
344 #define AC97_SCAP_AUDIO (1<<0) /* audio codec 97 */
345 #define AC97_SCAP_MODEM (1<<1) /* modem codec 97 */
346 #define AC97_SCAP_SURROUND_DAC (1<<2) /* surround L&R DACs are present */
347 #define AC97_SCAP_CENTER_LFE_DAC (1<<3) /* center and LFE DACs are present */
348 #define AC97_SCAP_SKIP_AUDIO (1<<4) /* skip audio part of codec */
349 #define AC97_SCAP_SKIP_MODEM (1<<5) /* skip modem part of codec */
350 #define AC97_SCAP_INDEP_SDIN (1<<6) /* independent SDIN */
351
352 /* ac97->flags */
353 #define AC97_HAS_PC_BEEP (1<<0) /* force PC Speaker usage */
354 #define AC97_AD_MULTI (1<<1) /* Analog Devices - multi codecs */
355 #define AC97_CS_SPDIF (1<<2) /* Cirrus Logic uses funky SPDIF */
356 #define AC97_CX_SPDIF (1<<3) /* Conexant's spdif interface */
357 #define AC97_STEREO_MUTES (1<<4) /* has stereo mute bits */
358
359 /* rates indexes */
360 #define AC97_RATES_FRONT_DAC 0
361 #define AC97_RATES_SURR_DAC 1
362 #define AC97_RATES_LFE_DAC 2
363 #define AC97_RATES_ADC 3
364 #define AC97_RATES_MIC_ADC 4
365 #define AC97_RATES_SPDIF 5
366
367 /* shared controllers */
368 enum {
369 AC97_SHARED_TYPE_NONE,
370 AC97_SHARED_TYPE_ICH,
371 AC97_SHARED_TYPE_ATIIXP,
372 AC97_SHARED_TYPES
373 };
374
375 /*
376 *
377 */
378
379 typedef struct _snd_ac97_bus ac97_bus_t;
380 typedef struct _snd_ac97_bus_ops ac97_bus_ops_t;
381 typedef struct _snd_ac97_template ac97_template_t;
382 typedef struct _snd_ac97 ac97_t;
383
384 enum ac97_pcm_cfg {
385 AC97_PCM_CFG_FRONT = 2,
386 AC97_PCM_CFG_REAR = 10, /* alias surround */
387 AC97_PCM_CFG_LFE = 11, /* center + lfe */
388 AC97_PCM_CFG_40 = 4, /* front + rear */
389 AC97_PCM_CFG_51 = 6, /* front + rear + center/lfe */
390 AC97_PCM_CFG_SPDIF = 20
391 };
392
393 /* PCM allocation */
394 struct ac97_pcm {
395 ac97_bus_t *bus;
396 unsigned int stream: 1, /* stream type: 1 = capture */
397 exclusive: 1, /* exclusive mode, don't override with other pcms */
398 copy_flag: 1, /* lowlevel driver must fill all entries */
399 spdif: 1; /* spdif pcm */
400 unsigned short aslots; /* active slots */
401 unsigned int rates; /* available rates */
402 struct {
403 unsigned short slots; /* driver input: requested AC97 slot numbers */
404 unsigned short rslots[4]; /* allocated slots per codecs */
405 unsigned char rate_table[4];
406 ac97_t *codec[4]; /* allocated codecs */
407 } r[2]; /* 0 = standard rates, 1 = double rates */
408 unsigned long private_value; /* used by the hardware driver */
409 };
410
411 struct snd_ac97_build_ops {
412 int (*build_3d) (ac97_t *ac97);
413 int (*build_specific) (ac97_t *ac97);
414 int (*build_spdif) (ac97_t *ac97);
415 int (*build_post_spdif) (ac97_t *ac97);
416 };
417
418 struct _snd_ac97_bus_ops {
419 void (*reset) (ac97_t *ac97);
420 void (*write) (ac97_t *ac97, unsigned short reg, unsigned short val);
421 unsigned short (*read) (ac97_t *ac97, unsigned short reg);
422 void (*wait) (ac97_t *ac97);
423 void (*init) (ac97_t *ac97);
424 };
425
426 struct _snd_ac97_bus {
427 /* -- lowlevel (hardware) driver specific -- */
428 ac97_bus_ops_t *ops;
429 void *private_data;
430 void (*private_free) (ac97_bus_t *bus);
431 /* --- */
432 snd_card_t *card;
433 unsigned short num; /* bus number */
434 unsigned short no_vra: 1, /* bridge doesn't support VRA */
435 isdin: 1;/* independent SDIN */
436 unsigned int clock; /* AC'97 base clock (usually 48000Hz) */
437 spinlock_t bus_lock; /* used mainly for slot allocation */
438 unsigned short used_slots[2][4]; /* actually used PCM slots */
439 unsigned short pcms_count; /* count of PCMs */
440 struct ac97_pcm *pcms;
441 unsigned int shared_type; /* type of shared controller betwen audio and modem */
442 ac97_t *codec[4];
443 snd_info_entry_t *proc;
444 };
445
446 struct _snd_ac97_template {
447 void *private_data;
448 void (*private_free) (ac97_t *ac97);
449 struct pci_dev *pci; /* assigned PCI device - used for quirks */
450 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
451 unsigned short addr; /* physical address of codec [0-3] */
452 unsigned int scaps; /* driver capabilities */
453 unsigned int limited_regs; /* allow limited registers only */
454 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
455 };
456
457 struct _snd_ac97 {
458 /* -- lowlevel (hardware) driver specific -- */
459 struct snd_ac97_build_ops * build_ops;
460 void *private_data;
461 void (*private_free) (ac97_t *ac97);
462 /* --- */
463 ac97_bus_t *bus;
464 struct pci_dev *pci; /* assigned PCI device - used for quirks */
465 snd_info_entry_t *proc;
466 snd_info_entry_t *proc_regs;
467 unsigned short subsystem_vendor;
468 unsigned short subsystem_device;
469 spinlock_t reg_lock;
470 struct semaphore mutex; /* mutex for AD18xx multi-codecs and paging (2.3) */
471 unsigned short num; /* number of codec: 0 = primary, 1 = secondary */
472 unsigned short addr; /* physical address of codec [0-3] */
473 unsigned int id; /* identification of codec */
474 unsigned short caps; /* capabilities (register 0) */
475 unsigned short ext_id; /* extended feature identification (register 28) */
476 unsigned short ext_mid; /* extended modem ID (register 3C) */
477 unsigned int scaps; /* driver capabilities */
478 unsigned int flags; /* specific code */
479 unsigned int rates[6]; /* see AC97_RATES_* defines */
480 unsigned int spdif_status;
481 unsigned short regs[0x80]; /* register cache */
482 unsigned int limited_regs; /* allow limited registers only */
483 DECLARE_BITMAP(reg_accessed, 0x80); /* bit flags */
484 union { /* vendor specific code */
485 struct {
486 unsigned short unchained[3]; // 0 = C34, 1 = C79, 2 = C69
487 unsigned short chained[3]; // 0 = C34, 1 = C79, 2 = C69
488 unsigned short id[3]; // codec IDs (lower 16-bit word)
489 unsigned short pcmreg[3]; // PCM registers
490 unsigned short codec_cfg[3]; // CODEC_CFG bits
491 } ad18xx;
492 unsigned int dev_flags; /* device specific */
493 } spec;
494 };
495
496 /* conditions */
497 static inline int ac97_is_audio(ac97_t * ac97)
498 {
499 return (ac97->scaps & AC97_SCAP_AUDIO);
500 }
501 static inline int ac97_is_modem(ac97_t * ac97)
502 {
503 return (ac97->scaps & AC97_SCAP_MODEM);
504 }
505 static inline int ac97_is_rev22(ac97_t * ac97)
506 {
507 return (ac97->ext_id & AC97_EI_REV_MASK) >= AC97_EI_REV_22;
508 }
509 static inline int ac97_can_amap(ac97_t * ac97)
510 {
511 return (ac97->ext_id & AC97_EI_AMAP) != 0;
512 }
513 static inline int ac97_can_spdif(ac97_t * ac97)
514 {
515 return (ac97->ext_id & AC97_EI_SPDIF) != 0;
516 }
517
518 /* functions */
519 int snd_ac97_bus(snd_card_t *card, int num, ac97_bus_ops_t *ops, void *private_data, ac97_bus_t **rbus); /* create new AC97 bus */
520 int snd_ac97_mixer(ac97_bus_t *bus, ac97_template_t *template, ac97_t **rac97); /* create mixer controls */
521
522 void snd_ac97_write(ac97_t *ac97, unsigned short reg, unsigned short value);
523 unsigned short snd_ac97_read(ac97_t *ac97, unsigned short reg);
524 void snd_ac97_write_cache(ac97_t *ac97, unsigned short reg, unsigned short value);
525 int snd_ac97_update(ac97_t *ac97, unsigned short reg, unsigned short value);
526 int snd_ac97_update_bits(ac97_t *ac97, unsigned short reg, unsigned short mask, unsigned short value);
527 #ifdef CONFIG_PM
528 void snd_ac97_suspend(ac97_t *ac97);
529 void snd_ac97_resume(ac97_t *ac97);
530 #endif
531
532 /* quirk types */
533 enum {
534 AC97_TUNE_DEFAULT = -1, /* use default from quirk list (not valid in list) */
535 AC97_TUNE_NONE = 0, /* nothing extra to do */
536 AC97_TUNE_HP_ONLY, /* headphone (true line-out) control as master only */
537 AC97_TUNE_SWAP_HP, /* swap headphone and master controls */
538 AC97_TUNE_SWAP_SURROUND, /* swap master and surround controls */
539 AC97_TUNE_AD_SHARING, /* for AD1985, turn on OMS bit and use headphone */
540 AC97_TUNE_ALC_JACK, /* for Realtek, enable JACK detection */
541 };
542
543 struct ac97_quirk {
544 unsigned short vendor; /* PCI vendor id */
545 unsigned short device; /* PCI device id */
546 unsigned short mask; /* device id bit mask, 0 = accept all */
547 const char *name; /* name shown as info */
548 int type; /* quirk type above */
549 };
550
551 int snd_ac97_tune_hardware(ac97_t *ac97, struct ac97_quirk *quirk, int override);
552 int snd_ac97_set_rate(ac97_t *ac97, int reg, unsigned short rate);
553
554 int snd_ac97_pcm_assign(ac97_bus_t *ac97,
555 unsigned short pcms_count,
556 const struct ac97_pcm *pcms);
557 int snd_ac97_pcm_open(struct ac97_pcm *pcm, unsigned int rate,
558 enum ac97_pcm_cfg cfg, unsigned short slots);
559 int snd_ac97_pcm_close(struct ac97_pcm *pcm);
560
561 #endif /* __SOUND_AC97_CODEC_H */
MOXA 2.6.9 from sdlinux-moxaart.tgz