1 /* $Id: rwsem.h,v 1.5 2001/11/18 00:12:56 davem Exp $
2 * rwsem.h: R/W semaphores implemented using CAS
4 * Written by David S. Miller (davem@redhat.com), 2001.
5 * Derived from asm-i386/rwsem.h
7 #ifndef _SPARC64_RWSEM_H
8 #define _SPARC64_RWSEM_H
10 #ifndef _LINUX_RWSEM_H
11 #error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
16 #include <linux/list.h>
17 #include <linux/spinlock.h>
23 #define RWSEM_UNLOCKED_VALUE 0x00000000
24 #define RWSEM_ACTIVE_BIAS 0x00000001
25 #define RWSEM_ACTIVE_MASK 0x0000ffff
26 #define RWSEM_WAITING_BIAS 0xffff0000
27 #define RWSEM_ACTIVE_READ_BIAS RWSEM_ACTIVE_BIAS
28 #define RWSEM_ACTIVE_WRITE_BIAS (RWSEM_WAITING_BIAS + RWSEM_ACTIVE_BIAS)
30 struct list_head wait_list
;
33 #define __RWSEM_INITIALIZER(name) \
34 { RWSEM_UNLOCKED_VALUE, SPIN_LOCK_UNLOCKED, LIST_HEAD_INIT((name).wait_list) }
36 #define DECLARE_RWSEM(name) \
37 struct rw_semaphore name = __RWSEM_INITIALIZER(name)
39 static __inline__
void init_rwsem(struct rw_semaphore
*sem
)
41 sem
->count
= RWSEM_UNLOCKED_VALUE
;
42 spin_lock_init(&sem
->wait_lock
);
43 INIT_LIST_HEAD(&sem
->wait_list
);
46 extern void __down_read(struct rw_semaphore
*sem
);
47 extern int __down_read_trylock(struct rw_semaphore
*sem
);
48 extern void __down_write(struct rw_semaphore
*sem
);
49 extern int __down_write_trylock(struct rw_semaphore
*sem
);
50 extern void __up_read(struct rw_semaphore
*sem
);
51 extern void __up_write(struct rw_semaphore
*sem
);
52 extern void __downgrade_write(struct rw_semaphore
*sem
);
54 static __inline__
int rwsem_atomic_update(int delta
, struct rw_semaphore
*sem
)
59 "1:\tlduw [%2], %%g5\n\t"
60 "add %%g5, %1, %%g7\n\t"
61 "cas [%2], %%g5, %%g7\n\t"
63 "bne,pn %%icc, 1b\n\t"
64 " membar #StoreLoad | #StoreStore\n\t"
67 : "0" (tmp
), "r" (sem
)
68 : "g5", "g7", "memory", "cc");
73 #define rwsem_atomic_add rwsem_atomic_update
75 static __inline__ __u16
rwsem_cmpxchgw(struct rw_semaphore
*sem
, __u16 __old
, __u16 __new
)
77 u32 old
= (sem
->count
& 0xffff0000) | (u32
) __old
;
78 u32
new = (old
& 0xffff0000) | (u32
) __new
;
82 __asm__
__volatile__("cas [%2], %3, %0\n\t"
83 "membar #StoreLoad | #StoreStore"
85 : "0" (new), "r" (sem
), "r" (old
)
88 /* To give the same semantics as x86 cmpxchgw, keep trying
89 * if only the upper 16-bits changed.
92 ((prev
& 0xffff) == (old
& 0xffff)))
98 static __inline__
signed long rwsem_cmpxchg(struct rw_semaphore
*sem
, signed long old
, signed long new)
100 return cmpxchg(&sem
->count
,old
,new);
103 #endif /* __KERNEL__ */
105 #endif /* _SPARC64_RWSEM_H */