2 * include/asm-sh/watchdog.h
4 * Copyright (C) 2002, 2003 Paul Mundt
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 #ifndef __ASM_SH_WATCHDOG_H
12 #define __ASM_SH_WATCHDOG_H
14 #include <linux/types.h>
15 #include <linux/config.h>
16 #include <asm/cpu/watchdog.h>
20 * See asm/cpu-sh2/watchdog.h for explanation of this stupidity..
23 # define WTCNT_R WTCNT
27 # define WTCSR_R WTCSR
30 #define WTCNT_HIGH 0x5a
31 #define WTCSR_HIGH 0xa5
33 #define WTCSR_CKS2 0x04
34 #define WTCSR_CKS1 0x02
35 #define WTCSR_CKS0 0x01
38 * CKS0-2 supports a number of clock division ratios. At the time the watchdog
39 * is enabled, it defaults to a 41 usec overflow period .. we overload this to
40 * something a little more reasonable, and really can't deal with anything
41 * lower than WTCSR_CKS_1024, else we drop back into the usec range.
43 * Clock Division Ratio Overflow Period
44 * --------------------------------------------
45 * 1/32 (initial value) 41 usecs
54 #define WTCSR_CKS_32 0x00
55 #define WTCSR_CKS_64 0x01
56 #define WTCSR_CKS_128 0x02
57 #define WTCSR_CKS_256 0x03
58 #define WTCSR_CKS_512 0x04
59 #define WTCSR_CKS_1024 0x05
60 #define WTCSR_CKS_2048 0x06
61 #define WTCSR_CKS_4096 0x07
64 * sh_wdt_read_cnt - Read from Counter
66 * Reads back the WTCNT value.
68 static inline __u8
sh_wdt_read_cnt(void)
70 return ctrl_inb(WTCNT_R
);
74 * sh_wdt_write_cnt - Write to Counter
76 * @val: Value to write
78 * Writes the given value @val to the lower byte of the timer counter.
79 * The upper byte is set manually on each write.
81 static inline void sh_wdt_write_cnt(__u8 val
)
83 ctrl_outw((WTCNT_HIGH
<< 8) | (__u16
)val
, WTCNT
);
87 * sh_wdt_read_csr - Read from Control/Status Register
89 * Reads back the WTCSR value.
91 static inline __u8
sh_wdt_read_csr(void)
93 return ctrl_inb(WTCSR_R
);
97 * sh_wdt_write_csr - Write to Control/Status Register
99 * @val: Value to write
101 * Writes the given value @val to the lower byte of the control/status
102 * register. The upper byte is set manually on each write.
104 static inline void sh_wdt_write_csr(__u8 val
)
106 ctrl_outw((WTCSR_HIGH
<< 8) | (__u16
)val
, WTCSR
);
109 #endif /* __ASM_SH_WATCHDOG_H */