include/asm-ppc64/paca.h

   1 #ifndef _PPC64_PACA_H
   2 #define _PPC64_PACA_H
   3
   4 /*
   5  * include/asm-ppc64/paca.h
   6  *
   7  * This control block defines the PACA which defines the processor
   8  * specific data for each logical processor on the system.
   9  * There are some pointers defined that are utilized by PLIC.
  10  *
  11  * C 2001 PPC 64 Team, IBM Corp
  12  *
  13  * This program is free software; you can redistribute it and/or
  14  * modify it under the terms of the GNU General Public License
  15  * as published by the Free Software Foundation; either version
  16  * 2 of the License, or (at your option) any later version.
  17  */
  18
  19 #include        <linux/config.h>
  20 #include        <asm/types.h>
  21 #include        <asm/iSeries/ItLpPaca.h>
  22 #include        <asm/iSeries/ItLpRegSave.h>
  23 #include        <asm/mmu.h>
  24
  25 extern struct paca_struct paca[];
  26 register struct paca_struct *local_paca asm("r13");
  27 #define get_paca()      local_paca
  28
  29 struct task_struct;
  30 struct ItLpQueue;
  31
  32 /*
  33  * Defines the layout of the paca.
  34  *
  35  * This structure is not directly accessed by firmware or the service
  36  * processor except for the first two pointers that point to the
  37  * ItLpPaca area and the ItLpRegSave area for this CPU.  Both the
  38  * ItLpPaca and ItLpRegSave objects are currently contained within the
  39  * PACA but they do not need to be.
  40  */
  41 struct paca_struct {
  42         /*
  43          * Because hw_cpu_id, unlike other paca fields, is accessed
  44          * routinely from other CPUs (from the IRQ code), we stick to
  45          * read-only (after boot) fields in the first cacheline to
  46          * avoid cacheline bouncing.
  47          */
  48
  49         /*
  50          * MAGIC: These first two pointers can't be moved - they're
  51          * accessed by the firmware
  52          */
  53         struct ItLpPaca *lppaca_ptr;    /* Pointer to LpPaca for PLIC */
  54         struct ItLpRegSave *reg_save_ptr; /* Pointer to LpRegSave for PLIC */
  55
  56         /*
  57          * MAGIC: the spinlock functions in arch/ppc64/lib/locks.c
  58          * load lock_token and paca_index with a single lwz
  59          * instruction.  They must travel together and be properly
  60          * aligned.
  61          */
  62         u16 lock_token;                 /* Constant 0x8000, used in locks */
  63         u16 paca_index;                 /* Logical processor number */
  64
  65         u32 default_decr;               /* Default decrementer value */
  66         struct ItLpQueue *lpqueue_ptr;  /* LpQueue handled by this CPU */
  67         u64 kernel_toc;                 /* Kernel TOC address */
  68         u64 stab_real;                  /* Absolute address of segment table */
  69         u64 stab_addr;                  /* Virtual address of segment table */
  70         void *emergency_sp;             /* pointer to emergency stack */
  71         u16 hw_cpu_id;                  /* Physical processor number */
  72         u8 cpu_start;                   /* At startup, processor spins until */
  73                                         /* this becomes non-zero. */
  74
  75         /*
  76          * Now, starting in cacheline 2, the exception save areas
  77          */
  78         u64 exgen[8] __attribute__((aligned(0x80))); /* used for most interrupts/exceptions */
  79         u64 exmc[8];            /* used for machine checks */
  80         u64 exslb[8];           /* used for SLB/segment table misses
  81                                  * on the linear mapping */
  82         mm_context_t context;
  83         u16 slb_cache[SLB_CACHE_ENTRIES];
  84         u16 slb_cache_ptr;
  85
  86         /*
  87          * then miscellaneous read-write fields
  88          */
  89         struct task_struct *__current;  /* Pointer to current */
  90         u64 kstack;                     /* Saved Kernel stack addr */
  91         u64 stab_rr;                    /* stab/slb round-robin counter */
  92         u64 next_jiffy_update_tb;       /* TB value for next jiffy update */
  93         u64 saved_r1;                   /* r1 save for RTAS calls */
  94         u64 saved_msr;                  /* MSR saved here by enter_rtas */
  95         u32 lpevent_count;              /* lpevents processed  */
  96         u8 proc_enabled;                /* irq soft-enable flag */
  97
  98         /* not yet used */
  99         u64 exdsi[8];           /* used for linear mapping hash table misses */
 100
 101         /*
 102          * iSeries structues which the hypervisor knows about - Not
 103          * sure if these particularly need to be cacheline aligned.
 104          * The lppaca is also used on POWER5 pSeries boxes.
 105          */
 106         struct ItLpPaca lppaca __attribute__((aligned(0x80)));
 107 #ifdef CONFIG_PPC_ISERIES
 108         struct ItLpRegSave reg_save;
 109 #endif
 110 };
 111
 112 #endif /* _PPC64_PACA_H */