include/asm-ppc/ppc4xx_dma.h

   1 /*
   2  * include/asm-ppc/ppc4xx_dma.h
   3  *
   4  * IBM PPC4xx DMA engine library
   5  *
   6  * Copyright 2000-2004 MontaVista Software Inc.
   7  *
   8  * Cleaned up a bit more, Matt Porter <mporter@kernel.crashing.org>
   9  *
  10  * Original code by Armin Kuster <akuster@mvista.com>
  11  * and Pete Popov <ppopov@mvista.com>
  12  *
  13  * This program is free software; you can redistribute  it and/or modify it
  14  * under  the terms of  the GNU General  Public License as published by the
  15  * Free Software Foundation;  either version 2 of the  License, or (at your
  16  * option) any later version.
  17  *
  18  * You should have received a copy of the  GNU General Public License along
  19  * with this program; if not, write  to the Free Software Foundation, Inc.,
  20  * 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #ifdef __KERNEL__
  24 #ifndef __ASMPPC_PPC4xx_DMA_H
  25 #define __ASMPPC_PPC4xx_DMA_H
  26
  27 #include <linux/config.h>
  28 #include <linux/types.h>
  29 #include <asm/mmu.h>
  30 #include <asm/ibm4xx.h>
  31
  32 #undef DEBUG_4xxDMA
  33
  34 #define MAX_PPC4xx_DMA_CHANNELS         4
  35
  36 /* in arch/ppc/kernel/setup.c -- Cort */
  37 extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ;
  38
  39 /*
  40  * Function return status codes
  41  * These values are used to indicate whether or not the function
  42  * call was successful, or a bad/invalid parameter was passed.
  43  */
  44 #define DMA_STATUS_GOOD                 0
  45 #define DMA_STATUS_BAD_CHANNEL          1
  46 #define DMA_STATUS_BAD_HANDLE           2
  47 #define DMA_STATUS_BAD_MODE             3
  48 #define DMA_STATUS_NULL_POINTER         4
  49 #define DMA_STATUS_OUT_OF_MEMORY        5
  50 #define DMA_STATUS_SGL_LIST_EMPTY       6
  51 #define DMA_STATUS_GENERAL_ERROR        7
  52 #define DMA_STATUS_CHANNEL_NOTFREE      8
  53
  54 #define DMA_CHANNEL_BUSY                0x80000000
  55
  56 /*
  57  * These indicate status as returned from the DMA Status Register.
  58  */
  59 #define DMA_STATUS_NO_ERROR     0
  60 #define DMA_STATUS_CS           1       /* Count Status        */
  61 #define DMA_STATUS_TS           2       /* Transfer Status     */
  62 #define DMA_STATUS_DMA_ERROR    3       /* DMA Error Occurred  */
  63 #define DMA_STATUS_DMA_BUSY     4       /* The channel is busy */
  64
  65
  66 /*
  67  * DMA Channel Control Registers
  68  */
  69
  70 #ifdef CONFIG_44x
  71 #define PPC4xx_DMA_64BIT
  72 #define DMA_CR_OFFSET 1
  73 #else
  74 #define DMA_CR_OFFSET 0
  75 #endif
  76
  77 #define DMA_CE_ENABLE        (1<<31)    /* DMA Channel Enable */
  78 #define SET_DMA_CE_ENABLE(x) (((x)&0x1)<<31)
  79 #define GET_DMA_CE_ENABLE(x) (((x)&DMA_CE_ENABLE)>>31)
  80
  81 #define DMA_CIE_ENABLE        (1<<30)   /* DMA Channel Interrupt Enable */
  82 #define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30)
  83 #define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30)
  84
  85 #define DMA_TD                (1<<29)
  86 #define SET_DMA_TD(x)         (((x)&0x1)<<29)
  87 #define GET_DMA_TD(x)         (((x)&DMA_TD)>>29)
  88
  89 #define DMA_PL                (1<<28)   /* Peripheral Location */
  90 #define SET_DMA_PL(x)         (((x)&0x1)<<28)
  91 #define GET_DMA_PL(x)         (((x)&DMA_PL)>>28)
  92
  93 #define EXTERNAL_PERIPHERAL    0
  94 #define INTERNAL_PERIPHERAL    1
  95
  96 #define SET_DMA_PW(x)     (((x)&0x3)<<(26-DMA_CR_OFFSET))       /* Peripheral Width */
  97 #define DMA_PW_MASK       SET_DMA_PW(3)
  98 #define   PW_8                 0
  99 #define   PW_16                1
 100 #define   PW_32                2
 101 #define   PW_64                3
 102 /* FIXME: Add PW_128 support for 440GP DMA block */
 103 #define GET_DMA_PW(x)     (((x)&DMA_PW_MASK)>>(26-DMA_CR_OFFSET))
 104
 105 #define DMA_DAI           (1<<(25-DMA_CR_OFFSET))       /* Destination Address Increment */
 106 #define SET_DMA_DAI(x)    (((x)&0x1)<<(25-DMA_CR_OFFSET))
 107
 108 #define DMA_SAI           (1<<(24-DMA_CR_OFFSET))       /* Source Address Increment */
 109 #define SET_DMA_SAI(x)    (((x)&0x1)<<(24-DMA_CR_OFFSET))
 110
 111 #define DMA_BEN           (1<<(23-DMA_CR_OFFSET))       /* Buffer Enable */
 112 #define SET_DMA_BEN(x)    (((x)&0x1)<<(23-DMA_CR_OFFSET))
 113
 114 #define SET_DMA_TM(x)     (((x)&0x3)<<(21-DMA_CR_OFFSET))       /* Transfer Mode */
 115 #define DMA_TM_MASK       SET_DMA_TM(3)
 116 #define   TM_PERIPHERAL        0        /* Peripheral */
 117 #define   TM_RESERVED          1        /* Reserved */
 118 #define   TM_S_MM              2        /* Memory to Memory */
 119 #define   TM_D_MM              3        /* Device Paced Memory to Memory */
 120 #define GET_DMA_TM(x)     (((x)&DMA_TM_MASK)>>(21-DMA_CR_OFFSET))
 121
 122 #define SET_DMA_PSC(x)    (((x)&0x3)<<(19-DMA_CR_OFFSET))       /* Peripheral Setup Cycles */
 123 #define DMA_PSC_MASK      SET_DMA_PSC(3)
 124 #define GET_DMA_PSC(x)    (((x)&DMA_PSC_MASK)>>(19-DMA_CR_OFFSET))
 125
 126 #define SET_DMA_PWC(x)    (((x)&0x3F)<<(13-DMA_CR_OFFSET))      /* Peripheral Wait Cycles */
 127 #define DMA_PWC_MASK      SET_DMA_PWC(0x3F)
 128 #define GET_DMA_PWC(x)    (((x)&DMA_PWC_MASK)>>(13-DMA_CR_OFFSET))
 129
 130 #define SET_DMA_PHC(x)    (((x)&0x7)<<(10-DMA_CR_OFFSET))       /* Peripheral Hold Cycles */
 131 #define DMA_PHC_MASK      SET_DMA_PHC(0x7)
 132 #define GET_DMA_PHC(x)    (((x)&DMA_PHC_MASK)>>(10-DMA_CR_OFFSET))
 133
 134 #define DMA_ETD_OUTPUT     (1<<(9-DMA_CR_OFFSET))       /* EOT pin is a TC output */
 135 #define SET_DMA_ETD(x)     (((x)&0x1)<<(9-DMA_CR_OFFSET))
 136
 137 #define DMA_TCE_ENABLE     (1<<(8-DMA_CR_OFFSET))
 138 #define SET_DMA_TCE(x)     (((x)&0x1)<<(8-DMA_CR_OFFSET))
 139
 140 #define DMA_DEC            (1<<(2)      /* Address Decrement */
 141 #define SET_DMA_DEC(x)     (((x)&0x1)<<2)
 142 #define GET_DMA_DEC(x)     (((x)&DMA_DEC)>>2)
 143
 144 /*
 145  * Transfer Modes
 146  * These modes are defined in a way that makes it possible to
 147  * simply "or" in the value in the control register.
 148  */
 149
 150 #define DMA_MODE_MM             (SET_DMA_TM(TM_S_MM))   /* memory to memory */
 151
 152                                 /* Device-paced memory to memory, */
 153                                 /* device is at source address    */
 154 #define DMA_MODE_MM_DEVATSRC    (DMA_TD | SET_DMA_TM(TM_D_MM))
 155
 156                                 /* Device-paced memory to memory,      */
 157                                 /* device is at destination address    */
 158 #define DMA_MODE_MM_DEVATDST    (SET_DMA_TM(TM_D_MM))
 159
 160 /* 405gp/440gp */
 161 #define SET_DMA_PREFETCH(x)   (((x)&0x3)<<(4-DMA_CR_OFFSET))    /* Memory Read Prefetch */
 162 #define DMA_PREFETCH_MASK      SET_DMA_PREFETCH(3)
 163 #define   PREFETCH_1           0        /* Prefetch 1 Double Word */
 164 #define   PREFETCH_2           1
 165 #define   PREFETCH_4           2
 166 #define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>(4-DMA_CR_OFFSET))
 167
 168 #define DMA_PCE            (1<<(3-DMA_CR_OFFSET))       /* Parity Check Enable */
 169 #define SET_DMA_PCE(x)     (((x)&0x1)<<(3-DMA_CR_OFFSET))
 170 #define GET_DMA_PCE(x)     (((x)&DMA_PCE)>>(3-DMA_CR_OFFSET))
 171
 172 /* stb3x */
 173
 174 #define DMA_ECE_ENABLE (1<<5)
 175 #define SET_DMA_ECE(x) (((x)&0x1)<<5)
 176 #define GET_DMA_ECE(x) (((x)&DMA_ECE_ENABLE)>>5)
 177
 178 #define DMA_TCD_DISABLE (1<<4)
 179 #define SET_DMA_TCD(x) (((x)&0x1)<<4)
 180 #define GET_DMA_TCD(x) (((x)&DMA_TCD_DISABLE)>>4)
 181
 182 typedef uint32_t sgl_handle_t;
 183
 184 #ifdef CONFIG_PPC4xx_EDMA
 185
 186 #define SGL_LIST_SIZE 4096
 187 #define DMA_PPC4xx_SIZE SGL_LIST_SIZE
 188
 189 #define SET_DMA_PRIORITY(x)   (((x)&0x3)<<(6-DMA_CR_OFFSET))    /* DMA Channel Priority */
 190 #define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3)
 191 #define PRIORITY_LOW           0
 192 #define PRIORITY_MID_LOW       1
 193 #define PRIORITY_MID_HIGH      2
 194 #define PRIORITY_HIGH          3
 195 #define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>(6-DMA_CR_OFFSET))
 196
 197 /*
 198  * DMA Polarity Configuration Register
 199  */
 200 #define DMAReq_ActiveLow(chan) (1<<(31-(chan*3)))
 201 #define DMAAck_ActiveLow(chan) (1<<(30-(chan*3)))
 202 #define EOT_ActiveLow(chan)    (1<<(29-(chan*3)))       /* End of Transfer */
 203
 204 /*
 205  * DMA Sleep Mode Register
 206  */
 207 #define SLEEP_MODE_ENABLE (1<<21)
 208
 209 /*
 210  * DMA Status Register
 211  */
 212 #define DMA_CS0           (1<<31)       /* Terminal Count has been reached */
 213 #define DMA_CS1           (1<<30)
 214 #define DMA_CS2           (1<<29)
 215 #define DMA_CS3           (1<<28)
 216
 217 #define DMA_TS0           (1<<27)       /* End of Transfer has been requested */
 218 #define DMA_TS1           (1<<26)
 219 #define DMA_TS2           (1<<25)
 220 #define DMA_TS3           (1<<24)
 221
 222 #define DMA_CH0_ERR       (1<<23)       /* DMA Chanel 0 Error */
 223 #define DMA_CH1_ERR       (1<<22)
 224 #define DMA_CH2_ERR       (1<<21)
 225 #define DMA_CH3_ERR       (1<<20)
 226
 227 #define DMA_IN_DMA_REQ0   (1<<19)       /* Internal DMA Request is pending */
 228 #define DMA_IN_DMA_REQ1   (1<<18)
 229 #define DMA_IN_DMA_REQ2   (1<<17)
 230 #define DMA_IN_DMA_REQ3   (1<<16)
 231
 232 #define DMA_EXT_DMA_REQ0  (1<<15)       /* External DMA Request is pending */
 233 #define DMA_EXT_DMA_REQ1  (1<<14)
 234 #define DMA_EXT_DMA_REQ2  (1<<13)
 235 #define DMA_EXT_DMA_REQ3  (1<<12)
 236
 237 #define DMA_CH0_BUSY      (1<<11)       /* DMA Channel 0 Busy */
 238 #define DMA_CH1_BUSY      (1<<10)
 239 #define DMA_CH2_BUSY       (1<<9)
 240 #define DMA_CH3_BUSY       (1<<8)
 241
 242 #define DMA_SG0            (1<<7)       /* DMA Channel 0 Scatter/Gather in progress */
 243 #define DMA_SG1            (1<<6)
 244 #define DMA_SG2            (1<<5)
 245 #define DMA_SG3            (1<<4)
 246
 247 /*
 248  * DMA SG Command Register
 249  */
 250 #define SSG_ENABLE(chan)        (1<<(31-chan))  /* Start Scatter Gather */
 251 #define SSG_MASK_ENABLE(chan)   (1<<(15-chan))  /* Enable writing to SSG0 bit */
 252
 253 /*
 254  * DMA Scatter/Gather Descriptor Bit fields
 255  */
 256 #define SG_LINK            (1<<31)      /* Link */
 257 #define SG_TCI_ENABLE      (1<<29)      /* Enable Terminal Count Interrupt */
 258 #define SG_ETI_ENABLE      (1<<28)      /* Enable End of Transfer Interrupt */
 259 #define SG_ERI_ENABLE      (1<<27)      /* Enable Error Interrupt */
 260 #define SG_COUNT_MASK       0xFFFF      /* Count Field */
 261
 262 #define SET_DMA_CONTROL \
 263                 (SET_DMA_CIE_ENABLE(p_init->int_enable) | /* interrupt enable         */ \
 264                 SET_DMA_BEN(p_init->buffer_enable)     | /* buffer enable            */\
 265                 SET_DMA_ETD(p_init->etd_output)        | /* end of transfer pin      */ \
 266                 SET_DMA_TCE(p_init->tce_enable)        | /* terminal count enable    */ \
 267                 SET_DMA_PL(p_init->pl)                 | /* peripheral location      */ \
 268                 SET_DMA_DAI(p_init->dai)               | /* dest addr increment      */ \
 269                 SET_DMA_SAI(p_init->sai)               | /* src addr increment       */ \
 270                 SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */ \
 271                 SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
 272                 SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
 273                 SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
 274                 SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
 275                 SET_DMA_PREFETCH(p_init->pf)              /* read prefetch           */)
 276
 277 #define GET_DMA_POLARITY(chan) (DMAReq_ActiveLow(chan) | DMAAck_ActiveLow(chan) | EOT_ActiveLow(chan))
 278
 279 #elif defined(CONFIG_STBXXX_DMA)                /* stb03xxx */
 280
 281 #define DMA_PPC4xx_SIZE 4096
 282
 283 /*
 284  * DMA Status Register
 285  */
 286
 287 #define SET_DMA_PRIORITY(x)   (((x)&0x00800001))        /* DMA Channel Priority */
 288 #define DMA_PRIORITY_MASK       0x00800001
 289 #define   PRIORITY_LOW          0x00000000
 290 #define   PRIORITY_MID_LOW      0x00000001
 291 #define   PRIORITY_MID_HIGH     0x00800000
 292 #define   PRIORITY_HIGH         0x00800001
 293 #define GET_DMA_PRIORITY(x) (((((x)&DMA_PRIORITY_MASK) &0x00800000) >> 22 ) | (((x)&DMA_PRIORITY_MASK) &0x00000001))
 294
 295 #define DMA_CS0           (1<<31)       /* Terminal Count has been reached */
 296 #define DMA_CS1           (1<<30)
 297 #define DMA_CS2           (1<<29)
 298 #define DMA_CS3           (1<<28)
 299
 300 #define DMA_TS0           (1<<27)       /* End of Transfer has been requested */
 301 #define DMA_TS1           (1<<26)
 302 #define DMA_TS2           (1<<25)
 303 #define DMA_TS3           (1<<24)
 304
 305 #define DMA_CH0_ERR       (1<<23)       /* DMA Chanel 0 Error */
 306 #define DMA_CH1_ERR       (1<<22)
 307 #define DMA_CH2_ERR       (1<<21)
 308 #define DMA_CH3_ERR       (1<<20)
 309
 310 #define DMA_CT0           (1<<19)       /* Chained transfere */
 311
 312 #define DMA_IN_DMA_REQ0   (1<<18)       /* Internal DMA Request is pending */
 313 #define DMA_IN_DMA_REQ1   (1<<17)
 314 #define DMA_IN_DMA_REQ2   (1<<16)
 315 #define DMA_IN_DMA_REQ3   (1<<15)
 316
 317 #define DMA_EXT_DMA_REQ0  (1<<14)       /* External DMA Request is pending */
 318 #define DMA_EXT_DMA_REQ1  (1<<13)
 319 #define DMA_EXT_DMA_REQ2  (1<<12)
 320 #define DMA_EXT_DMA_REQ3  (1<<11)
 321
 322 #define DMA_CH0_BUSY      (1<<10)       /* DMA Channel 0 Busy */
 323 #define DMA_CH1_BUSY      (1<<9)
 324 #define DMA_CH2_BUSY       (1<<8)
 325 #define DMA_CH3_BUSY       (1<<7)
 326
 327 #define DMA_CT1            (1<<6)       /* Chained transfere */
 328 #define DMA_CT2            (1<<5)
 329 #define DMA_CT3            (1<<4)
 330
 331 #define DMA_CH_ENABLE (1<<7)
 332 #define SET_DMA_CH(x) (((x)&0x1)<<7)
 333 #define GET_DMA_CH(x) (((x)&DMA_CH_ENABLE)>>7)
 334
 335 /* STBx25xxx dma unique */
 336 /* enable device port on a dma channel
 337  * example ext 0 on dma 1
 338  */
 339
 340 #define SSP0_RECV       15
 341 #define SSP0_XMIT       14
 342 #define EXT_DMA_0       12
 343 #define SC1_XMIT        11
 344 #define SC1_RECV        10
 345 #define EXT_DMA_2       9
 346 #define EXT_DMA_3       8
 347 #define SERIAL2_XMIT    7
 348 #define SERIAL2_RECV    6
 349 #define SC0_XMIT        5
 350 #define SC0_RECV        4
 351 #define SERIAL1_XMIT    3
 352 #define SERIAL1_RECV    2
 353 #define SERIAL0_XMIT    1
 354 #define SERIAL0_RECV    0
 355
 356 #define DMA_CHAN_0      1
 357 #define DMA_CHAN_1      2
 358 #define DMA_CHAN_2      3
 359 #define DMA_CHAN_3      4
 360
 361 /* end STBx25xx */
 362
 363 /*
 364  * Bit 30 must be one for Redwoods, otherwise transfers may receive errors.
 365  */
 366 #define DMA_CR_MB0 0x2
 367
 368 #define SET_DMA_CONTROL \
 369                 (SET_DMA_CIE_ENABLE(p_init->int_enable) |  /* interrupt enable         */ \
 370                 SET_DMA_ETD(p_init->etd_output)        |  /* end of transfer pin      */ \
 371                 SET_DMA_TCE(p_init->tce_enable)        |  /* terminal count enable    */ \
 372                 SET_DMA_PL(p_init->pl)                 |  /* peripheral location      */ \
 373                 SET_DMA_DAI(p_init->dai)               |  /* dest addr increment      */ \
 374                 SET_DMA_SAI(p_init->sai)               |  /* src addr increment       */ \
 375                 SET_DMA_PRIORITY(p_init->cp)           |  /* channel priority        */  \
 376                 SET_DMA_PW(p_init->pwidth)             |  /* peripheral/bus width    */ \
 377                 SET_DMA_PSC(p_init->psc)               |  /* peripheral setup cycles */ \
 378                 SET_DMA_PWC(p_init->pwc)               |  /* peripheral wait cycles  */ \
 379                 SET_DMA_PHC(p_init->phc)               |  /* peripheral hold cycles  */ \
 380                 SET_DMA_TCD(p_init->tcd_disable)          |  /* TC chain mode disable   */ \
 381                 SET_DMA_ECE(p_init->ece_enable)   |  /* ECE chanin mode enable  */ \
 382                 SET_DMA_CH(p_init->ch_enable)   |    /* Chain enable            */ \
 383                 DMA_CR_MB0                              /* must be one */)
 384
 385 #define GET_DMA_POLARITY(chan) chan
 386
 387 #endif
 388
 389 typedef struct {
 390         unsigned short in_use;  /* set when channel is being used, clr when
 391                                  * available.
 392                                  */
 393         /*
 394          * Valid polarity settings:
 395          *   DMAReq_ActiveLow(n)
 396          *   DMAAck_ActiveLow(n)
 397          *   EOT_ActiveLow(n)
 398          *
 399          *   n is 0 to max dma chans
 400          */
 401         unsigned int polarity;
 402
 403         char buffer_enable;     /* Boolean: buffer enable            */
 404         char tce_enable;        /* Boolean: terminal count enable    */
 405         char etd_output;        /* Boolean: eot pin is a tc output   */
 406         char pce;               /* Boolean: parity check enable      */
 407
 408         /*
 409          * Peripheral location:
 410          * INTERNAL_PERIPHERAL (UART0 on the 405GP)
 411          * EXTERNAL_PERIPHERAL
 412          */
 413         char pl;                /* internal/external peripheral      */
 414
 415         /*
 416          * Valid pwidth settings:
 417          *   PW_8
 418          *   PW_16
 419          *   PW_32
 420          *   PW_64
 421          */
 422         unsigned int pwidth;
 423
 424         char dai;               /* Boolean: dst address increment   */
 425         char sai;               /* Boolean: src address increment   */
 426
 427         /*
 428          * Valid psc settings: 0-3
 429          */
 430         unsigned int psc;       /* Peripheral Setup Cycles         */
 431
 432         /*
 433          * Valid pwc settings:
 434          * 0-63
 435          */
 436         unsigned int pwc;       /* Peripheral Wait Cycles          */
 437
 438         /*
 439          * Valid phc settings:
 440          * 0-7
 441          */
 442         unsigned int phc;       /* Peripheral Hold Cycles          */
 443
 444         /*
 445          * Valid cp (channel priority) settings:
 446          *   PRIORITY_LOW
 447          *   PRIORITY_MID_LOW
 448          *   PRIORITY_MID_HIGH
 449          *   PRIORITY_HIGH
 450          */
 451         unsigned int cp;        /* channel priority                */
 452
 453         /*
 454          * Valid pf (memory read prefetch) settings:
 455          *
 456          *   PREFETCH_1
 457          *   PREFETCH_2
 458          *   PREFETCH_4
 459          */
 460         unsigned int pf;        /* memory read prefetch            */
 461
 462         /*
 463          * Boolean: channel interrupt enable
 464          * NOTE: for sgl transfers, only the last descriptor will be setup to
 465          * interrupt.
 466          */
 467         char int_enable;
 468
 469         char shift;             /* easy access to byte_count shift, based on */
 470         /* the width of the channel                  */
 471
 472         uint32_t control;       /* channel control word                      */
 473
 474         /* These variabled are used ONLY in single dma transfers              */
 475         unsigned int mode;      /* transfer mode                     */
 476         phys_addr_t addr;
 477         char ce;                /* channel enable */
 478 #ifdef CONFIG_STB03xxx
 479         char ch_enable;
 480         char tcd_disable;
 481         char ece_enable;
 482         char td;                /* transfer direction */
 483 #endif
 484
 485 } ppc_dma_ch_t;
 486
 487 /*
 488  * PPC44x DMA implementations have a slightly different
 489  * descriptor layout.  Probably moved about due to the
 490  * change to 64-bit addresses and link pointer. I don't
 491  * know why they didn't just leave control_count after
 492  * the dst_addr.
 493  */
 494 #ifdef PPC4xx_DMA_64BIT
 495 typedef struct {
 496         uint32_t control;
 497         uint32_t control_count;
 498         phys_addr_t src_addr;
 499         phys_addr_t dst_addr;
 500         phys_addr_t next;
 501 } ppc_sgl_t;
 502 #else
 503 typedef struct {
 504         uint32_t control;
 505         phys_addr_t src_addr;
 506         phys_addr_t dst_addr;
 507         uint32_t control_count;
 508         uint32_t next;
 509 } ppc_sgl_t;
 510 #endif
 511
 512 typedef struct {
 513         unsigned int dmanr;
 514         uint32_t control;       /* channel ctrl word; loaded from each descrptr */
 515         uint32_t sgl_control;   /* LK, TCI, ETI, and ERI bits in sgl descriptor */
 516         dma_addr_t dma_addr;    /* dma (physical) address of this list          */
 517         ppc_sgl_t *phead;
 518         dma_addr_t phead_dma;
 519         ppc_sgl_t *ptail;
 520         dma_addr_t ptail_dma;
 521 } sgl_list_info_t;
 522
 523 typedef struct {
 524         phys_addr_t *src_addr;
 525         phys_addr_t *dst_addr;
 526         phys_addr_t dma_src_addr;
 527         phys_addr_t dma_dst_addr;
 528 } pci_alloc_desc_t;
 529
 530 extern ppc_dma_ch_t dma_channels[];
 531
 532 /*
 533  * The DMA API are in ppc4xx_dma.c and ppc4xx_sgdma.c
 534  */
 535 extern int ppc4xx_init_dma_channel(unsigned int, ppc_dma_ch_t *);
 536 extern int ppc4xx_get_channel_config(unsigned int, ppc_dma_ch_t *);
 537 extern int ppc4xx_set_channel_priority(unsigned int, unsigned int);
 538 extern unsigned int ppc4xx_get_peripheral_width(unsigned int);
 539 extern void ppc4xx_set_sg_addr(int, phys_addr_t);
 540 extern int ppc4xx_add_dma_sgl(sgl_handle_t, phys_addr_t, phys_addr_t, unsigned int);
 541 extern void ppc4xx_enable_dma_sgl(sgl_handle_t);
 542 extern void ppc4xx_disable_dma_sgl(sgl_handle_t);
 543 extern int ppc4xx_get_dma_sgl_residue(sgl_handle_t, phys_addr_t *, phys_addr_t *);
 544 extern int ppc4xx_delete_dma_sgl_element(sgl_handle_t, phys_addr_t *, phys_addr_t *);
 545 extern int ppc4xx_alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int);
 546 extern void ppc4xx_free_dma_handle(sgl_handle_t);
 547 extern int ppc4xx_get_dma_status(void);
 548 extern void ppc4xx_set_src_addr(int dmanr, phys_addr_t src_addr);
 549 extern void ppc4xx_set_dst_addr(int dmanr, phys_addr_t dst_addr);
 550 extern void ppc4xx_enable_dma(unsigned int dmanr);
 551 extern void ppc4xx_disable_dma(unsigned int dmanr);
 552 extern void ppc4xx_set_dma_count(unsigned int dmanr, unsigned int count);
 553 extern int ppc4xx_get_dma_residue(unsigned int dmanr);
 554 extern void ppc4xx_set_dma_addr2(unsigned int dmanr, phys_addr_t src_dma_addr,
 555                                  phys_addr_t dst_dma_addr);
 556 extern int ppc4xx_enable_dma_interrupt(unsigned int dmanr);
 557 extern int ppc4xx_disable_dma_interrupt(unsigned int dmanr);
 558 extern int ppc4xx_clr_dma_status(unsigned int dmanr);
 559 extern int ppc4xx_map_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
 560 extern int ppc4xx_disable_dma_port(unsigned int dmanr, unsigned int ocp_dma,short dma_chan);
 561 extern int ppc4xx_set_dma_mode(unsigned int dmanr, unsigned int mode);
 562
 563 /* These are in kernel/dma.c: */
 564
 565 /* reserve a DMA channel */
 566 extern int request_dma(unsigned int dmanr, const char *device_id);
 567 /* release it again */
 568 extern void free_dma(unsigned int dmanr);
 569 #endif
 570 #endif                          /* __KERNEL__ */