include/asm-ppc/mpc52xx.h

   1 /*
   2  * include/asm-ppc/mpc52xx.h
   3  *
   4  * Prototypes, etc. for the Freescale MPC52xx embedded cpu chips
   5  * May need to be cleaned as the port goes on ...
   6  *
   7  *
   8  * Maintainer : Sylvain Munaut <tnt@246tNt.com>
   9  *
  10  * Originally written by Dale Farnsworth <dfarnsworth@mvista.com>
  11  * for the 2.4 kernel.
  12  *
  13  * Copyright (C) 2004 Sylvain Munaut <tnt@246tNt.com>
  14  * Copyright (C) 2003 MontaVista, Software, Inc.
  15  *
  16  * This file is licensed under the terms of the GNU General Public License
  17  * version 2. This program is licensed "as is" without any warranty of any
  18  * kind, whether express or implied.
  19  */
  20
  21 #ifndef __ASM_MPC52xx_H__
  22 #define __ASM_MPC52xx_H__
  23
  24 #ifndef __ASSEMBLY__
  25 #include <asm/ppcboot.h>
  26 #include <asm/types.h>
  27
  28 struct pt_regs;
  29 struct ocp_def;
  30 #endif /* __ASSEMBLY__ */
  31
  32
  33 /* ======================================================================== */
  34 /* Main registers/struct addresses                                          */
  35 /* ======================================================================== */
  36 /* Theses are PHYSICAL addresses !                                          */
  37 /* TODO : There should be no static mapping, but it's not yet the case, so  */
  38 /*        we require a 1:1 mapping                                          */
  39
  40 #define MPC52xx_MBAR            0xf0000000      /* Phys address */
  41 #define MPC52xx_MBAR_SIZE       0x00010000
  42 #define MPC52xx_MBAR_VIRT       0xf0000000      /* Virt address */
  43
  44 #define MPC52xx_MMAP_CTL        (MPC52xx_MBAR + 0x0000)
  45 #define MPC52xx_SDRAM           (MPC52xx_MBAR + 0x0100)
  46 #define MPC52xx_CDM             (MPC52xx_MBAR + 0x0200)
  47 #define MPC52xx_SFTRST          (MPC52xx_MBAR + 0x0220)
  48 #define MPC52xx_SFTRST_BIT      0x01000000
  49 #define MPC52xx_INTR            (MPC52xx_MBAR + 0x0500)
  50 #define MPC52xx_GPTx(x)         (MPC52xx_MBAR + 0x0600 + ((x)<<4))
  51 #define MPC52xx_RTC             (MPC52xx_MBAR + 0x0800)
  52 #define MPC52xx_MSCAN1          (MPC52xx_MBAR + 0x0900)
  53 #define MPC52xx_MSCAN2          (MPC52xx_MBAR + 0x0980)
  54 #define MPC52xx_GPIO            (MPC52xx_MBAR + 0x0b00)
  55 #define MPC52xx_GPIO_WKUP       (MPC52xx_MBAR + 0x0c00)
  56 #define MPC52xx_PCI             (MPC52xx_MBAR + 0x0d00)
  57 #define MPC52xx_USB_OHCI        (MPC52xx_MBAR + 0x1000)
  58 #define MPC52xx_SDMA            (MPC52xx_MBAR + 0x1200)
  59 #define MPC52xx_XLB             (MPC52xx_MBAR + 0x1f00)
  60 #define MPC52xx_PSCx(x)         (MPC52xx_MBAR + 0x2000 + ((x)<<9))
  61 #define MPC52xx_PSC1            (MPC52xx_MBAR + 0x2000)
  62 #define MPC52xx_PSC2            (MPC52xx_MBAR + 0x2200)
  63 #define MPC52xx_PSC3            (MPC52xx_MBAR + 0x2400)
  64 #define MPC52xx_PSC4            (MPC52xx_MBAR + 0x2600)
  65 #define MPC52xx_PSC5            (MPC52xx_MBAR + 0x2800)
  66 #define MPC52xx_PSC6            (MPC52xx_MBAR + 0x2C00)
  67 #define MPC52xx_FEC             (MPC52xx_MBAR + 0x3000)
  68 #define MPC52xx_ATA             (MPC52xx_MBAR + 0x3a00)
  69 #define MPC52xx_I2C1            (MPC52xx_MBAR + 0x3d00)
  70 #define MPC52xx_I2C_MICR        (MPC52xx_MBAR + 0x3d20)
  71 #define MPC52xx_I2C2            (MPC52xx_MBAR + 0x3d40)
  72
  73 /* SRAM used for SDMA */
  74 #define MPC52xx_SRAM            (MPC52xx_MBAR + 0x8000)
  75 #define MPC52xx_SRAM_SIZE       (16*1024)
  76
  77
  78 /* ======================================================================== */
  79 /* IRQ mapping                                                              */
  80 /* ======================================================================== */
  81 /* Be sure to look at mpc52xx_pic.h if you wish for whatever reason to change
  82  * this
  83  */
  84
  85 #define MPC52xx_CRIT_IRQ_NUM    4
  86 #define MPC52xx_MAIN_IRQ_NUM    17
  87 #define MPC52xx_SDMA_IRQ_NUM    17
  88 #define MPC52xx_PERP_IRQ_NUM    23
  89
  90 #define MPC52xx_CRIT_IRQ_BASE   0
  91 #define MPC52xx_MAIN_IRQ_BASE   (MPC52xx_CRIT_IRQ_BASE + MPC52xx_CRIT_IRQ_NUM)
  92 #define MPC52xx_SDMA_IRQ_BASE   (MPC52xx_MAIN_IRQ_BASE + MPC52xx_MAIN_IRQ_NUM)
  93 #define MPC52xx_PERP_IRQ_BASE   (MPC52xx_SDMA_IRQ_BASE + MPC52xx_SDMA_IRQ_NUM)
  94
  95 #define MPC52xx_IRQ0                    (MPC52xx_CRIT_IRQ_BASE + 0)
  96 #define MPC52xx_SLICE_TIMER_0_IRQ       (MPC52xx_CRIT_IRQ_BASE + 1)
  97 #define MPC52xx_HI_INT_IRQ              (MPC52xx_CRIT_IRQ_BASE + 2)
  98 #define MPC52xx_CCS_IRQ                 (MPC52xx_CRIT_IRQ_BASE + 3)
  99
 100 #define MPC52xx_IRQ1                    (MPC52xx_MAIN_IRQ_BASE + 1)
 101 #define MPC52xx_IRQ2                    (MPC52xx_MAIN_IRQ_BASE + 2)
 102 #define MPC52xx_IRQ3                    (MPC52xx_MAIN_IRQ_BASE + 3)
 103
 104 #define MPC52xx_SDMA_IRQ                (MPC52xx_PERP_IRQ_BASE + 0)
 105 #define MPC52xx_PSC1_IRQ                (MPC52xx_PERP_IRQ_BASE + 1)
 106 #define MPC52xx_PSC2_IRQ                (MPC52xx_PERP_IRQ_BASE + 2)
 107 #define MPC52xx_PSC3_IRQ                (MPC52xx_PERP_IRQ_BASE + 3)
 108 #define MPC52xx_PSC6_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
 109 #define MPC52xx_IRDA_IRQ                (MPC52xx_PERP_IRQ_BASE + 4)
 110 #define MPC52xx_FEC_IRQ                 (MPC52xx_PERP_IRQ_BASE + 5)
 111 #define MPC52xx_USB_IRQ                 (MPC52xx_PERP_IRQ_BASE + 6)
 112 #define MPC52xx_ATA_IRQ                 (MPC52xx_PERP_IRQ_BASE + 7)
 113 #define MPC52xx_PCI_CNTRL_IRQ           (MPC52xx_PERP_IRQ_BASE + 8)
 114 #define MPC52xx_PCI_SCIRX_IRQ           (MPC52xx_PERP_IRQ_BASE + 9)
 115 #define MPC52xx_PCI_SCITX_IRQ           (MPC52xx_PERP_IRQ_BASE + 10)
 116 #define MPC52xx_PSC4_IRQ                (MPC52xx_PERP_IRQ_BASE + 11)
 117 #define MPC52xx_PSC5_IRQ                (MPC52xx_PERP_IRQ_BASE + 12)
 118 #define MPC52xx_SPI_MODF_IRQ            (MPC52xx_PERP_IRQ_BASE + 13)
 119 #define MPC52xx_SPI_SPIF_IRQ            (MPC52xx_PERP_IRQ_BASE + 14)
 120 #define MPC52xx_I2C1_IRQ                (MPC52xx_PERP_IRQ_BASE + 15)
 121 #define MPC52xx_I2C2_IRQ                (MPC52xx_PERP_IRQ_BASE + 16)
 122 #define MPC52xx_CAN1_IRQ                (MPC52xx_PERP_IRQ_BASE + 17)
 123 #define MPC52xx_CAN2_IRQ                (MPC52xx_PERP_IRQ_BASE + 18)
 124 #define MPC52xx_IR_RX_IRQ               (MPC52xx_PERP_IRQ_BASE + 19)
 125 #define MPC52xx_IR_TX_IRQ               (MPC52xx_PERP_IRQ_BASE + 20)
 126 #define MPC52xx_XLB_ARB_IRQ             (MPC52xx_PERP_IRQ_BASE + 21)
 127
 128
 129
 130 /* ======================================================================== */
 131 /* Structures mapping of some unit register set                             */
 132 /* ======================================================================== */
 133
 134 #ifndef __ASSEMBLY__
 135
 136 /* Memory Mapping Control */
 137 struct mpc52xx_mmap_ctl {
 138         u32     mbar;           /* MMAP_CTRL + 0x00 */
 139
 140         u32     cs0_start;      /* MMAP_CTRL + 0x04 */
 141         u32     cs0_stop;       /* MMAP_CTRL + 0x08 */
 142         u32     cs1_start;      /* MMAP_CTRL + 0x0c */
 143         u32     cs1_stop;       /* MMAP_CTRL + 0x10 */
 144         u32     cs2_start;      /* MMAP_CTRL + 0x14 */
 145         u32     cs2_stop;       /* MMAP_CTRL + 0x18 */
 146         u32     cs3_start;      /* MMAP_CTRL + 0x1c */
 147         u32     cs3_stop;       /* MMAP_CTRL + 0x20 */
 148         u32     cs4_start;      /* MMAP_CTRL + 0x24 */
 149         u32     cs4_stop;       /* MMAP_CTRL + 0x28 */
 150         u32     cs5_start;      /* MMAP_CTRL + 0x2c */
 151         u32     cs5_stop;       /* MMAP_CTRL + 0x30 */
 152
 153         u32     sdram0;         /* MMAP_CTRL + 0x34 */
 154         u32     sdram1;         /* MMAP_CTRL + 0X38 */
 155
 156         u32     reserved[4];    /* MMAP_CTRL + 0x3c .. 0x48 */
 157
 158         u32     boot_start;     /* MMAP_CTRL + 0x4c */
 159         u32     boot_stop;      /* MMAP_CTRL + 0x50 */
 160
 161         u32     ipbi_ws_ctrl;   /* MMAP_CTRL + 0x54 */
 162
 163         u32     cs6_start;      /* MMAP_CTRL + 0x58 */
 164         u32     cs6_stop;       /* MMAP_CTRL + 0x5c */
 165         u32     cs7_start;      /* MMAP_CTRL + 0x60 */
 166         u32     cs7_stop;       /* MMAP_CTRL + 0x60 */
 167 };
 168
 169 /* SDRAM control */
 170 struct mpc52xx_sdram {
 171         u32     mode;           /* SDRAM + 0x00 */
 172         u32     ctrl;           /* SDRAM + 0x04 */
 173         u32     config1;        /* SDRAM + 0x08 */
 174         u32     config2;        /* SDRAM + 0x0c */
 175 };
 176
 177 /* Interrupt controller */
 178 struct mpc52xx_intr {
 179         u32     per_mask;       /* INTR + 0x00 */
 180         u32     per_pri1;       /* INTR + 0x04 */
 181         u32     per_pri2;       /* INTR + 0x08 */
 182         u32     per_pri3;       /* INTR + 0x0c */
 183         u32     ctrl;           /* INTR + 0x10 */
 184         u32     main_mask;      /* INTR + 0x14 */
 185         u32     main_pri1;      /* INTR + 0x18 */
 186         u32     main_pri2;      /* INTR + 0x1c */
 187         u32     reserved1;      /* INTR + 0x20 */
 188         u32     enc_status;     /* INTR + 0x24 */
 189         u32     crit_status;    /* INTR + 0x28 */
 190         u32     main_status;    /* INTR + 0x2c */
 191         u32     per_status;     /* INTR + 0x30 */
 192         u32     reserved2;      /* INTR + 0x34 */
 193         u32     per_error;      /* INTR + 0x38 */
 194 };
 195
 196 /* SDMA */
 197 struct mpc52xx_sdma {
 198         u32     taskBar;        /* SDMA + 0x00 */
 199         u32     currentPointer; /* SDMA + 0x04 */
 200         u32     endPointer;     /* SDMA + 0x08 */
 201         u32     variablePointer;/* SDMA + 0x0c */
 202
 203         u8      IntVect1;       /* SDMA + 0x10 */
 204         u8      IntVect2;       /* SDMA + 0x11 */
 205         u16     PtdCntrl;       /* SDMA + 0x12 */
 206
 207         u32     IntPend;        /* SDMA + 0x14 */
 208         u32     IntMask;        /* SDMA + 0x18 */
 209
 210         u16     tcr[16];        /* SDMA + 0x1c .. 0x3a */
 211
 212         u8      ipr[32];        /* SDMA + 0x3c .. 5b */
 213
 214         u32     cReqSelect;     /* SDMA + 0x5c */
 215         u32     task_size0;     /* SDMA + 0x60 */
 216         u32     task_size1;     /* SDMA + 0x64 */
 217         u32     MDEDebug;       /* SDMA + 0x68 */
 218         u32     ADSDebug;       /* SDMA + 0x6c */
 219         u32     Value1;         /* SDMA + 0x70 */
 220         u32     Value2;         /* SDMA + 0x74 */
 221         u32     Control;        /* SDMA + 0x78 */
 222         u32     Status;         /* SDMA + 0x7c */
 223         u32     PTDDebug;       /* SDMA + 0x80 */
 224 };
 225
 226 /* GPT */
 227 struct mpc52xx_gpt {
 228         u32     mode;           /* GPTx + 0x00 */
 229         u32     count;          /* GPTx + 0x04 */
 230         u32     pwm;            /* GPTx + 0x08 */
 231         u32     status;         /* GPTx + 0X0c */
 232 };
 233
 234 /* RTC */
 235 struct mpc52xx_rtc {
 236         u32     time_set;       /* RTC + 0x00 */
 237         u32     date_set;       /* RTC + 0x04 */
 238         u32     stopwatch;      /* RTC + 0x08 */
 239         u32     int_enable;     /* RTC + 0x0c */
 240         u32     time;           /* RTC + 0x10 */
 241         u32     date;           /* RTC + 0x14 */
 242         u32     stopwatch_intr; /* RTC + 0x18 */
 243         u32     bus_error;      /* RTC + 0x1c */
 244         u32     dividers;       /* RTC + 0x20 */
 245 };
 246
 247 /* GPIO */
 248 struct mpc52xx_gpio {
 249         u32     port_config;    /* GPIO + 0x00 */
 250         u32     simple_gpioe;   /* GPIO + 0x04 */
 251         u32     simple_ode;     /* GPIO + 0x08 */
 252         u32     simple_ddr;     /* GPIO + 0x0c */
 253         u32     simple_dvo;     /* GPIO + 0x10 */
 254         u32     simple_ival;    /* GPIO + 0x14 */
 255         u8      outo_gpioe;     /* GPIO + 0x18 */
 256         u8      reserved1[3];   /* GPIO + 0x19 */
 257         u8      outo_dvo;       /* GPIO + 0x1c */
 258         u8      reserved2[3];   /* GPIO + 0x1d */
 259         u8      sint_gpioe;     /* GPIO + 0x20 */
 260         u8      reserved3[3];   /* GPIO + 0x21 */
 261         u8      sint_ode;       /* GPIO + 0x24 */
 262         u8      reserved4[3];   /* GPIO + 0x25 */
 263         u8      sint_ddr;       /* GPIO + 0x28 */
 264         u8      reserved5[3];   /* GPIO + 0x29 */
 265         u8      sint_dvo;       /* GPIO + 0x2c */
 266         u8      reserved6[3];   /* GPIO + 0x2d */
 267         u8      sint_inten;     /* GPIO + 0x30 */
 268         u8      reserved7[3];   /* GPIO + 0x31 */
 269         u16     sint_itype;     /* GPIO + 0x34 */
 270         u16     reserved8;      /* GPIO + 0x36 */
 271         u8      gpio_control;   /* GPIO + 0x38 */
 272         u8      reserved9[3];   /* GPIO + 0x39 */
 273         u8      sint_istat;     /* GPIO + 0x3c */
 274         u8      sint_ival;      /* GPIO + 0x3d */
 275         u8      bus_errs;       /* GPIO + 0x3e */
 276         u8      reserved10;     /* GPIO + 0x3f */
 277 };
 278
 279 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITHOUT_CD 4
 280 #define MPC52xx_GPIO_PSC_CONFIG_UART_WITH_CD    5
 281 #define MPC52xx_GPIO_PCI_DIS                    (1<<15)
 282
 283 /* GPIO with WakeUp*/
 284 struct mpc52xx_gpio_wkup {
 285         u8      wkup_gpioe;     /* GPIO_WKUP + 0x00 */
 286         u8      reserved1[3];   /* GPIO_WKUP + 0x03 */
 287         u8      wkup_ode;       /* GPIO_WKUP + 0x04 */
 288         u8      reserved2[3];   /* GPIO_WKUP + 0x05 */
 289         u8      wkup_ddr;       /* GPIO_WKUP + 0x08 */
 290         u8      reserved3[3];   /* GPIO_WKUP + 0x09 */
 291         u8      wkup_dvo;       /* GPIO_WKUP + 0x0C */
 292         u8      reserved4[3];   /* GPIO_WKUP + 0x0D */
 293         u8      wkup_inten;     /* GPIO_WKUP + 0x10 */
 294         u8      reserved5[3];   /* GPIO_WKUP + 0x11 */
 295         u8      wkup_iinten;    /* GPIO_WKUP + 0x14 */
 296         u8      reserved6[3];   /* GPIO_WKUP + 0x15 */
 297         u16     wkup_itype;     /* GPIO_WKUP + 0x18 */
 298         u8      reserved7[2];   /* GPIO_WKUP + 0x1A */
 299         u8      wkup_maste;     /* GPIO_WKUP + 0x1C */
 300         u8      reserved8[3];   /* GPIO_WKUP + 0x1D */
 301         u8      wkup_ival;      /* GPIO_WKUP + 0x20 */
 302         u8      reserved9[3];   /* GPIO_WKUP + 0x21 */
 303         u8      wkup_istat;     /* GPIO_WKUP + 0x24 */
 304         u8      reserved10[3];  /* GPIO_WKUP + 0x25 */
 305 };
 306
 307 /* XLB Bus control */
 308 struct mpc52xx_xlb {
 309         u8      reserved[0x40];
 310         u32     config;                 /* XLB + 0x40 */
 311         u32     version;                /* XLB + 0x44 */
 312         u32     status;                 /* XLB + 0x48 */
 313         u32     int_enable;             /* XLB + 0x4c */
 314         u32     addr_capture;           /* XLB + 0x50 */
 315         u32     bus_sig_capture;        /* XLB + 0x54 */
 316         u32     addr_timeout;           /* XLB + 0x58 */
 317         u32     data_timeout;           /* XLB + 0x5c */
 318         u32     bus_act_timeout;        /* XLB + 0x60 */
 319         u32     master_pri_enable;      /* XLB + 0x64 */
 320         u32     master_priority;        /* XLB + 0x68 */
 321         u32     base_address;           /* XLB + 0x6c */
 322         u32     snoop_window;           /* XLB + 0x70 */
 323 };
 324
 325 #define MPC52xx_XLB_CFG_SNOOP           (1 << 15)
 326
 327 /* Clock Distribution control */
 328 struct mpc52xx_cdm {
 329         u32     jtag_id;                /* CDM + 0x00  reg0 read only */
 330         u32     rstcfg;                 /* CDM + 0x04  reg1 read only */
 331         u32     breadcrumb;             /* CDM + 0x08  reg2 */
 332
 333         u8      mem_clk_sel;            /* CDM + 0x0c  reg3 byte0 */
 334         u8      xlb_clk_sel;            /* CDM + 0x0d  reg3 byte1 read only */
 335         u8      ipb_clk_sel;            /* CDM + 0x0e  reg3 byte2 */
 336         u8      pci_clk_sel;            /* CDM + 0x0f  reg3 byte3 */
 337
 338         u8      ext_48mhz_en;           /* CDM + 0x10  reg4 byte0 */
 339         u8      fd_enable;              /* CDM + 0x11  reg4 byte1 */
 340         u16     fd_counters;            /* CDM + 0x12  reg4 byte2,3 */
 341
 342         u32     clk_enables;            /* CDM + 0x14  reg5 */
 343
 344         u8      osc_disable;            /* CDM + 0x18  reg6 byte0 */
 345         u8      reserved0[3];           /* CDM + 0x19  reg6 byte1,2,3 */
 346
 347         u8      ccs_sleep_enable;       /* CDM + 0x1c  reg7 byte0 */
 348         u8      osc_sleep_enable;       /* CDM + 0x1d  reg7 byte1 */
 349         u8      reserved1;              /* CDM + 0x1e  reg7 byte2 */
 350         u8      ccs_qreq_test;          /* CDM + 0x1f  reg7 byte3 */
 351
 352         u8      soft_reset;             /* CDM + 0x20  u8 byte0 */
 353         u8      no_ckstp;               /* CDM + 0x21  u8 byte0 */
 354         u8      reserved2[2];           /* CDM + 0x22  u8 byte1,2,3 */
 355
 356         u8      pll_lock;               /* CDM + 0x24  reg9 byte0 */
 357         u8      pll_looselock;          /* CDM + 0x25  reg9 byte1 */
 358         u8      pll_sm_lockwin;         /* CDM + 0x26  reg9 byte2 */
 359         u8      reserved3;              /* CDM + 0x27  reg9 byte3 */
 360
 361         u16     reserved4;              /* CDM + 0x28  reg10 byte0,1 */
 362         u16     mclken_div_psc1;        /* CDM + 0x2a  reg10 byte2,3 */
 363
 364         u16     reserved5;              /* CDM + 0x2c  reg11 byte0,1 */
 365         u16     mclken_div_psc2;        /* CDM + 0x2e  reg11 byte2,3 */
 366
 367         u16     reserved6;              /* CDM + 0x30  reg12 byte0,1 */
 368         u16     mclken_div_psc3;        /* CDM + 0x32  reg12 byte2,3 */
 369
 370         u16     reserved7;              /* CDM + 0x34  reg13 byte0,1 */
 371         u16     mclken_div_psc6;        /* CDM + 0x36  reg13 byte2,3 */
 372 };
 373
 374 #endif /* __ASSEMBLY__ */
 375
 376
 377 /* ========================================================================= */
 378 /* Prototypes for MPC52xx syslib                                             */
 379 /* ========================================================================= */
 380
 381 #ifndef __ASSEMBLY__
 382
 383 extern void mpc52xx_init_irq(void);
 384 extern int mpc52xx_get_irq(struct pt_regs *regs);
 385
 386 extern unsigned long mpc52xx_find_end_of_memory(void);
 387 extern void mpc52xx_set_bat(void);
 388 extern void mpc52xx_map_io(void);
 389 extern void mpc52xx_restart(char *cmd);
 390 extern void mpc52xx_halt(void);
 391 extern void mpc52xx_power_off(void);
 392 extern void mpc52xx_progress(char *s, unsigned short hex);
 393 extern void mpc52xx_calibrate_decr(void);
 394 extern void mpc52xx_add_board_devices(struct ocp_def board_ocp[]);
 395
 396 #endif /* __ASSEMBLY__ */
 397
 398
 399 /* ========================================================================= */
 400 /* Platform configuration                                                    */
 401 /* ========================================================================= */
 402
 403 /* The U-Boot platform information struct */
 404 extern bd_t __res;
 405
 406 /* Platform options */
 407 #if defined(CONFIG_LITE5200)
 408 #include <platforms/lite5200.h>
 409 #endif
 410
 411
 412 #endif /* __ASM_MPC52xx_H__ */