include/asm-ia64/sn/pda.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_PDA_H
   9 #define _ASM_IA64_SN_PDA_H
  10
  11 #include <linux/cache.h>
  12 #include <asm/percpu.h>
  13 #include <asm/system.h>
  14 #include <asm/sn/bte.h>
  15
  16
  17 /*
  18  * CPU-specific data structure.
  19  *
  20  * One of these structures is allocated for each cpu of a NUMA system.
  21  *
  22  * This structure provides a convenient way of keeping together
  23  * all SN per-cpu data structures.
  24  */
  25
  26 typedef struct pda_s {
  27
  28         /* Having a pointer in the begining of PDA tends to increase
  29          * the chance of having this pointer in cache. (Yes something
  30          * else gets pushed out). Doing this reduces the number of memory
  31          * access to all nodepda variables to be one
  32          */
  33         struct nodepda_s *p_nodepda;            /* Pointer to Per node PDA */
  34         struct subnodepda_s *p_subnodepda;      /* Pointer to CPU  subnode PDA */
  35
  36         /*
  37          * Support for SN LEDs
  38          */
  39         volatile short  *led_address;
  40         u8              led_state;
  41         u8              hb_state;       /* supports blinking heartbeat leds */
  42         u8              shub_1_1_found;
  43         unsigned int    hb_count;
  44
  45         unsigned int    idle_flag;
  46
  47         volatile unsigned long *bedrock_rev_id;
  48         volatile unsigned long *pio_write_status_addr;
  49         volatile unsigned long *pio_shub_war_cam_addr;
  50         volatile unsigned long *mem_write_status_addr;
  51
  52         unsigned long   sn_soft_irr[4];
  53         unsigned long   sn_in_service_ivecs[4];
  54         short           cnodeid_to_nasid_table[MAX_NUMNODES];
  55         int             sn_lb_int_war_ticks;
  56         int             sn_last_irq;
  57         int             sn_first_irq;
  58         int             sn_num_irqs;                    /* number of irqs targeted for this cpu */
  59 } pda_t;
  60
  61
  62 #define CACHE_ALIGN(x)  (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
  63
  64 /*
  65  * PDA
  66  * Per-cpu private data area for each cpu. The PDA is located immediately after
  67  * the IA64 cpu_data area. A full page is allocated for the cp_data area for each
  68  * cpu but only a small amout of the page is actually used. We put the SNIA PDA
  69  * in the same page as the cpu_data area. Note that there is a check in the setup
  70  * code to verify that we don't overflow the page.
  71  *
  72  * Seems like we should should cache-line align the pda so that any changes in the
  73  * size of the cpu_data area don't change cache layout. Should we align to 32, 64, 128
  74  * or 512 boundary. Each has merits. For now, pick 128 but should be revisited later.
  75  */
  76 DECLARE_PER_CPU(struct pda_s, pda_percpu);
  77
  78 #define pda             (&__get_cpu_var(pda_percpu))
  79
  80 #define pdacpu(cpu)     (&per_cpu(pda_percpu, cpu))
  81
  82 /*
  83  * Use this macro to test if shub 1.1 wars should be enabled
  84  */
  85 #define enable_shub_wars_1_1()  (pda->shub_1_1_found)
  86
  87 #endif /* _ASM_IA64_SN_PDA_H */