include/asm-ia64/sn/pci/pic.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_PCI_PIC_H
   9 #define _ASM_IA64_SN_PCI_PIC_H
  10
  11 /*
  12  * PIC AS DEVICE ZERO
  13  * ------------------
  14  *
  15  * PIC handles PCI/X busses.  PCI/X requires that the 'bridge' (i.e. PIC)
  16  * be designated as 'device 0'.   That is a departure from earlier SGI
  17  * PCI bridges.  Because of that we use config space 1 to access the
  18  * config space of the first actual PCI device on the bus.
  19  * Here's what the PIC manual says:
  20  *
  21  *     The current PCI-X bus specification now defines that the parent
  22  *     hosts bus bridge (PIC for example) must be device 0 on bus 0. PIC
  23  *     reduced the total number of devices from 8 to 4 and removed the
  24  *     device registers and windows, now only supporting devices 0,1,2, and
  25  *     3. PIC did leave all 8 configuration space windows. The reason was
  26  *     there was nothing to gain by removing them. Here in lies the problem.
  27  *     The device numbering we do using 0 through 3 is unrelated to the device
  28  *     numbering which PCI-X requires in configuration space. In the past we
  29  *     correlated Configs pace and our device space 0 <-> 0, 1 <-> 1, etc.
  30  *     PCI-X requires we start a 1, not 0 and currently the PX brick
  31  *     does associate our:
  32  *
  33  *         device 0 with configuration space window 1,
  34  *         device 1 with configuration space window 2,
  35  *         device 2 with configuration space window 3,
  36  *         device 3 with configuration space window 4.
  37  *
  38  * The net effect is that all config space access are off-by-one with
  39  * relation to other per-slot accesses on the PIC.
  40  * Here is a table that shows some of that:
  41  *
  42  *                               Internal Slot#
  43  *           |
  44  *           |     0         1        2         3
  45  * ----------|---------------------------------------
  46  * config    |  0x21000   0x22000  0x23000   0x24000
  47  *           |
  48  * even rrb  |  0[0]      n/a      1[0]      n/a        [] == implied even/odd
  49  *           |
  50  * odd rrb   |  n/a       0[1]     n/a       1[1]
  51  *           |
  52  * int dev   |  00       01        10        11
  53  *           |
  54  * ext slot# |  1        2         3         4
  55  * ----------|---------------------------------------
  56  */
  57
  58
  59 #ifdef __KERNEL__
  60 #include <linux/types.h>
  61 #include <asm/sn/xtalk/xwidget.h>       /* generic widget header */
  62 #else
  63 #include <xtalk/xwidget.h>
  64 #endif
  65
  66 #include <asm/sn/pci/pciio.h>
  67
  68
  69 /*
  70  *    bus provider function table
  71  *
  72  *      Normally, this table is only handed off explicitly
  73  *      during provider initialization, and the PCI generic
  74  *      layer will stash a pointer to it in the vertex; however,
  75  *      exporting it explicitly enables a performance hack in
  76  *      the generic PCI provider where if we know at compile
  77  *      time that the only possible PCI provider is a
  78  *      pcibr, we can go directly to this ops table.
  79  */
  80
  81 extern pciio_provider_t pci_pic_provider;
  82
  83
  84 /*
  85  * misc defines
  86  *
  87  */
  88
  89 #define PIC_WIDGET_PART_NUM_BUS0 0xd102
  90 #define PIC_WIDGET_PART_NUM_BUS1 0xd112
  91 #define PIC_WIDGET_MFGR_NUM 0x24
  92 #define PIC_WIDGET_REV_A  0x1
  93 #define PIC_WIDGET_REV_B  0x2
  94 #define PIC_WIDGET_REV_C  0x3
  95
  96 #define PIC_XTALK_ADDR_MASK                     0x0000FFFFFFFFFFFF
  97 #define PIC_INTERNAL_ATES                       1024
  98
  99
 100 #define IS_PIC_PART_REV_A(rev) \
 101         ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_A)) || \
 102         (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_A)))
 103 #define IS_PIC_PART_REV_B(rev) \
 104         ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_B)) || \
 105         (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_B)))
 106 #define IS_PIC_PART_REV_C(rev) \
 107         ((rev == (PIC_WIDGET_PART_NUM_BUS0 << 4 | PIC_WIDGET_REV_C)) || \
 108         (rev == (PIC_WIDGET_PART_NUM_BUS1 << 4 | PIC_WIDGET_REV_C)))
 109
 110
 111 /*
 112  * misc typedefs
 113  *
 114  */
 115 typedef uint64_t picreg_t;
 116 typedef uint64_t picate_t;
 117
 118 /*
 119  * PIC Bridge MMR defines
 120  */
 121
 122 /*
 123  * PIC STATUS register          offset 0x00000008
 124  */
 125
 126 #define PIC_STAT_PCIX_ACTIVE_SHFT       33
 127
 128 /*
 129  * PIC CONTROL register         offset 0x00000020
 130  */
 131
 132 #define PIC_CTRL_PCI_SPEED_SHFT         4
 133 #define PIC_CTRL_PCI_SPEED              (0x3 << PIC_CTRL_PCI_SPEED_SHFT)
 134 #define PIC_CTRL_PAGE_SIZE_SHFT         21
 135 #define PIC_CTRL_PAGE_SIZE              (0x1 << PIC_CTRL_PAGE_SIZE_SHFT)
 136
 137
 138 /*
 139  * PIC Intr Destination Addr    offset 0x00000038
 140  */
 141
 142 #define PIC_INTR_DEST_ADDR              0x0000FFFFFFFFFFFF
 143 #define PIC_INTR_DEST_TID_SHFT          48
 144 #define PIC_INTR_DEST_TID               (0xFull << PIC_INTR_DEST_TID_SHFT)
 145
 146 /*
 147  * PIC PCI Responce Buffer      offset 0x00000068
 148  */
 149 #define PIC_RSP_BUF_ADDR                0x0000FFFFFFFFFFFF
 150 #define PIC_RSP_BUF_NUM_SHFT            48
 151 #define PIC_RSP_BUF_NUM                 (0xFull << PIC_RSP_BUF_NUM_SHFT)
 152 #define PIC_RSP_BUF_DEV_NUM_SHFT        52
 153 #define PIC_RSP_BUF_DEV_NUM             (0x3ull << PIC_RSP_BUF_DEV_NUM_SHFT)
 154
 155 /*
 156  * PIC PCI DIRECT MAP register  offset 0x00000080
 157  */
 158 #define PIC_DIRMAP_DIROFF_SHFT          0
 159 #define PIC_DIRMAP_DIROFF               (0x1FFFF << PIC_DIRMAP_DIROFF_SHFT)
 160 #define PIC_DIRMAP_ADD512_SHFT          17
 161 #define PIC_DIRMAP_ADD512               (0x1 << PIC_DIRMAP_ADD512_SHFT)
 162 #define PIC_DIRMAP_WID_SHFT             20
 163 #define PIC_DIRMAP_WID                  (0xF << PIC_DIRMAP_WID_SHFT)
 164
 165 #define PIC_DIRMAP_OFF_ADDRSHFT         31
 166
 167 /*
 168  * Interrupt Status register            offset 0x00000100
 169  */
 170 #define PIC_ISR_PCIX_SPLIT_MSG_PE     (0x1ull << 45)
 171 #define PIC_ISR_PCIX_SPLIT_EMSG       (0x1ull << 44)
 172 #define PIC_ISR_PCIX_SPLIT_TO         (0x1ull << 43)
 173 #define PIC_ISR_PCIX_UNEX_COMP        (0x1ull << 42)
 174 #define PIC_ISR_INT_RAM_PERR          (0x1ull << 41)
 175 #define PIC_ISR_PCIX_ARB_ERR          (0x1ull << 40)
 176 #define PIC_ISR_PCIX_REQ_TOUT         (0x1ull << 39)
 177 #define PIC_ISR_PCIX_TABORT           (0x1ull << 38)
 178 #define PIC_ISR_PCIX_PERR             (0x1ull << 37)
 179 #define PIC_ISR_PCIX_SERR             (0x1ull << 36)
 180 #define PIC_ISR_PCIX_MRETRY           (0x1ull << 35)
 181 #define PIC_ISR_PCIX_MTOUT            (0x1ull << 34)
 182 #define PIC_ISR_PCIX_DA_PARITY        (0x1ull << 33)
 183 #define PIC_ISR_PCIX_AD_PARITY        (0x1ull << 32)
 184 #define PIC_ISR_PMU_PAGE_FAULT        (0x1ull << 30)
 185 #define PIC_ISR_UNEXP_RESP            (0x1ull << 29)
 186 #define PIC_ISR_BAD_XRESP_PKT         (0x1ull << 28)
 187 #define PIC_ISR_BAD_XREQ_PKT          (0x1ull << 27)
 188 #define PIC_ISR_RESP_XTLK_ERR         (0x1ull << 26)
 189 #define PIC_ISR_REQ_XTLK_ERR          (0x1ull << 25)
 190 #define PIC_ISR_INVLD_ADDR            (0x1ull << 24)
 191 #define PIC_ISR_UNSUPPORTED_XOP       (0x1ull << 23)
 192 #define PIC_ISR_XREQ_FIFO_OFLOW       (0x1ull << 22)
 193 #define PIC_ISR_LLP_REC_SNERR         (0x1ull << 21)
 194 #define PIC_ISR_LLP_REC_CBERR         (0x1ull << 20)
 195 #define PIC_ISR_LLP_RCTY              (0x1ull << 19)
 196 #define PIC_ISR_LLP_TX_RETRY          (0x1ull << 18)
 197 #define PIC_ISR_LLP_TCTY              (0x1ull << 17)
 198 #define PIC_ISR_PCI_ABORT             (0x1ull << 15)
 199 #define PIC_ISR_PCI_PARITY            (0x1ull << 14)
 200 #define PIC_ISR_PCI_SERR              (0x1ull << 13)
 201 #define PIC_ISR_PCI_PERR              (0x1ull << 12)
 202 #define PIC_ISR_PCI_MST_TIMEOUT       (0x1ull << 11)
 203 #define PIC_ISR_PCI_RETRY_CNT         (0x1ull << 10)
 204 #define PIC_ISR_XREAD_REQ_TIMEOUT     (0x1ull << 9)
 205 #define PIC_ISR_INT_MSK               (0xffull << 0)
 206 #define PIC_ISR_INT(x)                (0x1ull << (x))
 207
 208 #define PIC_ISR_LINK_ERROR            \
 209                 (PIC_ISR_LLP_REC_SNERR|PIC_ISR_LLP_REC_CBERR|       \
 210                  PIC_ISR_LLP_RCTY|PIC_ISR_LLP_TX_RETRY|             \
 211                  PIC_ISR_LLP_TCTY)
 212
 213 #define PIC_ISR_PCIBUS_PIOERR         \
 214                 (PIC_ISR_PCI_MST_TIMEOUT|PIC_ISR_PCI_ABORT|         \
 215                  PIC_ISR_PCIX_MTOUT|PIC_ISR_PCIX_TABORT)
 216
 217 #define PIC_ISR_PCIBUS_ERROR          \
 218                 (PIC_ISR_PCIBUS_PIOERR|PIC_ISR_PCI_PERR|            \
 219                  PIC_ISR_PCI_SERR|PIC_ISR_PCI_RETRY_CNT|            \
 220                  PIC_ISR_PCI_PARITY|PIC_ISR_PCIX_PERR|              \
 221                  PIC_ISR_PCIX_SERR|PIC_ISR_PCIX_MRETRY|             \
 222                  PIC_ISR_PCIX_AD_PARITY|PIC_ISR_PCIX_DA_PARITY|     \
 223                  PIC_ISR_PCIX_REQ_TOUT|PIC_ISR_PCIX_UNEX_COMP|      \
 224                  PIC_ISR_PCIX_SPLIT_TO|PIC_ISR_PCIX_SPLIT_EMSG|     \
 225                  PIC_ISR_PCIX_SPLIT_MSG_PE)
 226
 227 #define PIC_ISR_XTALK_ERROR           \
 228                 (PIC_ISR_XREAD_REQ_TIMEOUT|PIC_ISR_XREQ_FIFO_OFLOW| \
 229                  PIC_ISR_UNSUPPORTED_XOP|PIC_ISR_INVLD_ADDR|        \
 230                  PIC_ISR_REQ_XTLK_ERR|PIC_ISR_RESP_XTLK_ERR|        \
 231                  PIC_ISR_BAD_XREQ_PKT|PIC_ISR_BAD_XRESP_PKT|        \
 232                  PIC_ISR_UNEXP_RESP)
 233
 234 #define PIC_ISR_ERRORS                \
 235                 (PIC_ISR_LINK_ERROR|PIC_ISR_PCIBUS_ERROR|           \
 236                  PIC_ISR_XTALK_ERROR|                                 \
 237                  PIC_ISR_PMU_PAGE_FAULT|PIC_ISR_INT_RAM_PERR)
 238
 239 /*
 240  * PIC RESET INTR register      offset 0x00000110
 241  */
 242
 243 #define PIC_IRR_ALL_CLR                 0xffffffffffffffff
 244
 245 /*
 246  * PIC PCI Host Intr Addr       offset 0x00000130 - 0x00000168
 247  */
 248 #define PIC_HOST_INTR_ADDR              0x0000FFFFFFFFFFFF
 249 #define PIC_HOST_INTR_FLD_SHFT          48
 250 #define PIC_HOST_INTR_FLD               (0xFFull << PIC_HOST_INTR_FLD_SHFT)
 251
 252
 253 /*
 254  * PIC MMR structure mapping
 255  */
 256
 257 /* NOTE: PIC WAR. PV#854697.  PIC does not allow writes just to [31:0]
 258  * of a 64-bit register.  When writing PIC registers, always write the
 259  * entire 64 bits.
 260  */
 261
 262 typedef volatile struct pic_s {
 263
 264     /* 0x000000-0x00FFFF -- Local Registers */
 265
 266     /* 0x000000-0x000057 -- Standard Widget Configuration */
 267     picreg_t            p_wid_id;                       /* 0x000000 */
 268     picreg_t            p_wid_stat;                     /* 0x000008 */
 269     picreg_t            p_wid_err_upper;                /* 0x000010 */
 270     picreg_t            p_wid_err_lower;                /* 0x000018 */
 271     #define p_wid_err p_wid_err_lower
 272     picreg_t            p_wid_control;                  /* 0x000020 */
 273     picreg_t            p_wid_req_timeout;              /* 0x000028 */
 274     picreg_t            p_wid_int_upper;                /* 0x000030 */
 275     picreg_t            p_wid_int_lower;                /* 0x000038 */
 276     #define p_wid_int p_wid_int_lower
 277     picreg_t            p_wid_err_cmdword;              /* 0x000040 */
 278     picreg_t            p_wid_llp;                      /* 0x000048 */
 279     picreg_t            p_wid_tflush;                   /* 0x000050 */
 280
 281     /* 0x000058-0x00007F -- Bridge-specific Widget Configuration */
 282     picreg_t            p_wid_aux_err;                  /* 0x000058 */
 283     picreg_t            p_wid_resp_upper;               /* 0x000060 */
 284     picreg_t            p_wid_resp_lower;               /* 0x000068 */
 285     #define p_wid_resp p_wid_resp_lower
 286     picreg_t            p_wid_tst_pin_ctrl;             /* 0x000070 */
 287     picreg_t            p_wid_addr_lkerr;               /* 0x000078 */
 288
 289     /* 0x000080-0x00008F -- PMU & MAP */
 290     picreg_t            p_dir_map;                      /* 0x000080 */
 291     picreg_t            _pad_000088;                    /* 0x000088 */
 292
 293     /* 0x000090-0x00009F -- SSRAM */
 294     picreg_t            p_map_fault;                    /* 0x000090 */
 295     picreg_t            _pad_000098;                    /* 0x000098 */
 296
 297     /* 0x0000A0-0x0000AF -- Arbitration */
 298     picreg_t            p_arb;                          /* 0x0000A0 */
 299     picreg_t            _pad_0000A8;                    /* 0x0000A8 */
 300
 301     /* 0x0000B0-0x0000BF -- Number In A Can or ATE Parity Error */
 302     picreg_t            p_ate_parity_err;               /* 0x0000B0 */
 303     picreg_t            _pad_0000B8;                    /* 0x0000B8 */
 304
 305     /* 0x0000C0-0x0000FF -- PCI/GIO */
 306     picreg_t            p_bus_timeout;                  /* 0x0000C0 */
 307     picreg_t            p_pci_cfg;                      /* 0x0000C8 */
 308     picreg_t            p_pci_err_upper;                /* 0x0000D0 */
 309     picreg_t            p_pci_err_lower;                /* 0x0000D8 */
 310     #define p_pci_err p_pci_err_lower
 311     picreg_t            _pad_0000E0[4];                 /* 0x0000{E0..F8} */
 312
 313     /* 0x000100-0x0001FF -- Interrupt */
 314     picreg_t            p_int_status;                   /* 0x000100 */
 315     picreg_t            p_int_enable;                   /* 0x000108 */
 316     picreg_t            p_int_rst_stat;                 /* 0x000110 */
 317     picreg_t            p_int_mode;                     /* 0x000118 */
 318     picreg_t            p_int_device;                   /* 0x000120 */
 319     picreg_t            p_int_host_err;                 /* 0x000128 */
 320     picreg_t            p_int_addr[8];                  /* 0x0001{30,,,68} */
 321     picreg_t            p_err_int_view;                 /* 0x000170 */
 322     picreg_t            p_mult_int;                     /* 0x000178 */
 323     picreg_t            p_force_always[8];              /* 0x0001{80,,,B8} */
 324     picreg_t            p_force_pin[8];                 /* 0x0001{C0,,,F8} */
 325
 326     /* 0x000200-0x000298 -- Device */
 327     picreg_t            p_device[4];                    /* 0x0002{00,,,18} */
 328     picreg_t            _pad_000220[4];                 /* 0x0002{20,,,38} */
 329     picreg_t            p_wr_req_buf[4];                /* 0x0002{40,,,58} */
 330     picreg_t            _pad_000260[4];                 /* 0x0002{60,,,78} */
 331     picreg_t            p_rrb_map[2];                   /* 0x0002{80,,,88} */
 332     #define p_even_resp p_rrb_map[0]                    /* 0x000280 */
 333     #define p_odd_resp  p_rrb_map[1]                    /* 0x000288 */
 334     picreg_t            p_resp_status;                  /* 0x000290 */
 335     picreg_t            p_resp_clear;                   /* 0x000298 */
 336
 337     picreg_t            _pad_0002A0[12];                /* 0x0002{A0..F8} */
 338
 339     /* 0x000300-0x0003F8 -- Buffer Address Match Registers */
 340     struct {
 341         picreg_t        upper;                          /* 0x0003{00,,,F0} */
 342         picreg_t        lower;                          /* 0x0003{08,,,F8} */
 343     } p_buf_addr_match[16];
 344
 345     /* 0x000400-0x0005FF -- Performance Monitor Registers (even only) */
 346     struct {
 347         picreg_t        flush_w_touch;                  /* 0x000{400,,,5C0} */
 348         picreg_t        flush_wo_touch;                 /* 0x000{408,,,5C8} */
 349         picreg_t        inflight;                       /* 0x000{410,,,5D0} */
 350         picreg_t        prefetch;                       /* 0x000{418,,,5D8} */
 351         picreg_t        total_pci_retry;                /* 0x000{420,,,5E0} */
 352         picreg_t        max_pci_retry;                  /* 0x000{428,,,5E8} */
 353         picreg_t        max_latency;                    /* 0x000{430,,,5F0} */
 354         picreg_t        clear_all;                      /* 0x000{438,,,5F8} */
 355     } p_buf_count[8];
 356
 357
 358     /* 0x000600-0x0009FF -- PCI/X registers */
 359     picreg_t            p_pcix_bus_err_addr;            /* 0x000600 */
 360     picreg_t            p_pcix_bus_err_attr;            /* 0x000608 */
 361     picreg_t            p_pcix_bus_err_data;            /* 0x000610 */
 362     picreg_t            p_pcix_pio_split_addr;          /* 0x000618 */
 363     picreg_t            p_pcix_pio_split_attr;          /* 0x000620 */
 364     picreg_t            p_pcix_dma_req_err_attr;        /* 0x000628 */
 365     picreg_t            p_pcix_dma_req_err_addr;        /* 0x000630 */
 366     picreg_t            p_pcix_timeout;                 /* 0x000638 */
 367
 368     picreg_t            _pad_000640[120];               /* 0x000{640,,,9F8} */
 369
 370     /* 0x000A00-0x000BFF -- PCI/X Read&Write Buffer */
 371     struct {
 372         picreg_t        p_buf_addr;                     /* 0x000{A00,,,AF0} */
 373         picreg_t        p_buf_attr;                     /* 0X000{A08,,,AF8} */
 374     } p_pcix_read_buf_64[16];
 375
 376     struct {
 377         picreg_t        p_buf_addr;                     /* 0x000{B00,,,BE0} */
 378         picreg_t        p_buf_attr;                     /* 0x000{B08,,,BE8} */
 379         picreg_t        p_buf_valid;                    /* 0x000{B10,,,BF0} */
 380         picreg_t        __pad1;                         /* 0x000{B18,,,BF8} */
 381     } p_pcix_write_buf_64[8];
 382
 383     /* End of Local Registers -- Start of Address Map space */
 384
 385     char                _pad_000c00[0x010000 - 0x000c00];
 386
 387     /* 0x010000-0x011fff -- Internal ATE RAM (Auto Parity Generation) */
 388     picate_t            p_int_ate_ram[1024];            /* 0x010000-0x011fff */
 389
 390     /* 0x012000-0x013fff -- Internal ATE RAM (Manual Parity Generation) */
 391     picate_t            p_int_ate_ram_mp[1024];         /* 0x012000-0x013fff */
 392
 393     char                _pad_014000[0x18000 - 0x014000];
 394
 395     /* 0x18000-0x197F8 -- PIC Write Request Ram */
 396     picreg_t            p_wr_req_lower[256];            /* 0x18000 - 0x187F8 */
 397     picreg_t            p_wr_req_upper[256];            /* 0x18800 - 0x18FF8 */
 398     picreg_t            p_wr_req_parity[256];           /* 0x19000 - 0x197F8 */
 399
 400     char                _pad_019800[0x20000 - 0x019800];
 401
 402     /* 0x020000-0x027FFF -- PCI Device Configuration Spaces */
 403     union {
 404         uint8_t         c[0x1000 / 1];                  /* 0x02{0000,,,7FFF} */
 405         uint16_t        s[0x1000 / 2];                  /* 0x02{0000,,,7FFF} */
 406         uint32_t        l[0x1000 / 4];                  /* 0x02{0000,,,7FFF} */
 407         uint64_t        d[0x1000 / 8];                  /* 0x02{0000,,,7FFF} */
 408         union {
 409             uint8_t     c[0x100 / 1];
 410             uint16_t    s[0x100 / 2];
 411             uint32_t    l[0x100 / 4];
 412             uint64_t    d[0x100 / 8];
 413         } f[8];
 414     } p_type0_cfg_dev[8];                               /* 0x02{0000,,,7FFF} */
 415
 416     /* 0x028000-0x028FFF -- PCI Type 1 Configuration Space */
 417     union {
 418         uint8_t         c[0x1000 / 1];                  /* 0x028000-0x029000 */
 419         uint16_t        s[0x1000 / 2];                  /* 0x028000-0x029000 */
 420         uint32_t        l[0x1000 / 4];                  /* 0x028000-0x029000 */
 421         uint64_t        d[0x1000 / 8];                  /* 0x028000-0x029000 */
 422         union {
 423             uint8_t     c[0x100 / 1];
 424             uint16_t    s[0x100 / 2];
 425             uint32_t    l[0x100 / 4];
 426             uint64_t    d[0x100 / 8];
 427         } f[8];
 428     } p_type1_cfg;                                      /* 0x028000-0x029000 */
 429
 430     char                _pad_029000[0x030000-0x029000];
 431
 432     /* 0x030000-0x030007 -- PCI Interrupt Acknowledge Cycle */
 433     union {
 434         uint8_t         c[8 / 1];
 435         uint16_t        s[8 / 2];
 436         uint32_t        l[8 / 4];
 437         uint64_t        d[8 / 8];
 438     } p_pci_iack;                                       /* 0x030000-0x030007 */
 439
 440     char                _pad_030007[0x040000-0x030008];
 441
 442     /* 0x040000-0x030007 -- PCIX Special Cycle */
 443     union {
 444         uint8_t         c[8 / 1];
 445         uint16_t        s[8 / 2];
 446         uint32_t        l[8 / 4];
 447         uint64_t        d[8 / 8];
 448     } p_pcix_cycle;                                     /* 0x040000-0x040007 */
 449 } pic_t;
 450
 451 #endif                          /* _ASM_IA64_SN_PCI_PIC_H */