include/asm-ia64/sn/pci/pciio.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1992 - 1997, 2000-2003 Silicon Graphics, Inc. All rights reserved.
   7  */
   8 #ifndef _ASM_IA64_SN_PCI_PCIIO_H
   9 #define _ASM_IA64_SN_PCI_PCIIO_H
  10
  11 /*
  12  * pciio.h -- platform-independent PCI interface
  13  */
  14
  15 #ifdef __KERNEL__
  16 #include <linux/ioport.h>
  17 #include <asm/sn/ioerror.h>
  18 #include <asm/sn/driver.h>
  19 #include <asm/sn/hcl.h>
  20 #else
  21 #include <linux/ioport.h>
  22 #include <ioerror.h>
  23 #include <driver.h>
  24 #include <hcl.h>
  25 #endif
  26
  27 #ifndef __ASSEMBLY__
  28
  29 #ifdef __KERNEL__
  30 #include <asm/sn/dmamap.h>
  31 #else
  32 #include <dmamap.h>
  33 #endif
  34
  35 typedef int pciio_vendor_id_t;
  36
  37 #define PCIIO_VENDOR_ID_NONE    (-1)
  38
  39 typedef int pciio_device_id_t;
  40
  41 #define PCIIO_DEVICE_ID_NONE    (-1)
  42
  43 typedef uint8_t pciio_bus_t;       /* PCI bus number (0..255) */
  44 typedef uint8_t pciio_slot_t;      /* PCI slot number (0..31, 255) */
  45 typedef uint8_t pciio_function_t;  /* PCI func number (0..7, 255) */
  46
  47 #define PCIIO_SLOTS             ((pciio_slot_t)32)
  48 #define PCIIO_FUNCS             ((pciio_function_t)8)
  49
  50 #define PCIIO_SLOT_NONE         ((pciio_slot_t)255)
  51 #define PCIIO_FUNC_NONE         ((pciio_function_t)255)
  52
  53 typedef int pciio_intr_line_t;          /* PCI interrupt line(s) */
  54
  55 #define PCIIO_INTR_LINE(n)      (0x1 << (n))
  56 #define PCIIO_INTR_LINE_A       (0x1)
  57 #define PCIIO_INTR_LINE_B       (0x2)
  58 #define PCIIO_INTR_LINE_C       (0x4)
  59 #define PCIIO_INTR_LINE_D       (0x8)
  60
  61 typedef int pciio_space_t;              /* PCI address space designation */
  62
  63 #define PCIIO_SPACE_NONE        (0)
  64 #define PCIIO_SPACE_ROM         (1)
  65 #define PCIIO_SPACE_IO          (2)
  66 /*      PCIIO_SPACE_            (3) */
  67 #define PCIIO_SPACE_MEM         (4)
  68 #define PCIIO_SPACE_MEM32       (5)
  69 #define PCIIO_SPACE_MEM64       (6)
  70 #define PCIIO_SPACE_CFG         (7)
  71 #define PCIIO_SPACE_WIN0        (8)
  72 #define PCIIO_SPACE_WIN(n)      (PCIIO_SPACE_WIN0+(n))  /* 8..13 */
  73 /*      PCIIO_SPACE_            (14) */
  74 #define PCIIO_SPACE_BAD         (15)
  75
  76 #if 1   /* does anyone really use these? */
  77 #define PCIIO_SPACE_USER0       (20)
  78 #define PCIIO_SPACE_USER(n)     (PCIIO_SPACE_USER0+(n)) /* 20 .. ? */
  79 #endif
  80
  81 /*
  82  * PCI_NOWHERE is the error value returned in
  83  * place of a PCI address when there is no
  84  * corresponding address.
  85  */
  86 #define PCI_NOWHERE             (0)
  87
  88 /*
  89  *    Acceptable flag bits for pciio service calls
  90  *
  91  * PCIIO_FIXED: require that mappings be established
  92  *      using fixed sharable resources; address
  93  *      translation results will be permanently
  94  *      available. (PIOMAP_FIXED and DMAMAP_FIXED are
  95  *      the same numeric value and are acceptable).
  96  * PCIIO_NOSLEEP: if any part of the operation would
  97  *      sleep waiting for resoruces, return an error
  98  *      instead. (PIOMAP_NOSLEEP and DMAMAP_NOSLEEP are
  99  *      the same numeric value and are acceptable).
 100  *
 101  * PCIIO_DMA_CMD: configure this stream as a
 102  *      generic "command" stream. Generally this
 103  *      means turn off prefetchers and write
 104  *      gatherers, and whatever else might be
 105  *      necessary to make command ring DMAs
 106  *      work as expected.
 107  * PCIIO_DMA_DATA: configure this stream as a
 108  *      generic "data" stream. Generally, this
 109  *      means turning on prefetchers and write
 110  *      gatherers, and anything else that might
 111  *      increase the DMA throughput (short of
 112  *      using "high priority" or "real time"
 113  *      resources that may lower overall system
 114  *      performance).
 115  * PCIIO_DMA_A64: this device is capable of
 116  *      using 64-bit DMA addresses. Unless this
 117  *      flag is specified, it is assumed that
 118  *      the DMA address must be in the low 4G
 119  *      of PCI space.
 120  * PCIIO_PREFETCH: if there are prefetchers
 121  *      available, they can be turned on.
 122  * PCIIO_NOPREFETCH: any prefetchers along
 123  *      the dma path should be turned off.
 124  * PCIIO_WRITE_GATHER: if there are write gatherers
 125  *      available, they can be turned on.
 126  * PCIIO_NOWRITE_GATHER: any write gatherers along
 127  *      the dma path should be turned off.
 128  *
 129  * PCIIO_BYTE_STREAM: the DMA stream represents a group
 130  *      of ordered bytes. Arrange all byte swapping
 131  *      hardware so that the bytes land in the correct
 132  *      order. This is a common setting for data
 133  *      channels, but is NOT implied by PCIIO_DMA_DATA.
 134  * PCIIO_WORD_VALUES: the DMA stream is used to
 135  *      communicate quantities stored in multiple bytes,
 136  *      and the device doing the DMA is little-endian;
 137  *      arrange any swapping hardware so that
 138  *      32-bit-wide values are maintained. This is a
 139  *      common setting for command rings that contain
 140  *      DMA addresses and counts, but is NOT implied by
 141  *      PCIIO_DMA_CMD. CPU Accesses to 16-bit fields
 142  *      must have their address xor-ed with 2, and
 143  *      accesses to individual bytes must have their
 144  *      addresses xor-ed with 3 relative to what the
 145  *      device expects.
 146  *
 147  * NOTE: any "provider specific" flags that
 148  * conflict with the generic flags will
 149  * override the generic flags, locally
 150  * at that provider.
 151  *
 152  * Also, note that PCI-generic flags (PCIIO_) are
 153  * in bits 0-14. The upper bits, 15-31, are reserved
 154  * for PCI implementation-specific flags.
 155  */
 156
 157 #define PCIIO_FIXED             DMAMAP_FIXED
 158 #define PCIIO_NOSLEEP           DMAMAP_NOSLEEP
 159
 160 #define PCIIO_DMA_CMD           0x0010
 161 #define PCIIO_DMA_DATA          0x0020
 162 #define PCIIO_DMA_A64           0x0040
 163
 164 #define PCIIO_WRITE_GATHER      0x0100
 165 #define PCIIO_NOWRITE_GATHER    0x0200
 166 #define PCIIO_PREFETCH          0x0400
 167 #define PCIIO_NOPREFETCH        0x0800
 168
 169 /* Requesting an endianness setting that the
 170  * underlieing hardware can not support
 171  * WILL result in a failure to allocate
 172  * dmamaps or complete a dmatrans.
 173  */
 174 #define PCIIO_BYTE_STREAM       0x1000  /* set BYTE SWAP for "byte stream" */
 175 #define PCIIO_WORD_VALUES       0x2000  /* set BYTE SWAP for "word values" */
 176
 177 /*
 178  * Interface to deal with PCI endianness.
 179  * The driver calls pciio_endian_set once, supplying the actual endianness of
 180  * the device and the desired endianness.  On SGI systems, only use LITTLE if
 181  * dealing with a driver that does software swizzling.  Most of the time,
 182  * it's preferable to request BIG.  The return value indicates the endianness
 183  * that is actually achieved.  On systems that support hardware swizzling,
 184  * the achieved endianness will be the desired endianness.  On systems without
 185  * swizzle hardware, the achieved endianness will be the device's endianness.
 186  */
 187 typedef enum pciio_endian_e {
 188     PCIDMA_ENDIAN_BIG,
 189     PCIDMA_ENDIAN_LITTLE
 190 } pciio_endian_t;
 191
 192 /*
 193  * Generic PCI bus information
 194  */
 195 typedef enum pciio_asic_type_e {
 196     PCIIO_ASIC_TYPE_UNKNOWN,
 197     PCIIO_ASIC_TYPE_MACE,
 198     PCIIO_ASIC_TYPE_BRIDGE,
 199     PCIIO_ASIC_TYPE_XBRIDGE,
 200     PCIIO_ASIC_TYPE_PIC,
 201 } pciio_asic_type_t;
 202
 203 typedef enum pciio_bus_type_e {
 204     PCIIO_BUS_TYPE_UNKNOWN,
 205     PCIIO_BUS_TYPE_PCI,
 206     PCIIO_BUS_TYPE_PCIX
 207 } pciio_bus_type_t;
 208
 209 typedef enum pciio_bus_speed_e {
 210     PCIIO_BUS_SPEED_UNKNOWN,
 211     PCIIO_BUS_SPEED_33,
 212     PCIIO_BUS_SPEED_66,
 213     PCIIO_BUS_SPEED_100,
 214     PCIIO_BUS_SPEED_133
 215 } pciio_bus_speed_t;
 216
 217 /*
 218  * Interface to set PCI arbitration priority for devices that require
 219  * realtime characteristics.  pciio_priority_set is used to switch a
 220  * device between the PCI high-priority arbitration ring and the low
 221  * priority arbitration ring.
 222  *
 223  * (Note: this is strictly for the PCI arbitrary priority.  It has
 224  * no direct relationship to GBR.)
 225  */
 226 typedef enum pciio_priority_e {
 227     PCI_PRIO_LOW,
 228     PCI_PRIO_HIGH
 229 } pciio_priority_t;
 230
 231 /*
 232  * handles of various sorts
 233  */
 234 typedef struct pciio_piomap_s *pciio_piomap_t;
 235 typedef struct pciio_dmamap_s *pciio_dmamap_t;
 236 typedef struct pciio_intr_s *pciio_intr_t;
 237 typedef struct pciio_info_s *pciio_info_t;
 238 typedef struct pciio_piospace_s *pciio_piospace_t;
 239 typedef struct pciio_win_info_s *pciio_win_info_t;
 240 typedef struct pciio_win_map_s *pciio_win_map_t;
 241 typedef struct pciio_win_alloc_s *pciio_win_alloc_t;
 242 typedef struct pciio_bus_map_s *pciio_bus_map_t;
 243 typedef struct pciio_businfo_s *pciio_businfo_t;
 244
 245
 246 /* PIO MANAGEMENT */
 247
 248 /*
 249  *    A NOTE ON PCI PIO ADDRESSES
 250  *
 251  *      PCI supports three different address spaces: CFG
 252  *      space, MEM space and I/O space. Further, each
 253  *      card always accepts CFG accesses at an address
 254  *      based on which slot it is attached to, but can
 255  *      decode up to six address ranges.
 256  *
 257  *      Assignment of the base address registers for all
 258  *      PCI devices is handled centrally; most commonly,
 259  *      device drivers will want to talk to offsets
 260  *      within one or another of the address ranges. In
 261  *      order to do this, which of these "address
 262  *      spaces" the PIO is directed into must be encoded
 263  *      in the flag word.
 264  *
 265  *      We reserve the right to defer allocation of PCI
 266  *      address space for a device window until the
 267  *      driver makes a piomap_alloc or piotrans_addr
 268  *      request.
 269  *
 270  *      If a device driver mucks with its device's base
 271  *      registers through a PIO mapping to CFG space,
 272  *      results of further PIO through the corresponding
 273  *      window are UNDEFINED.
 274  *
 275  *      Windows are named by the index in the base
 276  *      address register set for the device of the
 277  *      desired register; IN THE CASE OF 64 BIT base
 278  *      registers, the index should be to the word of
 279  *      the register that contains the mapping type
 280  *      bits; since the PCI CFG space is natively
 281  *      organized little-endian fashion, this is the
 282  *      first of the two words.
 283  *
 284  *      AT THE MOMENT, any required corrections for
 285  *      endianness are the responsibility of the device
 286  *      driver; not all platforms support control in
 287  *      hardware of byteswapping hardware. We anticipate
 288  *      providing flag bits to the PIO and DMA
 289  *      management interfaces to request different
 290  *      configurations of byteswapping hardware.
 291  *
 292  *      PIO Accesses to CFG space via the "Bridge" ASIC
 293  *      used in IP30 platforms preserve the native byte
 294  *      significance within the 32-bit word; byte
 295  *      addresses for single byte accesses need to be
 296  *      XORed with 3, and addresses for 16-bit accesses
 297  *      need to be XORed with 2.
 298  *
 299  *      The IOC3 used on IP30, and other SGI PCI devices
 300  *      as well, require use of 32-bit accesses to their
 301  *      configuration space registers. Any potential PCI
 302  *      bus providers need to be aware of this requirement.
 303  */
 304
 305 #define PCIIO_PIOMAP_CFG        (0x1)
 306 #define PCIIO_PIOMAP_MEM        (0x2)
 307 #define PCIIO_PIOMAP_IO         (0x4)
 308 #define PCIIO_PIOMAP_WIN(n)     (0x8+(n))
 309
 310 typedef pciio_piomap_t
 311 pciio_piomap_alloc_f    (vertex_hdl_t dev,      /* set up mapping for this device */
 312                          device_desc_t dev_desc,        /* device descriptor */
 313                          pciio_space_t space,   /* which address space */
 314                          iopaddr_t pcipio_addr,         /* starting address */
 315                          size_t byte_count,
 316                          size_t byte_count_max,         /* maximum size of a mapping */
 317                          unsigned int flags);   /* defined in sys/pio.h */
 318
 319 typedef void
 320 pciio_piomap_free_f     (pciio_piomap_t pciio_piomap);
 321
 322 typedef caddr_t
 323 pciio_piomap_addr_f     (pciio_piomap_t pciio_piomap,   /* mapping resources */
 324                          iopaddr_t pciio_addr,  /* map for this pcipio address */
 325                          size_t byte_count);    /* map this many bytes */
 326
 327 typedef void
 328 pciio_piomap_done_f     (pciio_piomap_t pciio_piomap);
 329
 330 typedef caddr_t
 331 pciio_piotrans_addr_f   (vertex_hdl_t dev,      /* translate for this device */
 332                          device_desc_t dev_desc,        /* device descriptor */
 333                          pciio_space_t space,   /* which address space */
 334                          iopaddr_t pciio_addr,  /* starting address */
 335                          size_t byte_count,     /* map this many bytes */
 336                          unsigned int flags);
 337
 338 typedef caddr_t
 339 pciio_pio_addr_f        (vertex_hdl_t dev,      /* translate for this device */
 340                          device_desc_t dev_desc,        /* device descriptor */
 341                          pciio_space_t space,   /* which address space */
 342                          iopaddr_t pciio_addr,  /* starting address */
 343                          size_t byte_count,     /* map this many bytes */
 344                          pciio_piomap_t *mapp,  /* in case a piomap was needed */
 345                          unsigned int flags);
 346
 347 typedef iopaddr_t
 348 pciio_piospace_alloc_f  (vertex_hdl_t dev,      /* PIO space for this device */
 349                          device_desc_t dev_desc,        /* Device descriptor   */
 350                          pciio_space_t space,   /* which address space  */
 351                          size_t byte_count,     /* Number of bytes of space */
 352                          size_t alignment);     /* Alignment of allocation  */
 353
 354 typedef void
 355 pciio_piospace_free_f   (vertex_hdl_t dev,      /* Device freeing space */
 356                          pciio_space_t space,   /* Which space is freed */
 357                          iopaddr_t pci_addr,    /* Address being freed */
 358                          size_t size);  /* Size freed           */
 359
 360 /* DMA MANAGEMENT */
 361
 362 typedef pciio_dmamap_t
 363 pciio_dmamap_alloc_f    (vertex_hdl_t dev,      /* set up mappings for this device */
 364                          device_desc_t dev_desc,        /* device descriptor */
 365                          size_t byte_count_max,         /* max size of a mapping */
 366                          unsigned int flags);   /* defined in dma.h */
 367
 368 typedef void
 369 pciio_dmamap_free_f     (pciio_dmamap_t dmamap);
 370
 371 typedef iopaddr_t
 372 pciio_dmamap_addr_f     (pciio_dmamap_t dmamap,         /* use these mapping resources */
 373                          paddr_t paddr, /* map for this address */
 374                          size_t byte_count);    /* map this many bytes */
 375
 376 typedef void
 377 pciio_dmamap_done_f     (pciio_dmamap_t dmamap);
 378
 379 typedef iopaddr_t
 380 pciio_dmatrans_addr_f   (vertex_hdl_t dev,      /* translate for this device */
 381                          device_desc_t dev_desc,        /* device descriptor */
 382                          paddr_t paddr, /* system physical address */
 383                          size_t byte_count,     /* length */
 384                          unsigned int flags);   /* defined in dma.h */
 385
 386 typedef void
 387 pciio_dmamap_drain_f    (pciio_dmamap_t map);
 388
 389 typedef void
 390 pciio_dmaaddr_drain_f   (vertex_hdl_t vhdl,
 391                          paddr_t addr,
 392                          size_t bytes);
 393
 394
 395 /* INTERRUPT MANAGEMENT */
 396
 397 typedef pciio_intr_t
 398 pciio_intr_alloc_f      (vertex_hdl_t dev,      /* which PCI device */
 399                          device_desc_t dev_desc,        /* device descriptor */
 400                          pciio_intr_line_t lines,       /* which line(s) will be used */
 401                          vertex_hdl_t owner_dev);       /* owner of this intr */
 402
 403 typedef void
 404 pciio_intr_free_f       (pciio_intr_t intr_hdl);
 405
 406 typedef int
 407 pciio_intr_connect_f    (pciio_intr_t intr_hdl, intr_func_t intr_func, intr_arg_t intr_arg);    /* pciio intr resource handle */
 408
 409 typedef void
 410 pciio_intr_disconnect_f (pciio_intr_t intr_hdl);
 411
 412 typedef vertex_hdl_t
 413 pciio_intr_cpu_get_f    (pciio_intr_t intr_hdl);        /* pciio intr resource handle */
 414
 415 /* CONFIGURATION MANAGEMENT */
 416
 417 typedef void
 418 pciio_provider_startup_f (vertex_hdl_t pciio_provider);
 419
 420 typedef void
 421 pciio_provider_shutdown_f (vertex_hdl_t pciio_provider);
 422
 423 typedef int
 424 pciio_reset_f           (vertex_hdl_t conn);    /* pci connection point */
 425
 426 typedef pciio_endian_t                  /* actual endianness */
 427 pciio_endian_set_f      (vertex_hdl_t dev,      /* specify endianness for this device */
 428                          pciio_endian_t device_end,     /* endianness of device */
 429                          pciio_endian_t desired_end);   /* desired endianness */
 430
 431 typedef uint64_t
 432 pciio_config_get_f      (vertex_hdl_t conn,     /* pci connection point */
 433                          unsigned int reg,              /* register byte offset */
 434                          unsigned int size);    /* width in bytes (1..4) */
 435
 436 typedef void
 437 pciio_config_set_f      (vertex_hdl_t conn,     /* pci connection point */
 438                          unsigned int reg,              /* register byte offset */
 439                          unsigned int size,             /* width in bytes (1..4) */
 440                          uint64_t value);       /* value to store */
 441
 442 typedef pciio_slot_t
 443 pciio_error_extract_f   (vertex_hdl_t vhdl,
 444                          pciio_space_t *spacep,
 445                          iopaddr_t *addrp);
 446
 447 typedef void
 448 pciio_driver_reg_callback_f     (vertex_hdl_t conn,
 449                                 int key1,
 450                                 int key2,
 451                                 int error);
 452
 453 typedef void
 454 pciio_driver_unreg_callback_f   (vertex_hdl_t conn, /* pci connection point */
 455                                  int key1,
 456                                  int key2,
 457                                  int error);
 458
 459 typedef int
 460 pciio_device_unregister_f       (vertex_hdl_t conn);
 461
 462
 463 /*
 464  * Adapters that provide a PCI interface adhere to this software interface.
 465  */
 466 typedef struct pciio_provider_s {
 467     /* ASIC PROVIDER ID */
 468     pciio_asic_type_t      provider_asic;
 469
 470     /* PIO MANAGEMENT */
 471     pciio_piomap_alloc_f   *piomap_alloc;
 472     pciio_piomap_free_f    *piomap_free;
 473     pciio_piomap_addr_f    *piomap_addr;
 474     pciio_piomap_done_f    *piomap_done;
 475     pciio_piotrans_addr_f  *piotrans_addr;
 476     pciio_piospace_alloc_f *piospace_alloc;
 477     pciio_piospace_free_f  *piospace_free;
 478
 479     /* DMA MANAGEMENT */
 480     pciio_dmamap_alloc_f   *dmamap_alloc;
 481     pciio_dmamap_free_f    *dmamap_free;
 482     pciio_dmamap_addr_f    *dmamap_addr;
 483     pciio_dmamap_done_f    *dmamap_done;
 484     pciio_dmatrans_addr_f  *dmatrans_addr;
 485     pciio_dmamap_drain_f   *dmamap_drain;
 486     pciio_dmaaddr_drain_f  *dmaaddr_drain;
 487
 488     /* INTERRUPT MANAGEMENT */
 489     pciio_intr_alloc_f     *intr_alloc;
 490     pciio_intr_free_f      *intr_free;
 491     pciio_intr_connect_f   *intr_connect;
 492     pciio_intr_disconnect_f *intr_disconnect;
 493     pciio_intr_cpu_get_f   *intr_cpu_get;
 494
 495     /* CONFIGURATION MANAGEMENT */
 496     pciio_provider_startup_f *provider_startup;
 497     pciio_provider_shutdown_f *provider_shutdown;
 498     pciio_reset_f          *reset;
 499     pciio_endian_set_f     *endian_set;
 500     pciio_config_get_f     *config_get;
 501     pciio_config_set_f     *config_set;
 502
 503     /* Error handling interface */
 504     pciio_error_extract_f *error_extract;
 505
 506     /* Callback support */
 507     pciio_driver_reg_callback_f *driver_reg_callback;
 508     pciio_driver_unreg_callback_f *driver_unreg_callback;
 509     pciio_device_unregister_f   *device_unregister;
 510 } pciio_provider_t;
 511
 512 /* PCI devices use these standard PCI provider interfaces */
 513 extern pciio_piomap_alloc_f pciio_piomap_alloc;
 514 extern pciio_piomap_free_f pciio_piomap_free;
 515 extern pciio_piomap_addr_f pciio_piomap_addr;
 516 extern pciio_piomap_done_f pciio_piomap_done;
 517 extern pciio_piotrans_addr_f pciio_piotrans_addr;
 518 extern pciio_pio_addr_f pciio_pio_addr;
 519 extern pciio_piospace_alloc_f pciio_piospace_alloc;
 520 extern pciio_piospace_free_f pciio_piospace_free;
 521 extern pciio_dmamap_alloc_f pciio_dmamap_alloc;
 522 extern pciio_dmamap_free_f pciio_dmamap_free;
 523 extern pciio_dmamap_addr_f pciio_dmamap_addr;
 524 extern pciio_dmamap_done_f pciio_dmamap_done;
 525 extern pciio_dmatrans_addr_f pciio_dmatrans_addr;
 526 extern pciio_dmamap_drain_f pciio_dmamap_drain;
 527 extern pciio_dmaaddr_drain_f pciio_dmaaddr_drain;
 528 extern pciio_intr_alloc_f pciio_intr_alloc;
 529 extern pciio_intr_free_f pciio_intr_free;
 530 extern pciio_intr_connect_f pciio_intr_connect;
 531 extern pciio_intr_disconnect_f pciio_intr_disconnect;
 532 extern pciio_intr_cpu_get_f pciio_intr_cpu_get;
 533 extern pciio_provider_startup_f pciio_provider_startup;
 534 extern pciio_provider_shutdown_f pciio_provider_shutdown;
 535 extern pciio_reset_f pciio_reset;
 536 extern pciio_endian_set_f pciio_endian_set;
 537 extern pciio_config_get_f pciio_config_get;
 538 extern pciio_config_set_f pciio_config_set;
 539
 540 /* Widgetdev in the IOERROR structure is encoded as follows.
 541  *      +---------------------------+
 542  *      | slot (7:3) | function(2:0)|
 543  *      +---------------------------+
 544  * Following are the convenience interfaces to get at form
 545  * a widgetdev or to break it into its constituents.
 546  */
 547
 548 #define PCIIO_WIDGETDEV_SLOT_SHFT               3
 549 #define PCIIO_WIDGETDEV_SLOT_MASK               0x1f
 550 #define PCIIO_WIDGETDEV_FUNC_MASK               0x7
 551
 552 #define pciio_widgetdev_create(slot,func)       \
 553         (((slot) << PCIIO_WIDGETDEV_SLOT_SHFT) + (func))
 554
 555 #define pciio_widgetdev_slot_get(wdev)          \
 556         (((wdev) >> PCIIO_WIDGETDEV_SLOT_SHFT) & PCIIO_WIDGETDEV_SLOT_MASK)
 557
 558 #define pciio_widgetdev_func_get(wdev)          \
 559         ((wdev) & PCIIO_WIDGETDEV_FUNC_MASK)
 560
 561
 562 /* Generic PCI card initialization interface
 563  */
 564
 565 extern int
 566 pciio_driver_register  (pciio_vendor_id_t vendor_id,    /* card's vendor number */
 567                         pciio_device_id_t device_id,    /* card's device number */
 568                         char *driver_prefix,    /* driver prefix */
 569                         unsigned int flags);
 570
 571 extern void
 572 pciio_error_register   (vertex_hdl_t pconn,     /* which slot */
 573                         error_handler_f *efunc, /* function to call */
 574                         error_handler_arg_t einfo);     /* first parameter */
 575
 576 extern void             pciio_driver_unregister(char *driver_prefix);
 577
 578 typedef void            pciio_iter_f(vertex_hdl_t pconn);       /* a connect point */
 579
 580 /* Interfaces used by PCI Bus Providers to talk to
 581  * the Generic PCI layer.
 582  */
 583 extern vertex_hdl_t
 584 pciio_device_register  (vertex_hdl_t connectpt, /* vertex at center of bus */
 585                         vertex_hdl_t master,    /* card's master ASIC (pci provider) */
 586                         pciio_slot_t slot,      /* card's slot (0..?) */
 587                         pciio_function_t func,  /* card's func (0..?) */
 588                         pciio_vendor_id_t vendor,       /* card's vendor number */
 589                         pciio_device_id_t device);      /* card's device number */
 590
 591 extern void
 592 pciio_device_unregister(vertex_hdl_t connectpt);
 593
 594 extern pciio_info_t
 595 pciio_device_info_new  (pciio_info_t pciio_info,        /* preallocated info struct */
 596                         vertex_hdl_t master,    /* card's master ASIC (pci provider) */
 597                         pciio_slot_t slot,      /* card's slot (0..?) */
 598                         pciio_function_t func,  /* card's func (0..?) */
 599                         pciio_vendor_id_t vendor,       /* card's vendor number */
 600                         pciio_device_id_t device);      /* card's device number */
 601
 602 extern void
 603 pciio_device_info_free(pciio_info_t pciio_info);
 604
 605 extern vertex_hdl_t
 606 pciio_device_info_register(
 607                         vertex_hdl_t connectpt, /* vertex at center of bus */
 608                         pciio_info_t pciio_info);       /* details about conn point */
 609
 610 extern void
 611 pciio_device_info_unregister(
 612                         vertex_hdl_t connectpt, /* vertex at center of bus */
 613                         pciio_info_t pciio_info);       /* details about conn point */
 614
 615
 616 extern int
 617 pciio_device_attach(
 618                         vertex_hdl_t pcicard,   /* vertex created by pciio_device_register */
 619                         int drv_flags);
 620 extern int
 621 pciio_device_detach(
 622                         vertex_hdl_t pcicard,   /* vertex created by pciio_device_register */
 623                         int drv_flags);
 624
 625
 626 /* create and initialize empty window mapping resource */
 627 extern pciio_win_map_t
 628 pciio_device_win_map_new(pciio_win_map_t win_map,       /* preallocated win map structure */
 629                          size_t region_size,            /* size of region to be tracked */
 630                          size_t page_size);             /* allocation page size */
 631
 632 /* destroy window mapping resource freeing up ancillary resources */
 633 extern void
 634 pciio_device_win_map_free(pciio_win_map_t win_map);     /* preallocated win map structure */
 635
 636 /* populate window mapping with free range of addresses */
 637 extern void
 638 pciio_device_win_populate(pciio_win_map_t win_map,      /* win map */
 639                           iopaddr_t ioaddr,             /* base address of free range */
 640                           size_t size);                 /* size of free range */
 641
 642 /* allocate window from mapping resource */
 643 extern iopaddr_t
 644 pciio_device_win_alloc(struct resource * res,
 645                        pciio_win_alloc_t win_alloc,     /* opaque allocation cookie */
 646                        size_t start,                    /* start unit, or 0 */
 647                        size_t size,                     /* size of allocation */
 648                        size_t align);                   /* alignment of allocation */
 649
 650 /* free previously allocated window */
 651 extern void
 652 pciio_device_win_free(pciio_win_alloc_t win_alloc);     /* opaque allocation cookie */
 653
 654
 655 /*
 656  * Generic PCI interface, for use with all PCI providers
 657  * and all PCI devices.
 658  */
 659
 660 /* Generic PCI interrupt interfaces */
 661 extern vertex_hdl_t     pciio_intr_dev_get(pciio_intr_t pciio_intr);
 662 extern vertex_hdl_t     pciio_intr_cpu_get(pciio_intr_t pciio_intr);
 663
 664 /* Generic PCI pio interfaces */
 665 extern vertex_hdl_t     pciio_pio_dev_get(pciio_piomap_t pciio_piomap);
 666 extern pciio_slot_t     pciio_pio_slot_get(pciio_piomap_t pciio_piomap);
 667 extern pciio_space_t    pciio_pio_space_get(pciio_piomap_t pciio_piomap);
 668 extern iopaddr_t        pciio_pio_pciaddr_get(pciio_piomap_t pciio_piomap);
 669 extern ulong            pciio_pio_mapsz_get(pciio_piomap_t pciio_piomap);
 670 extern caddr_t          pciio_pio_kvaddr_get(pciio_piomap_t pciio_piomap);
 671
 672 /* Generic PCI dma interfaces */
 673 extern vertex_hdl_t     pciio_dma_dev_get(pciio_dmamap_t pciio_dmamap);
 674
 675 /* Register/unregister PCI providers and get implementation handle */
 676 extern void             pciio_provider_register(vertex_hdl_t provider, pciio_provider_t *pciio_fns);
 677 extern void             pciio_provider_unregister(vertex_hdl_t provider);
 678 extern pciio_provider_t *pciio_provider_fns_get(vertex_hdl_t provider);
 679
 680 /* Generic pci slot information access interface */
 681 extern pciio_info_t     pciio_info_chk(vertex_hdl_t vhdl);
 682 extern pciio_info_t     pciio_info_get(vertex_hdl_t vhdl);
 683 extern void             pciio_info_set(vertex_hdl_t vhdl, pciio_info_t widget_info);
 684 extern vertex_hdl_t     pciio_info_dev_get(pciio_info_t pciio_info);
 685 extern pciio_bus_t      pciio_info_bus_get(pciio_info_t pciio_info);
 686 extern pciio_slot_t     pciio_info_slot_get(pciio_info_t pciio_info);
 687 extern pciio_function_t pciio_info_function_get(pciio_info_t pciio_info);
 688 extern pciio_vendor_id_t pciio_info_vendor_id_get(pciio_info_t pciio_info);
 689 extern pciio_device_id_t pciio_info_device_id_get(pciio_info_t pciio_info);
 690 extern vertex_hdl_t     pciio_info_master_get(pciio_info_t pciio_info);
 691 extern arbitrary_info_t pciio_info_mfast_get(pciio_info_t pciio_info);
 692 extern pciio_provider_t *pciio_info_pops_get(pciio_info_t pciio_info);
 693 extern error_handler_f *pciio_info_efunc_get(pciio_info_t);
 694 extern error_handler_arg_t *pciio_info_einfo_get(pciio_info_t);
 695 extern pciio_space_t    pciio_info_bar_space_get(pciio_info_t, int);
 696 extern iopaddr_t        pciio_info_bar_base_get(pciio_info_t, int);
 697 extern size_t           pciio_info_bar_size_get(pciio_info_t, int);
 698 extern iopaddr_t        pciio_info_rom_base_get(pciio_info_t);
 699 extern size_t           pciio_info_rom_size_get(pciio_info_t);
 700 extern int              pciio_info_type1_get(pciio_info_t);
 701 extern int              pciio_error_handler(vertex_hdl_t, int, ioerror_mode_t, ioerror_t *);
 702
 703 /**
 704  * sn_pci_set_vchan - Set the requested Virtual Channel bits into the mapped DMA
 705  *                    address.
 706  * @pci_dev: pci device pointer
 707  * @addr: mapped dma address
 708  * @vchan: Virtual Channel to use 0 or 1.
 709  *
 710  * Set the Virtual Channel bit in the mapped dma address.
 711  */
 712
 713 static inline int
 714 sn_pci_set_vchan(struct pci_dev *pci_dev,
 715                  dma_addr_t *addr,
 716                  int vchan)
 717 {
 718         if (vchan > 1) {
 719                 return -1;
 720         }
 721
 722         if (!(*addr >> 32))     /* Using a mask here would be cleaner */
 723                 return 0;       /* but this generates better code */
 724
 725         if (vchan == 1) {
 726                 /* Set Bit 57 */
 727                 *addr |= (1UL << 57);
 728         } else {
 729                 /* Clear Bit 57 */
 730                 *addr &= ~(1UL << 57);
 731         }
 732
 733         return 0;
 734 }
 735
 736 #endif                          /* C or C++ */
 737
 738
 739 /*
 740  * Prototypes
 741  */
 742
 743 int snia_badaddr_val(volatile void *addr, int len, volatile void *ptr);
 744 nasid_t snia_get_console_nasid(void);
 745 nasid_t snia_get_master_baseio_nasid(void);
 746 #endif                          /* _ASM_IA64_SN_PCI_PCIIO_H */