include/asm-arm/arch-omap/fpga.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/fpga.h
   3  *
   4  * Interrupt handler for OMAP-1510 FPGA
   5  *
   6  * Copyright (C) 2001 RidgeRun, Inc.
   7  * Author: Greg Lonnon <glonnon@ridgerun.com>
   8  *
   9  * Copyright (C) 2002 MontaVista Software, Inc.
  10  *
  11  * Separated FPGA interrupts from innovator1510.c and cleaned up for 2.6
  12  * Copyright (C) 2004 Nokia Corporation by Tony Lindrgen <tony@atomide.com>
  13  *
  14  * This program is free software; you can redistribute it and/or modify
  15  * it under the terms of the GNU General Public License version 2 as
  16  * published by the Free Software Foundation.
  17  */
  18
  19 #ifndef __ASM_ARCH_OMAP_FPGA_H
  20 #define __ASM_ARCH_OMAP_FPGA_H
  21
  22 #if defined(CONFIG_MACH_OMAP_INNOVATOR) && defined(CONFIG_ARCH_OMAP1510)
  23 extern void omap1510_fpga_init_irq(void);
  24 #else
  25 #define omap1510_fpga_init_irq()        (0)
  26 #endif
  27
  28 #define fpga_read(reg)                  __raw_readb(reg)
  29 #define fpga_write(val, reg)            __raw_writeb(val, reg)
  30
  31 /*
  32  * ---------------------------------------------------------------------------
  33  *  H2/P2 Debug board FPGA
  34  * ---------------------------------------------------------------------------
  35  */
  36 /* maps in the FPGA registers and the ETHR registers */
  37 #define H2P2_DBG_FPGA_BASE              0xE8000000      /* VA */
  38 #define H2P2_DBG_FPGA_SIZE              SZ_4K           /* SIZE */
  39 #define H2P2_DBG_FPGA_START             0x04000000      /* PA */
  40
  41 #define H2P2_DBG_FPGA_ETHR_START        H2P2_DBG_FPGA_START
  42 #define H2P2_DBG_FPGA_ETHR_BASE         H2P2_DBG_FPGA_BASE
  43 #define H2P2_DBG_FPGA_FPGA_REV          (H2P2_DBG_FPGA_BASE + 0x10)     /* FPGA Revision */
  44 #define H2P2_DBG_FPGA_BOARD_REV         (H2P2_DBG_FPGA_BASE + 0x12)     /* Board Revision */
  45 #define H2P2_DBG_FPGA_GPIO              (H2P2_DBG_FPGA_BASE + 0x14)     /* GPIO outputs */
  46 #define H2P2_DBG_FPGA_LEDS              (H2P2_DBG_FPGA_BASE + 0x16)     /* LEDs outputs */
  47 #define H2P2_DBG_FPGA_MISC_INPUTS       (H2P2_DBG_FPGA_BASE + 0x18)     /* Misc inputs */
  48 #define H2P2_DBG_FPGA_LAN_STATUS        (H2P2_DBG_FPGA_BASE + 0x1A)     /* LAN Status line */
  49 #define H2P2_DBG_FPGA_LAN_RESET         (H2P2_DBG_FPGA_BASE + 0x1C)     /* LAN Reset line */
  50
  51 /* LEDs definition on debug board (16 LEDs) */
  52 #define H2P2_DBG_FPGA_LED_CLAIMRELEASE  (1 << 15)
  53 #define H2P2_DBG_FPGA_LED_STARTSTOP     (1 << 14)
  54 #define H2P2_DBG_FPGA_LED_HALTED        (1 << 13)
  55 #define H2P2_DBG_FPGA_LED_IDLE          (1 << 12)
  56 #define H2P2_DBG_FPGA_LED_TIMER         (1 << 11)
  57 /*  cpu0 load-meter LEDs */
  58 #define H2P2_DBG_FPGA_LOAD_METER        (1 << 0)        // A bit of fun on our board ...
  59 #define H2P2_DBG_FPGA_LOAD_METER_SIZE   11
  60 #define H2P2_DBG_FPGA_LOAD_METER_MASK   ((1 << H2P2_DBG_FPGA_LOAD_METER_SIZE) - 1)
  61
  62
  63 /*
  64  * ---------------------------------------------------------------------------
  65  *  OMAP-1510 FPGA
  66  * ---------------------------------------------------------------------------
  67  */
  68 #define OMAP1510_FPGA_BASE                      0xE8000000      /* Virtual */
  69 #define OMAP1510_FPGA_SIZE                      SZ_4K
  70 #define OMAP1510_FPGA_START                     0x08000000      /* Physical */
  71
  72 /* Revision */
  73 #define OMAP1510_FPGA_REV_LOW                   (OMAP1510_FPGA_BASE + 0x0)
  74 #define OMAP1510_FPGA_REV_HIGH                  (OMAP1510_FPGA_BASE + 0x1)
  75
  76 #define OMAP1510_FPGA_LCD_PANEL_CONTROL         (OMAP1510_FPGA_BASE + 0x2)
  77 #define OMAP1510_FPGA_LED_DIGIT                 (OMAP1510_FPGA_BASE + 0x3)
  78 #define INNOVATOR_FPGA_HID_SPI                  (OMAP1510_FPGA_BASE + 0x4)
  79 #define OMAP1510_FPGA_POWER                     (OMAP1510_FPGA_BASE + 0x5)
  80
  81 /* Interrupt status */
  82 #define OMAP1510_FPGA_ISR_LO                    (OMAP1510_FPGA_BASE + 0x6)
  83 #define OMAP1510_FPGA_ISR_HI                    (OMAP1510_FPGA_BASE + 0x7)
  84
  85 /* Interrupt mask */
  86 #define OMAP1510_FPGA_IMR_LO                    (OMAP1510_FPGA_BASE + 0x8)
  87 #define OMAP1510_FPGA_IMR_HI                    (OMAP1510_FPGA_BASE + 0x9)
  88
  89 /* Reset registers */
  90 #define OMAP1510_FPGA_HOST_RESET                (OMAP1510_FPGA_BASE + 0xa)
  91 #define OMAP1510_FPGA_RST                       (OMAP1510_FPGA_BASE + 0xb)
  92
  93 #define OMAP1510_FPGA_AUDIO                     (OMAP1510_FPGA_BASE + 0xc)
  94 #define OMAP1510_FPGA_DIP                       (OMAP1510_FPGA_BASE + 0xe)
  95 #define OMAP1510_FPGA_FPGA_IO                   (OMAP1510_FPGA_BASE + 0xf)
  96 #define OMAP1510_FPGA_UART1                     (OMAP1510_FPGA_BASE + 0x14)
  97 #define OMAP1510_FPGA_UART2                     (OMAP1510_FPGA_BASE + 0x15)
  98 #define OMAP1510_FPGA_OMAP1510_STATUS           (OMAP1510_FPGA_BASE + 0x16)
  99 #define OMAP1510_FPGA_BOARD_REV                 (OMAP1510_FPGA_BASE + 0x18)
 100 #define OMAP1510P1_PPT_DATA                     (OMAP1510_FPGA_BASE + 0x100)
 101 #define OMAP1510P1_PPT_STATUS                   (OMAP1510_FPGA_BASE + 0x101)
 102 #define OMAP1510P1_PPT_CONTROL                  (OMAP1510_FPGA_BASE + 0x102)
 103
 104 #define OMAP1510_FPGA_TOUCHSCREEN               (OMAP1510_FPGA_BASE + 0x204)
 105
 106 #define INNOVATOR_FPGA_INFO                     (OMAP1510_FPGA_BASE + 0x205)
 107 #define INNOVATOR_FPGA_LCD_BRIGHT_LO            (OMAP1510_FPGA_BASE + 0x206)
 108 #define INNOVATOR_FPGA_LCD_BRIGHT_HI            (OMAP1510_FPGA_BASE + 0x207)
 109 #define INNOVATOR_FPGA_LED_GRN_LO               (OMAP1510_FPGA_BASE + 0x208)
 110 #define INNOVATOR_FPGA_LED_GRN_HI               (OMAP1510_FPGA_BASE + 0x209)
 111 #define INNOVATOR_FPGA_LED_RED_LO               (OMAP1510_FPGA_BASE + 0x20a)
 112 #define INNOVATOR_FPGA_LED_RED_HI               (OMAP1510_FPGA_BASE + 0x20b)
 113 #define INNOVATOR_FPGA_CAM_USB_CONTROL          (OMAP1510_FPGA_BASE + 0x20c)
 114 #define INNOVATOR_FPGA_EXP_CONTROL              (OMAP1510_FPGA_BASE + 0x20d)
 115 #define INNOVATOR_FPGA_ISR2                     (OMAP1510_FPGA_BASE + 0x20e)
 116 #define INNOVATOR_FPGA_IMR2                     (OMAP1510_FPGA_BASE + 0x210)
 117
 118 #define OMAP1510_FPGA_ETHR_START                (OMAP1510_FPGA_START + 0x300)
 119 #define OMAP1510_FPGA_ETHR_BASE                 (OMAP1510_FPGA_BASE + 0x300)
 120
 121 /*
 122  * Power up Giga UART driver, turn on HID clock.
 123  * Turn off BT power, since we're not using it and it
 124  * draws power.
 125  */
 126 #define OMAP1510_FPGA_RESET_VALUE               0x42
 127
 128 #define OMAP1510_FPGA_PCR_IF_PD0                (1 << 7)
 129 #define OMAP1510_FPGA_PCR_COM2_EN               (1 << 6)
 130 #define OMAP1510_FPGA_PCR_COM1_EN               (1 << 5)
 131 #define OMAP1510_FPGA_PCR_EXP_PD0               (1 << 4)
 132 #define OMAP1510_FPGA_PCR_EXP_PD1               (1 << 3)
 133 #define OMAP1510_FPGA_PCR_48MHZ_CLK             (1 << 2)
 134 #define OMAP1510_FPGA_PCR_4MHZ_CLK              (1 << 1)
 135 #define OMAP1510_FPGA_PCR_RSRVD_BIT0            (1 << 0)
 136
 137 /*
 138  * Innovator/OMAP1510 FPGA HID register bit definitions
 139  */
 140 #define OMAP1510_FPGA_HID_SCLK  (1<<0)  /* output */
 141 #define OMAP1510_FPGA_HID_MOSI  (1<<1)  /* output */
 142 #define OMAP1510_FPGA_HID_nSS   (1<<2)  /* output 0/1 chip idle/select */
 143 #define OMAP1510_FPGA_HID_nHSUS (1<<3)  /* output 0/1 host active/suspended */
 144 #define OMAP1510_FPGA_HID_MISO  (1<<4)  /* input */
 145 #define OMAP1510_FPGA_HID_ATN   (1<<5)  /* input  0/1 chip idle/ATN */
 146 #define OMAP1510_FPGA_HID_rsrvd (1<<6)
 147 #define OMAP1510_FPGA_HID_RESETn (1<<7) /* output - 0/1 USAR reset/run */
 148
 149 /* The FPGA IRQ is cascaded through GPIO_13 */
 150 #define OMAP1510_INT_FPGA               (IH_GPIO_BASE + 13)
 151
 152 /* IRQ Numbers for interrupts muxed through the FPGA */
 153 #define OMAP1510_IH_FPGA_BASE           IH_BOARD_BASE
 154 #define OMAP1510_INT_FPGA_ATN           (OMAP1510_IH_FPGA_BASE + 0)
 155 #define OMAP1510_INT_FPGA_ACK           (OMAP1510_IH_FPGA_BASE + 1)
 156 #define OMAP1510_INT_FPGA2              (OMAP1510_IH_FPGA_BASE + 2)
 157 #define OMAP1510_INT_FPGA3              (OMAP1510_IH_FPGA_BASE + 3)
 158 #define OMAP1510_INT_FPGA4              (OMAP1510_IH_FPGA_BASE + 4)
 159 #define OMAP1510_INT_FPGA5              (OMAP1510_IH_FPGA_BASE + 5)
 160 #define OMAP1510_INT_FPGA6              (OMAP1510_IH_FPGA_BASE + 6)
 161 #define OMAP1510_INT_FPGA7              (OMAP1510_IH_FPGA_BASE + 7)
 162 #define OMAP1510_INT_FPGA8              (OMAP1510_IH_FPGA_BASE + 8)
 163 #define OMAP1510_INT_FPGA9              (OMAP1510_IH_FPGA_BASE + 9)
 164 #define OMAP1510_INT_FPGA10             (OMAP1510_IH_FPGA_BASE + 10)
 165 #define OMAP1510_INT_FPGA11             (OMAP1510_IH_FPGA_BASE + 11)
 166 #define OMAP1510_INT_FPGA12             (OMAP1510_IH_FPGA_BASE + 12)
 167 #define OMAP1510_INT_ETHER              (OMAP1510_IH_FPGA_BASE + 13)
 168 #define OMAP1510_INT_FPGAUART1          (OMAP1510_IH_FPGA_BASE + 14)
 169 #define OMAP1510_INT_FPGAUART2          (OMAP1510_IH_FPGA_BASE + 15)
 170 #define OMAP1510_INT_FPGA_TS            (OMAP1510_IH_FPGA_BASE + 16)
 171 #define OMAP1510_INT_FPGA17             (OMAP1510_IH_FPGA_BASE + 17)
 172 #define OMAP1510_INT_FPGA_CAM           (OMAP1510_IH_FPGA_BASE + 18)
 173 #define OMAP1510_INT_FPGA_RTC_A         (OMAP1510_IH_FPGA_BASE + 19)
 174 #define OMAP1510_INT_FPGA_RTC_B         (OMAP1510_IH_FPGA_BASE + 20)
 175 #define OMAP1510_INT_FPGA_CD            (OMAP1510_IH_FPGA_BASE + 21)
 176 #define OMAP1510_INT_FPGA22             (OMAP1510_IH_FPGA_BASE + 22)
 177 #define OMAP1510_INT_FPGA23             (OMAP1510_IH_FPGA_BASE + 23)
 178
 179 #endif