include/asm-arm/arch-omap/board-h3.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/board-h3.h
   3  *
   4  * Copyright (C) 2001 RidgeRun, Inc.
   5  * Copyright (C) 2004 Texas Instruments, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License as published by the
   9  * Free Software Foundation; either version 2 of the License, or (at your
  10  * option) any later version.
  11  *
  12  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  13  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  14  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  15  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  16  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  17  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  18  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  19  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  20  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  21  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  22  *
  23  * You should have received a copy of the  GNU General Public License along
  24  * with this program; if not, write  to the Free Software Foundation, Inc.,
  25  * 675 Mass Ave, Cambridge, MA 02139, USA.
  26  */
  27 #ifndef __ASM_ARCH_OMAP_H3_H
  28 #define __ASM_ARCH_OMAP_H3_H
  29
  30 /* In OMAP1710 H3 the Ethernet is directly connected to CS1 */
  31 #define OMAP1710_ETHR_BASE              0xE8000000
  32 #define OMAP1710_ETHR_SIZE              SZ_4K
  33 #define OMAP1710_ETHR_START             0x04000000
  34
  35 /* Intel STRATA NOR flash at CS3 */
  36 #define OMAP_NOR_FLASH_BASE             0xD8000000
  37 #define OMAP_NOR_FLASH_SIZE             SZ_32M
  38 #define OMAP_NOR_FLASH_START            0x00000000
  39
  40 #define MAXIRQNUM                       (IH_BOARD_BASE)
  41 #define MAXFIQNUM                       MAXIRQNUM
  42 #define MAXSWINUM                       MAXIRQNUM
  43
  44 #define NR_IRQS                         (MAXIRQNUM + 1)
  45
  46 #define OMAP_MCBSP1_BASE                OMAP1610_MCBSP1_BASE
  47 #define AUDIO_DRR2  (OMAP_MCBSP1_BASE + 0x00)
  48 #define AUDIO_DRR1  (OMAP_MCBSP1_BASE + 0x02)
  49 #define AUDIO_DXR2  (OMAP_MCBSP1_BASE + 0x04)
  50 #define AUDIO_DXR1  (OMAP_MCBSP1_BASE + 0x06)
  51 #define AUDIO_SPCR2 (OMAP_MCBSP1_BASE + 0x08)
  52 #define AUDIO_SPCR1 (OMAP_MCBSP1_BASE + 0x0a)
  53 #define AUDIO_RCR2  (OMAP_MCBSP1_BASE + 0x0c)
  54 #define AUDIO_RCR1  (OMAP_MCBSP1_BASE + 0x0e)
  55 #define AUDIO_XCR2  (OMAP_MCBSP1_BASE + 0x10)
  56 #define AUDIO_XCR1  (OMAP_MCBSP1_BASE + 0x12)
  57 #define AUDIO_SRGR2 (OMAP_MCBSP1_BASE + 0x14)
  58 #define AUDIO_SRGR1 (OMAP_MCBSP1_BASE + 0x16)
  59 #define AUDIO_MCR2  (OMAP_MCBSP1_BASE + 0x18)
  60 #define AUDIO_MCR1  (OMAP_MCBSP1_BASE + 0x1a)
  61 #define AUDIO_RCERA (OMAP_MCBSP1_BASE + 0x1c)
  62 #define AUDIO_RCERB (OMAP_MCBSP1_BASE + 0x1e)
  63 #define AUDIO_XCERA (OMAP_MCBSP1_BASE + 0x20)
  64 #define AUDIO_XCERB (OMAP_MCBSP1_BASE + 0x22)
  65 #define AUDIO_PCR0  (OMAP_MCBSP1_BASE + 0x24)
  66
  67 /* UART3 Registers Maping through MPU bus */
  68 #define OMAP_MPU_UART3_BASE     0xFFFB9800      /* UART3 through MPU bus */
  69 #define UART3_RHR               (OMAP_MPU_UART3_BASE + 0)
  70 #define UART3_THR               (OMAP_MPU_UART3_BASE + 0)
  71 #define UART3_DLL               (OMAP_MPU_UART3_BASE + 0)
  72 #define UART3_IER               (OMAP_MPU_UART3_BASE + 4)
  73 #define UART3_DLH               (OMAP_MPU_UART3_BASE + 4)
  74 #define UART3_IIR               (OMAP_MPU_UART3_BASE + 8)
  75 #define UART3_FCR               (OMAP_MPU_UART3_BASE + 8)
  76 #define UART3_EFR               (OMAP_MPU_UART3_BASE + 8)
  77 #define UART3_LCR               (OMAP_MPU_UART3_BASE + 0x0C)
  78 #define UART3_MCR               (OMAP_MPU_UART3_BASE + 0x10)
  79 #define UART3_XON1_ADDR1        (OMAP_MPU_UART3_BASE + 0x10)
  80 #define UART3_XON2_ADDR2        (OMAP_MPU_UART3_BASE + 0x14)
  81 #define UART3_LSR               (OMAP_MPU_UART3_BASE + 0x14)
  82 #define UART3_TCR               (OMAP_MPU_UART3_BASE + 0x18)
  83 #define UART3_MSR               (OMAP_MPU_UART3_BASE + 0x18)
  84 #define UART3_XOFF1             (OMAP_MPU_UART3_BASE + 0x18)
  85 #define UART3_XOFF2             (OMAP_MPU_UART3_BASE + 0x1C)
  86 #define UART3_SPR               (OMAP_MPU_UART3_BASE + 0x1C)
  87 #define UART3_TLR               (OMAP_MPU_UART3_BASE + 0x1C)
  88 #define UART3_MDR1              (OMAP_MPU_UART3_BASE + 0x20)
  89 #define UART3_MDR2              (OMAP_MPU_UART3_BASE + 0x24)
  90 #define UART3_SFLSR             (OMAP_MPU_UART3_BASE + 0x28)
  91 #define UART3_TXFLL             (OMAP_MPU_UART3_BASE + 0x28)
  92 #define UART3_RESUME            (OMAP_MPU_UART3_BASE + 0x2C)
  93 #define UART3_TXFLH             (OMAP_MPU_UART3_BASE + 0x2C)
  94 #define UART3_SFREGL            (OMAP_MPU_UART3_BASE + 0x30)
  95 #define UART3_RXFLL             (OMAP_MPU_UART3_BASE + 0x30)
  96 #define UART3_SFREGH            (OMAP_MPU_UART3_BASE + 0x34)
  97 #define UART3_RXFLH             (OMAP_MPU_UART3_BASE + 0x34)
  98 #define UART3_BLR               (OMAP_MPU_UART3_BASE + 0x38)
  99 #define UART3_ACREG             (OMAP_MPU_UART3_BASE + 0x3C)
 100 #define UART3_DIV16             (OMAP_MPU_UART3_BASE + 0x3C)
 101 #define UART3_SCR               (OMAP_MPU_UART3_BASE + 0x40)
 102 #define UART3_SSR               (OMAP_MPU_UART3_BASE + 0x44)
 103 #define UART3_EBLR              (OMAP_MPU_UART3_BASE + 0x48)
 104 #define UART3_OSC_12M_SEL       (OMAP_MPU_UART3_BASE + 0x4C)
 105 #define UART3_MVR               (OMAP_MPU_UART3_BASE + 0x50)
 106
 107 #endif /*  __ASM_ARCH_OMAP_H3_H */