include/asm-arm/arch-ixp2000/ixp2000-regs.h

   1 /*
   2  * include/asm-arm/arch-ixp2000/ixp2000-regs.h
   3  *
   4  * Chipset register definitions for IXP2400/2800 based systems.
   5  *
   6  * Original Author: Naeem Afzal <naeem.m.afzal@intel.com>
   7  *
   8  * Maintainer: Deepak Saxena <dsaxena@plexity.net>
   9  *
  10  * Copyright (C) 2002 Intel Corp.
  11  * Copyright (C) 2003-2004 MontaVista Software, Inc.
  12  *
  13  *  This program is free software; you can redistribute  it and/or modify it
  14  *  under  the terms of  the GNU General  Public License as published by the
  15  *  Free Software Foundation;  either version 2 of the  License, or (at your
  16  *  option) any later version.
  17  */
  18 #ifndef _IXP2000_REGS_H_
  19 #define _IXP2000_REGS_H_
  20
  21 /*
  22  * Static I/O regions. The manual defines each region as being several
  23  * MB in size, but all the registers are within the first 4K, so there's
  24  * no purpose in mapping the whole region in.
  25  */
  26 #define IXP2000_SLOWPORT_CSR_PHYS_BASE  0xc0080000
  27 #define IXP2000_SLOWPORT_CSR_VIRT_BASE  0xfefff000
  28 #define IXP2000_SLOWPORT_CSR_SIZE       0x1000
  29
  30 #define IXP2000_GLOBAL_REG_PHYS_BASE    0xc0004000
  31 #define IXP2000_GLOBAL_REG_VIRT_BASE    0xfeffe000
  32 #define IXP2000_GLOBAL_REG_SIZE         0x1000
  33
  34 #define IXP2000_UART_PHYS_BASE          0xc0030000
  35 #define IXP2000_UART_VIRT_BASE          0xfef30000
  36 #define IXP2000_UART_SIZE               0x1000
  37
  38 #define IXP2000_TIMER_PHYS_BASE         0xc0020000
  39 #define IXP2000_TIMER_VIRT_BASE         0xfeffc000
  40 #define IXP2000_TIMER_SIZE              0x1000
  41
  42 #define IXP2000_GPIO_PHYS_BASE          0xc0010000
  43 #define IXP2000_GPIO_VIRT_BASE          0xfeffb000
  44 #define IXP2000_GPIO_SIZE               0x1000
  45
  46 #define IXP2000_INTCTL_PHYS_BASE        0xd6000000
  47 #define IXP2000_INTCTL_VIRT_BASE        0xfeffa000
  48 #define IXP2000_INTCTL_SIZE             0x01000
  49
  50 #define IXP2000_PCI_CREG_PHYS_BASE      0xde000000
  51 #define IXP2000_PCI_CREG_VIRT_BASE      0xfeff0000
  52 #define IXP2000_PCI_CREG_SIZE           0x1000
  53
  54 #define IXP2000_PCI_CSR_PHYS_BASE       0xdf000000
  55 #define IXP2000_PCI_CSR_VIRT_BASE       0xfefde000
  56 #define IXP2000_PCI_CSR_SIZE            0x1000
  57
  58 #define IXP2000_PCI_IO_PHYS_BASE        0xd8000000
  59 #define IXP2000_PCI_IO_VIRT_BASE        0xfd000000
  60 #define IXP2000_PCI_IO_SIZE             0x01000000
  61
  62 #define IXP2000_PCI_CFG0_PHYS_BASE      0xda000000
  63 #define IXP2000_PCI_CFG0_VIRT_BASE      0xfc000000
  64 #define IXP2000_PCI_CFG0_SIZE           0x01000000
  65
  66 #define IXP2000_PCI_CFG1_PHYS_BASE      0xdb000000
  67 #define IXP2000_PCI_CFG1_VIRT_BASE      0xfb000000
  68 #define IXP2000_PCI_CFG1_SIZE           0x01000000
  69
  70
  71 /*
  72  * Timers
  73  */
  74 #define IXP2000_TIMER_REG(x)            ((volatile unsigned long*)(IXP2000_TIMER_VIRT_BASE | (x)))
  75 /* Timer control */
  76 #define IXP2000_T1_CTL                  IXP2000_TIMER_REG(0x00)
  77 #define IXP2000_T2_CTL                  IXP2000_TIMER_REG(0x04)
  78 #define IXP2000_T3_CTL                  IXP2000_TIMER_REG(0x08)
  79 #define IXP2000_T4_CTL                  IXP2000_TIMER_REG(0x0c)
  80 /* Store initial value */
  81 #define IXP2000_T1_CLD                  IXP2000_TIMER_REG(0x10)
  82 #define IXP2000_T2_CLD                  IXP2000_TIMER_REG(0x14)
  83 #define IXP2000_T3_CLD                  IXP2000_TIMER_REG(0x18)
  84 #define IXP2000_T4_CLD                  IXP2000_TIMER_REG(0x1c)
  85 /* Read current value */
  86 #define IXP2000_T1_CSR                  IXP2000_TIMER_REG(0x20)
  87 #define IXP2000_T2_CSR                  IXP2000_TIMER_REG(0x24)
  88 #define IXP2000_T3_CSR                  IXP2000_TIMER_REG(0x28)
  89 #define IXP2000_T4_CSR                  IXP2000_TIMER_REG(0x2c)
  90 /* Clear associated timer interrupt */
  91 #define IXP2000_T1_CLR                  IXP2000_TIMER_REG(0x30)
  92 #define IXP2000_T2_CLR                  IXP2000_TIMER_REG(0x34)
  93 #define IXP2000_T3_CLR                  IXP2000_TIMER_REG(0x38)
  94 #define IXP2000_T4_CLR                  IXP2000_TIMER_REG(0x3c)
  95 /* Timer watchdog enable for T4 */
  96 #define IXP2000_TWDE                    IXP2000_TIMER_REG(0x40)
  97
  98 #define WDT_ENABLE                      0x00000001
  99 #define TIMER_DIVIDER_256               0x00000008
 100 #define TIMER_ENABLE                    0x00000080
 101
 102 /*
 103  * Interrupt controller registers
 104  */
 105 #define IXP2000_INTCTL_REG(x)           (volatile unsigned long*)(IXP2000_INTCTL_VIRT_BASE | (x))
 106 #define IXP2000_IRQ_STATUS              IXP2000_INTCTL_REG(0x08)
 107 #define IXP2000_IRQ_ENABLE              IXP2000_INTCTL_REG(0x10)
 108 #define IXP2000_IRQ_ENABLE_SET          IXP2000_INTCTL_REG(0x10)
 109 #define IXP2000_IRQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x18)
 110 #define IXP2000_FIQ_ENABLE_CLR          IXP2000_INTCTL_REG(0x14)
 111 #define IXP2000_IRQ_ERR_STATUS          IXP2000_INTCTL_REG(0x24)
 112 #define IXP2000_IRQ_ERR_ENABLE_SET      IXP2000_INTCTL_REG(0x2c)
 113 #define IXP2000_FIQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x30)
 114 #define IXP2000_IRQ_ERR_ENABLE_CLR      IXP2000_INTCTL_REG(0x34)
 115
 116 /*
 117  * Mask of valid IRQs in the 32-bit IRQ register. We use
 118  * this to mark certain IRQs as being in-valid.
 119  */
 120 #define IXP2000_VALID_IRQ_MASK  0x0f0fffff
 121
 122 /*
 123  * PCI config register access from core
 124  */
 125 #define IXP2000_PCI_CREG(x)             (volatile unsigned long*)(IXP2000_PCI_CREG_VIRT_BASE | (x))
 126 #define IXP2000_PCI_CMDSTAT             IXP2000_PCI_CREG(0x04)
 127 #define IXP2000_PCI_CSR_BAR             IXP2000_PCI_CREG(0x10)
 128 #define IXP2000_PCI_SRAM_BAR            IXP2000_PCI_CREG(0x14)
 129 #define IXP2000_PCI_SDRAM_BAR           IXP2000_PCI_CREG(0x18)
 130
 131 /*
 132  * PCI CSRs
 133  */
 134 #define IXP2000_PCI_CSR(x)              (volatile unsigned long*)(IXP2000_PCI_CSR_VIRT_BASE | (x))
 135
 136 /*
 137  * PCI outbound interrupts
 138  */
 139 #define IXP2000_PCI_OUT_INT_STATUS      IXP2000_PCI_CSR(0x30)
 140 #define IXP2000_PCI_OUT_INT_MASK        IXP2000_PCI_CSR(0x34)
 141 /*
 142  * PCI communications
 143  */
 144 #define IXP2000_PCI_MAILBOX0            IXP2000_PCI_CSR(0x50)
 145 #define IXP2000_PCI_MAILBOX1            IXP2000_PCI_CSR(0x54)
 146 #define IXP2000_PCI_MAILBOX2            IXP2000_PCI_CSR(0x58)
 147 #define IXP2000_PCI_MAILBOX3            IXP2000_PCI_CSR(0x5C)
 148 #define IXP2000_XSCALE_DOORBELL         IXP2000_PCI_CSR(0x60)
 149 #define IXP2000_XSCALE_DOORBELL_SETUP   IXP2000_PCI_CSR(0x64)
 150 #define IXP2000_PCI_DOORBELL            IXP2000_PCI_CSR(0x70)
 151 #define IXP2000_PCI_DOORBELL_SETUP      IXP2000_PCI_CSR(0x74)
 152
 153 /*
 154  * DMA engines
 155  */
 156 #define IXP2000_PCI_CH1_BYTE_CNT        IXP2000_PCI_CSR(0x80)
 157 #define IXP2000_PCI_CH1_ADDR            IXP2000_PCI_CSR(0x84)
 158 #define IXP2000_PCI_CH1_DRAM_ADDR       IXP2000_PCI_CSR(0x88)
 159 #define IXP2000_PCI_CH1_DESC_PTR        IXP2000_PCI_CSR(0x8C)
 160 #define IXP2000_PCI_CH1_CNTRL           IXP2000_PCI_CSR(0x90)
 161 #define IXP2000_PCI_CH1_ME_PARAM        IXP2000_PCI_CSR(0x94)
 162 #define IXP2000_PCI_CH2_BYTE_CNT        IXP2000_PCI_CSR(0xA0)
 163 #define IXP2000_PCI_CH2_ADDR            IXP2000_PCI_CSR(0xA4)
 164 #define IXP2000_PCI_CH2_DRAM_ADDR       IXP2000_PCI_CSR(0xA8)
 165 #define IXP2000_PCI_CH2_DESC_PTR        IXP2000_PCI_CSR(0xAC)
 166 #define IXP2000_PCI_CH2_CNTRL           IXP2000_PCI_CSR(0xB0)
 167 #define IXP2000_PCI_CH2_ME_PARAM        IXP2000_PCI_CSR(0xB4)
 168 #define IXP2000_PCI_CH3_BYTE_CNT        IXP2000_PCI_CSR(0xC0)
 169 #define IXP2000_PCI_CH3_ADDR            IXP2000_PCI_CSR(0xC4)
 170 #define IXP2000_PCI_CH3_DRAM_ADDR       IXP2000_PCI_CSR(0xC8)
 171 #define IXP2000_PCI_CH3_DESC_PTR        IXP2000_PCI_CSR(0xCC)
 172 #define IXP2000_PCI_CH3_CNTRL           IXP2000_PCI_CSR(0xD0)
 173 #define IXP2000_PCI_CH3_ME_PARAM        IXP2000_PCI_CSR(0xD4)
 174 #define IXP2000_DMA_INF_MODE            IXP2000_PCI_CSR(0xE0)
 175 /*
 176  * Size masks for BARs
 177  */
 178 #define IXP2000_PCI_SRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0xFC)
 179 #define IXP2000_PCI_DRAM_BASE_ADDR_MASK IXP2000_PCI_CSR(0x100)
 180 /*
 181  * Control and uEngine related
 182  */
 183 #define IXP2000_PCI_CONTROL             IXP2000_PCI_CSR(0x13C)
 184 #define IXP2000_PCI_ADDR_EXT            IXP2000_PCI_CSR(0x140)
 185 #define IXP2000_PCI_ME_PUSH_STATUS      IXP2000_PCI_CSR(0x148)
 186 #define IXP2000_PCI_ME_PUSH_EN          IXP2000_PCI_CSR(0x14C)
 187 #define IXP2000_PCI_ERR_STATUS          IXP2000_PCI_CSR(0x150)
 188 #define IXP2000_PCI_ERR_ENABLE          IXP2000_PCI_CSR(0x154)
 189 /*
 190  * Inbound PCI interrupt control
 191  */
 192 #define IXP2000_PCI_XSCALE_INT_STATUS   IXP2000_PCI_CSR(0x158)
 193 #define IXP2000_PCI_XSCALE_INT_ENABLE   IXP2000_PCI_CSR(0x15C)
 194
 195 #define IXP2000_PCICNTL_PNR             (1<<17) /* PCI not Reset bit of PCI_CONTROL */
 196 #define IXP2000_PCICNTL_PCF             (1<<28) /* PCI Centrolfunction bit */
 197 #define IXP2000_XSCALE_INT              (1<<1)  /* Interrupt from  XScale to PCI */
 198
 199 /* These are from the IRQ register in the PCI ISR register */
 200 #define PCI_CONTROL_BE_DEO              (1 << 22)       /* Big Endian Data Enable Out */
 201 #define PCI_CONTROL_BE_DEI              (1 << 21)       /* Big Endian Data Enable In  */
 202 #define PCI_CONTROL_BE_BEO              (1 << 20)       /* Big Endian Byte Enable Out */
 203 #define PCI_CONTROL_BE_BEI              (1 << 19)       /* Big Endian Byte Enable In  */
 204 #define PCI_CONTROL_PNR                 (1 << 17)       /* PCI Not Reset bit */
 205
 206 #define IXP2000_PCI_RST_REL             (1 << 2)
 207 #define CFG_RST_DIR                     (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
 208 #define CFG_PCI_BOOT_HOST               (1 << 2)
 209 #define CFG_BOOT_PROM                   (1 << 1)
 210
 211 /*
 212  * SlowPort CSRs
 213  *
 214  * The slowport is used to access things like flash, SONET framer control
 215  * ports, slave microprocessors, CPLDs, and others of chip memory mapped
 216  * peripherals.
 217  */
 218 #define SLOWPORT_CSR(x)         (volatile unsigned long*)(IXP2000_SLOWPORT_CSR_VIRT_BASE | (x))
 219
 220 #define IXP2000_SLOWPORT_CCR            SLOWPORT_CSR(0x00)
 221 #define IXP2000_SLOWPORT_WTC1           SLOWPORT_CSR(0x04)
 222 #define IXP2000_SLOWPORT_WTC2           SLOWPORT_CSR(0x08)
 223 #define IXP2000_SLOWPORT_RTC1           SLOWPORT_CSR(0x0c)
 224 #define IXP2000_SLOWPORT_RTC2           SLOWPORT_CSR(0x10)
 225 #define IXP2000_SLOWPORT_FSR            SLOWPORT_CSR(0x14)
 226 #define IXP2000_SLOWPORT_PCR            SLOWPORT_CSR(0x18)
 227 #define IXP2000_SLOWPORT_ADC            SLOWPORT_CSR(0x1C)
 228 #define IXP2000_SLOWPORT_FAC            SLOWPORT_CSR(0x20)
 229 #define IXP2000_SLOWPORT_FRM            SLOWPORT_CSR(0x24)
 230 #define IXP2000_SLOWPORT_FIN            SLOWPORT_CSR(0x28)
 231
 232 /*
 233  * CCR values.
 234  * The CCR configures the clock division for the slowport interface.
 235  */
 236 #define SLOWPORT_CCR_DIV_1              0x00
 237 #define SLOWPORT_CCR_DIV_2              0x01
 238 #define SLOWPORT_CCR_DIV_4              0x02
 239 #define SLOWPORT_CCR_DIV_6              0x03
 240 #define SLOWPORT_CCR_DIV_8              0x04
 241 #define SLOWPORT_CCR_DIV_10             0x05
 242 #define SLOWPORT_CCR_DIV_12             0x06
 243 #define SLOWPORT_CCR_DIV_14             0x07
 244 #define SLOWPORT_CCR_DIV_16             0x08
 245 #define SLOWPORT_CCR_DIV_18             0x09
 246 #define SLOWPORT_CCR_DIV_20             0x0a
 247 #define SLOWPORT_CCR_DIV_22             0x0b
 248 #define SLOWPORT_CCR_DIV_24             0x0c
 249 #define SLOWPORT_CCR_DIV_26             0x0d
 250 #define SLOWPORT_CCR_DIV_28             0x0e
 251 #define SLOWPORT_CCR_DIV_30             0x0f
 252
 253 /*
 254  * PCR values.  PCR configure the mode of the interfac3
 255  */
 256 #define SLOWPORT_MODE_FLASH             0x00
 257 #define SLOWPORT_MODE_LUCENT            0x01
 258 #define SLOWPORT_MODE_PMC_SIERRA        0x02
 259 #define SLOWPORT_MODE_INTEL_UP          0x03
 260 #define SLOWPORT_MODE_MOTOROLA_UP       0x04
 261
 262 /*
 263  * ADC values.  Defines data and address bus widths
 264  */
 265 #define SLOWPORT_ADDR_WIDTH_8           0x00
 266 #define SLOWPORT_ADDR_WIDTH_16          0x01
 267 #define SLOWPORT_ADDR_WIDTH_24          0x02
 268 #define SLOWPORT_ADDR_WIDTH_32          0x03
 269 #define SLOWPORT_DATA_WIDTH_8           0x00
 270 #define SLOWPORT_DATA_WIDTH_16          0x10
 271 #define SLOWPORT_DATA_WIDTH_24          0x20
 272 #define SLOWPORT_DATA_WIDTH_32          0x30
 273
 274 /*
 275  * Masks and shifts for various fields in the WTC and RTC registers
 276  */
 277 #define SLOWPORT_WRTC_MASK_HD           0x0003
 278 #define SLOWPORT_WRTC_MASK_SU           0x003c
 279 #define SLOWPORT_WRTC_MASK_PW           0x03c0
 280
 281 #define SLOWPORT_WRTC_SHIFT_HD          0x00
 282 #define SLOWPORT_WRTC_SHIFT_SU          0x02
 283 #define SLOWPORT_WRTC_SHFIT_PW          0x06
 284
 285
 286 /*
 287  * GPIO registers & GPIO interface
 288  */
 289 #define IXP2000_GPIO_REG(x)             ((volatile unsigned long*)(IXP2000_GPIO_VIRT_BASE+(x)))
 290 #define IXP2000_GPIO_PLR                IXP2000_GPIO_REG(0x00)
 291 #define IXP2000_GPIO_PDPR               IXP2000_GPIO_REG(0x04)
 292 #define IXP2000_GPIO_PDSR               IXP2000_GPIO_REG(0x08)
 293 #define IXP2000_GPIO_PDCR               IXP2000_GPIO_REG(0x0c)
 294 #define IXP2000_GPIO_POPR               IXP2000_GPIO_REG(0x10)
 295 #define IXP2000_GPIO_POSR               IXP2000_GPIO_REG(0x14)
 296 #define IXP2000_GPIO_POCR               IXP2000_GPIO_REG(0x18)
 297 #define IXP2000_GPIO_REDR               IXP2000_GPIO_REG(0x1c)
 298 #define IXP2000_GPIO_FEDR               IXP2000_GPIO_REG(0x20)
 299 #define IXP2000_GPIO_EDSR               IXP2000_GPIO_REG(0x24)
 300 #define IXP2000_GPIO_LSHR               IXP2000_GPIO_REG(0x28)
 301 #define IXP2000_GPIO_LSLR               IXP2000_GPIO_REG(0x2c)
 302 #define IXP2000_GPIO_LDSR               IXP2000_GPIO_REG(0x30)
 303 #define IXP2000_GPIO_INER               IXP2000_GPIO_REG(0x34)
 304 #define IXP2000_GPIO_INSR               IXP2000_GPIO_REG(0x38)
 305 #define IXP2000_GPIO_INCR               IXP2000_GPIO_REG(0x3c)
 306 #define IXP2000_GPIO_INST               IXP2000_GPIO_REG(0x40)
 307
 308 /*
 309  * "Global" registers...whatever that's supposed to mean.
 310  */
 311 #define GLOBAL_REG_BASE                 (IXP2000_GLOBAL_REG_VIRT_BASE + 0x0a00)
 312 #define GLOBAL_REG(x)                   (volatile unsigned long*)(GLOBAL_REG_BASE | (x))
 313
 314 #define IXP2000_PROD_ID                 GLOBAL_REG(0x00)
 315
 316 #define IXP2000_MAJ_PROD_TYPE_MASK      0x001F0000
 317 #define IXP2000_MAJ_PROD_TYPE_IXP2000   0x00000000
 318 #define IXP2000_MIN_PROD_TYPE_MASK      0x0000FF00
 319 #define IXP2000_MIN_PROD_TYPE_IXP2400   0x00000200
 320 #define IXP2000_MIN_PROD_TYPE_IXP2850   0x00000100
 321 #define IXP2000_MIN_PROD_TYPE_IXP2800   0x00000000
 322 #define IXP2000_MAJ_REV_MASK            0x000000F0
 323 #define IXP2000_MIN_REV_MASK            0x0000000F
 324 #define IXP2000_PROD_ID_MASK            0xFFFFFFFF
 325
 326 #define IXP2000_MISC_CONTROL            GLOBAL_REG(0x04)
 327 #define IXP2000_MSF_CLK_CNTRL           GLOBAL_REG(0x08)
 328 #define IXP2000_RESET0                  GLOBAL_REG(0x0c)
 329 #define IXP2000_RESET1                  GLOBAL_REG(0x10)
 330 #define IXP2000_CCR                     GLOBAL_REG(0x14)
 331 #define IXP2000_STRAP_OPTIONS           GLOBAL_REG(0x18)
 332
 333 #define RSTALL                          (1 << 16)
 334 #define WDT_RESET_ENABLE                0x01000000
 335
 336
 337 #endif                          /* _IXP2000_H_ */