include/asm-arm/arch-iop3xx/iop331.h

   1 /*
   2  * linux/include/asm/arch-iop3xx/iop331.h
   3  *
   4  * Intel IOP331 Chip definitions
   5  *
   6  * Author: Dave Jiang (dave.jiang@intel.com)
   7  * Copyright (C) 2003 Intel Corp.
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef _IOP331_HW_H_
  15 #define _IOP331_HW_H_
  16
  17
  18 /*
  19  * This is needed for mixed drivers that need to work on all
  20  * IOP3xx variants but behave slightly differently on each.
  21  */
  22 #ifndef __ASSEMBLY__
  23 #ifdef  CONFIG_ARCH_IOP331
  24 #define iop_is_331()    ((processor_id & 0xffffffb0) == 0x69054090)
  25 #else
  26 #define iop_is_331()    0
  27 #endif
  28 #endif
  29
  30 /*
  31  * IOP331 I/O and Mem space regions for PCI autoconfiguration
  32  */
  33 #define IOP331_PCI_LOWER_IO             0x90000000
  34 #define IOP331_PCI_UPPER_IO             0x900fffff
  35 #define IOP331_PCI_LOWER_MEM            0x80000000
  36 #define IOP331_PCI_UPPER_MEM            0x87ffffff
  37
  38 #define IOP331_PCI_WINDOW_SIZE          128 * 0x100000
  39
  40
  41 /*
  42  * IOP331 chipset registers
  43  */
  44 #define IOP331_VIRT_MEM_BASE 0xfeffe000  /* chip virtual mem address*/
  45 // #define IOP331_VIRT_MEM_BASE 0xfff00000  /* chip virtual mem address*/
  46
  47 #define IOP331_PHYS_MEM_BASE  0xffffe000  /* chip physical memory address */
  48 #define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
  49
  50 /* Reserved 0x00000000 through 0x000000FF */
  51
  52 /* Address Translation Unit 0x00000100 through 0x000001FF */
  53 #define IOP331_ATUVID     (volatile u16 *)IOP331_REG_ADDR(0x00000100)
  54 #define IOP331_ATUDID     (volatile u16 *)IOP331_REG_ADDR(0x00000102)
  55 #define IOP331_ATUCMD     (volatile u16 *)IOP331_REG_ADDR(0x00000104)
  56 #define IOP331_ATUSR      (volatile u16 *)IOP331_REG_ADDR(0x00000106)
  57 #define IOP331_ATURID     (volatile u8  *)IOP331_REG_ADDR(0x00000108)
  58 #define IOP331_ATUCCR     (volatile u32 *)IOP331_REG_ADDR(0x00000109)
  59 #define IOP331_ATUCLSR    (volatile u8  *)IOP331_REG_ADDR(0x0000010C)
  60 #define IOP331_ATULT      (volatile u8  *)IOP331_REG_ADDR(0x0000010D)
  61 #define IOP331_ATUHTR     (volatile u8  *)IOP331_REG_ADDR(0x0000010E)
  62 #define IOP331_ATUBIST    (volatile u8  *)IOP331_REG_ADDR(0x0000010F)
  63 #define IOP331_IABAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000110)
  64 #define IOP331_IAUBAR0    (volatile u32 *)IOP331_REG_ADDR(0x00000114)
  65 #define IOP331_IABAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000118)
  66 #define IOP331_IAUBAR1    (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
  67 #define IOP331_IABAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000120)
  68 #define IOP331_IAUBAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000124)
  69 #define IOP331_ASVIR      (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
  70 #define IOP331_ASIR       (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
  71 #define IOP331_ERBAR      (volatile u32 *)IOP331_REG_ADDR(0x00000130)
  72 #define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
  73 /* Reserved 0x00000138 through 0x0000013B */
  74 #define IOP331_ATUILR     (volatile u8  *)IOP331_REG_ADDR(0x0000013C)
  75 #define IOP331_ATUIPR     (volatile u8  *)IOP331_REG_ADDR(0x0000013D)
  76 #define IOP331_ATUMGNT    (volatile u8  *)IOP331_REG_ADDR(0x0000013E)
  77 #define IOP331_ATUMLAT    (volatile u8  *)IOP331_REG_ADDR(0x0000013F)
  78 #define IOP331_IALR0      (volatile u32 *)IOP331_REG_ADDR(0x00000140)
  79 #define IOP331_IATVR0     (volatile u32 *)IOP331_REG_ADDR(0x00000144)
  80 #define IOP331_ERLR       (volatile u32 *)IOP331_REG_ADDR(0x00000148)
  81 #define IOP331_ERTVR      (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
  82 #define IOP331_IALR1      (volatile u32 *)IOP331_REG_ADDR(0x00000150)
  83 #define IOP331_IALR2      (volatile u32 *)IOP331_REG_ADDR(0x00000154)
  84 #define IOP331_IATVR2     (volatile u32 *)IOP331_REG_ADDR(0x00000158)
  85 #define IOP331_OIOWTVR    (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
  86 #define IOP331_OMWTVR0    (volatile u32 *)IOP331_REG_ADDR(0x00000160)
  87 #define IOP331_OUMWTVR0   (volatile u32 *)IOP331_REG_ADDR(0x00000164)
  88 #define IOP331_OMWTVR1    (volatile u32 *)IOP331_REG_ADDR(0x00000168)
  89 #define IOP331_OUMWTVR1   (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
  90 /* Reserved 0x00000170 through 0x00000177*/
  91 #define IOP331_OUDWTVR    (volatile u32 *)IOP331_REG_ADDR(0x00000178)
  92 /* Reserved 0x0000017C through 0x0000017F*/
  93 #define IOP331_ATUCR      (volatile u32 *)IOP331_REG_ADDR(0x00000180)
  94 #define IOP331_PCSR       (volatile u32 *)IOP331_REG_ADDR(0x00000184)
  95 #define IOP331_ATUISR     (volatile u32 *)IOP331_REG_ADDR(0x00000188)
  96 #define IOP331_ATUIMR     (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
  97 #define IOP331_IABAR3     (volatile u32 *)IOP331_REG_ADDR(0x00000190)
  98 #define IOP331_IAUBAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000194)
  99 #define IOP331_IALR3      (volatile u32 *)IOP331_REG_ADDR(0x00000198)
 100 #define IOP331_IATVR3     (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
 101 /* Reserved 0x000001A0 through 0x000001A3*/
 102 #define IOP331_OCCAR      (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
 103 /* Reserved 0x000001A8 through 0x000001AB*/
 104 #define IOP331_OCCDR      (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
 105 /* Reserved 0x000001B0 through 0x000001BB*/
 106 #define IOP331_VPDCAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
 107 #define IOP331_VPDNXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
 108 #define IOP331_VPDAR      (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
 109 #define IOP331_VPDDR      (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
 110 #define IOP331_PMCAPID    (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
 111 #define IOP331_PMNEXT     (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
 112 #define IOP331_APMCR      (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
 113 #define IOP331_APMCSR     (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
 114 /* Reserved 0x000001C6 through 0x000001CF */
 115 #define IOP331_MSICAPID   (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
 116 #define IOP331_MSINXTP    (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
 117 #define IOP331_MSIMCR     (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
 118 #define IOP331_MSIMAR     (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
 119 #define IOP331_MSIMUAR    (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
 120 #define IOP331_MSIMDR     (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
 121 #define IOP331_PCIXCAPID  (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
 122 #define IOP331_PCIXNEXT   (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
 123 #define IOP331_PCIXCMD    (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
 124 #define IOP331_PCIXSR     (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
 125 #define IOP331_PCIIRSR    (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
 126
 127 /* Messaging Unit 0x00000300 through 0x000003FF */
 128
 129 /* Reserved 0x00000300 through 0x0000030c */
 130 #define IOP331_IMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000310)
 131 #define IOP331_IMR1       (volatile u32 *)IOP331_REG_ADDR(0x00000314)
 132 #define IOP331_OMR0       (volatile u32 *)IOP331_REG_ADDR(0x00000318)
 133 #define IOP331_OMR1       (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
 134 #define IOP331_IDR        (volatile u32 *)IOP331_REG_ADDR(0x00000320)
 135 #define IOP331_IISR       (volatile u32 *)IOP331_REG_ADDR(0x00000324)
 136 #define IOP331_IIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000328)
 137 #define IOP331_ODR        (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
 138 #define IOP331_OISR       (volatile u32 *)IOP331_REG_ADDR(0x00000330)
 139 #define IOP331_OIMR       (volatile u32 *)IOP331_REG_ADDR(0x00000334)
 140 /* Reserved 0x00000338 through 0x0000034F */
 141 #define IOP331_MUCR       (volatile u32 *)IOP331_REG_ADDR(0x00000350)
 142 #define IOP331_QBAR       (volatile u32 *)IOP331_REG_ADDR(0x00000354)
 143 /* Reserved 0x00000358 through 0x0000035C */
 144 #define IOP331_IFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000360)
 145 #define IOP331_IFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000364)
 146 #define IOP331_IPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000368)
 147 #define IOP331_IPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
 148 #define IOP331_OFHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000370)
 149 #define IOP331_OFTPR      (volatile u32 *)IOP331_REG_ADDR(0x00000374)
 150 #define IOP331_OPHPR      (volatile u32 *)IOP331_REG_ADDR(0x00000378)
 151 #define IOP331_OPTPR      (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
 152 #define IOP331_IAR        (volatile u32 *)IOP331_REG_ADDR(0x00000380)
 153 /* Reserved 0x00000384 through 0x000003FF */
 154
 155 /* DMA Controller 0x00000400 through 0x000004FF */
 156 #define IOP331_DMA0_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000400)
 157 #define IOP331_DMA0_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000404)
 158 #define IOP331_DMA0_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
 159 #define IOP331_DMA0_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000410)
 160 #define IOP331_DMA0_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000414)
 161 #define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
 162 #define IOP331_DMA0_LADR  (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
 163 #define IOP331_DMA0_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000420)
 164 #define IOP331_DMA0_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000424)
 165 /* Reserved 0x00000428 through 0x0000043C */
 166 #define IOP331_DMA1_CCR   (volatile u32 *)IOP331_REG_ADDR(0x00000440)
 167 #define IOP331_DMA1_CSR   (volatile u32 *)IOP331_REG_ADDR(0x00000444)
 168 #define IOP331_DMA1_DAR   (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
 169 #define IOP331_DMA1_NDAR  (volatile u32 *)IOP331_REG_ADDR(0x00000450)
 170 #define IOP331_DMA1_PADR  (volatile u32 *)IOP331_REG_ADDR(0x00000454)
 171 #define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
 172 #define IOP331_DMA1_LADR  (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
 173 #define IOP331_DMA1_BCR   (volatile u32 *)IOP331_REG_ADDR(0x00000460)
 174 #define IOP331_DMA1_DCR   (volatile u32 *)IOP331_REG_ADDR(0x00000464)
 175 /* Reserved 0x00000468 through 0x000004FF */
 176
 177 /* Memory controller 0x00000500 through 0x0005FF */
 178
 179 /* Peripheral bus interface unit 0x00000680 through 0x0006FF */
 180 #define IOP331_PBCR       (volatile u32 *)IOP331_REG_ADDR(0x00000680)
 181 #define IOP331_PBISR      (volatile u32 *)IOP331_REG_ADDR(0x00000684)
 182 #define IOP331_PBBAR0     (volatile u32 *)IOP331_REG_ADDR(0x00000688)
 183 #define IOP331_PBLR0      (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
 184 #define IOP331_PBBAR1     (volatile u32 *)IOP331_REG_ADDR(0x00000690)
 185 #define IOP331_PBLR1      (volatile u32 *)IOP331_REG_ADDR(0x00000694)
 186 #define IOP331_PBBAR2     (volatile u32 *)IOP331_REG_ADDR(0x00000698)
 187 #define IOP331_PBLR2      (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
 188 #define IOP331_PBBAR3     (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
 189 #define IOP331_PBLR3      (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
 190 #define IOP331_PBBAR4     (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
 191 #define IOP331_PBLR4      (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
 192 #define IOP331_PBBAR5     (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
 193 #define IOP331_PBLR5      (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
 194 #define IOP331_PBDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
 195 /* Reserved 0x000006BC */
 196 #define IOP331_PMBR0      (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
 197 /* Reserved 0x000006C4 through 0x000006DC */
 198 #define IOP331_PMBR1      (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
 199 #define IOP331_PMBR2      (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
 200
 201 #define IOP331_PBCR_EN    0x1
 202
 203 #define IOP331_PBISR_BOOR_ERR 0x1
 204
 205
 206
 207 /* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
 208 /* Internal arbitration unit 0x00000780 through 0x0007BF */
 209
 210 /* Interrupt Controller */
 211 #define IOP331_INTCTL0    (volatile u32 *)IOP331_REG_ADDR(0x00000790)
 212 #define IOP331_INTCTL1    (volatile u32 *)IOP331_REG_ADDR(0x00000794)
 213 #define IOP331_INTSTR0    (volatile u32 *)IOP331_REG_ADDR(0x00000798)
 214 #define IOP331_INTSTR1    (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
 215 #define IOP331_IINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
 216 #define IOP331_IINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
 217 #define IOP331_FINTSRC0   (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
 218 #define IOP331_FINTSRC1   (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
 219 #define IOP331_IPR0       (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
 220 #define IOP331_IPR1       (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
 221 #define IOP331_IPR2       (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
 222 #define IOP331_IPR3       (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
 223 #define IOP331_INTBASE    (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
 224 #define IOP331_INTSIZE    (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
 225 #define IOP331_IINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
 226 #define IOP331_FINTVEC    (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
 227
 228
 229 /* Timers */
 230
 231 #define IOP331_TU_TMR0          (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
 232 #define IOP331_TU_TMR1          (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
 233
 234 #define IOP331_TMR_TC           0x01
 235 #define IOP331_TMR_EN           0x02
 236 #define IOP331_TMR_RELOAD       0x04
 237 #define IOP331_TMR_PRIVILEGED   0x09
 238
 239 #define IOP331_TMR_RATIO_1_1    0x00
 240 #define IOP331_TMR_RATIO_4_1    0x10
 241 #define IOP331_TMR_RATIO_8_1    0x20
 242 #define IOP331_TMR_RATIO_16_1   0x30
 243
 244 #define IOP331_TU_TCR0    (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
 245 #define IOP331_TU_TCR1    (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
 246 #define IOP331_TU_TRR0    (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
 247 #define IOP331_TU_TRR1    (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
 248 #define IOP331_TU_TISR    (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
 249 #define IOP331_TU_WDTCR   (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
 250
 251 #define IOP331_TICK_RATE        266000000       /* 266 MHz clock */
 252
 253
 254 /* Application accelerator unit 0x00000800 - 0x000008FF */
 255 #define IOP331_AAU_ACR     (volatile u32 *)IOP331_REG_ADDR(0x00000800)
 256 #define IOP331_AAU_ASR     (volatile u32 *)IOP331_REG_ADDR(0x00000804)
 257 #define IOP331_AAU_ADAR    (volatile u32 *)IOP331_REG_ADDR(0x00000808)
 258 #define IOP331_AAU_ANDAR   (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
 259 #define IOP331_AAU_SAR1    (volatile u32 *)IOP331_REG_ADDR(0x00000810)
 260 #define IOP331_AAU_SAR2    (volatile u32 *)IOP331_REG_ADDR(0x00000814)
 261 #define IOP331_AAU_SAR3    (volatile u32 *)IOP331_REG_ADDR(0x00000818)
 262 #define IOP331_AAU_SAR4    (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
 263 #define IOP331_AAU_SAR5    (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
 264 #define IOP331_AAU_SAR6    (volatile u32 *)IOP331_REG_ADDR(0x00000830)
 265 #define IOP331_AAU_SAR7    (volatile u32 *)IOP331_REG_ADDR(0x00000834)
 266 #define IOP331_AAU_SAR8    (volatile u32 *)IOP331_REG_ADDR(0x00000838)
 267 #define IOP331_AAU_SAR9    (volatile u32 *)IOP331_REG_ADDR(0x00000840)
 268 #define IOP331_AAU_SAR10   (volatile u32 *)IOP331_REG_ADDR(0x00000844)
 269 #define IOP331_AAU_SAR11   (volatile u32 *)IOP331_REG_ADDR(0x00000848)
 270 #define IOP331_AAU_SAR12   (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
 271 #define IOP331_AAU_SAR13   (volatile u32 *)IOP331_REG_ADDR(0x00000850)
 272 #define IOP331_AAU_SAR14   (volatile u32 *)IOP331_REG_ADDR(0x00000854)
 273 #define IOP331_AAU_SAR15   (volatile u32 *)IOP331_REG_ADDR(0x00000858)
 274 #define IOP331_AAU_SAR16   (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
 275 #define IOP331_AAU_SAR17   (volatile u32 *)IOP331_REG_ADDR(0x00000864)
 276 #define IOP331_AAU_SAR18   (volatile u32 *)IOP331_REG_ADDR(0x00000868)
 277 #define IOP331_AAU_SAR19   (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
 278 #define IOP331_AAU_SAR20   (volatile u32 *)IOP331_REG_ADDR(0x00000870)
 279 #define IOP331_AAU_SAR21   (volatile u32 *)IOP331_REG_ADDR(0x00000874)
 280 #define IOP331_AAU_SAR22   (volatile u32 *)IOP331_REG_ADDR(0x00000878)
 281 #define IOP331_AAU_SAR23   (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
 282 #define IOP331_AAU_SAR24   (volatile u32 *)IOP331_REG_ADDR(0x00000880)
 283 #define IOP331_AAU_SAR25   (volatile u32 *)IOP331_REG_ADDR(0x00000888)
 284 #define IOP331_AAU_SAR26   (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
 285 #define IOP331_AAU_SAR27   (volatile u32 *)IOP331_REG_ADDR(0x00000890)
 286 #define IOP331_AAU_SAR28   (volatile u32 *)IOP331_REG_ADDR(0x00000894)
 287 #define IOP331_AAU_SAR29   (volatile u32 *)IOP331_REG_ADDR(0x00000898)
 288 #define IOP331_AAU_SAR30   (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
 289 #define IOP331_AAU_SAR31   (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
 290 #define IOP331_AAU_SAR32   (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
 291 #define IOP331_AAU_DAR     (volatile u32 *)IOP331_REG_ADDR(0x00000820)
 292 #define IOP331_AAU_ABCR    (volatile u32 *)IOP331_REG_ADDR(0x00000824)
 293 #define IOP331_AAU_ADCR    (volatile u32 *)IOP331_REG_ADDR(0x00000828)
 294 #define IOP331_AAU_EDCR0   (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
 295 #define IOP331_AAU_EDCR1   (volatile u32 *)IOP331_REG_ADDR(0x00000860)
 296 #define IOP331_AAU_EDCR2   (volatile u32 *)IOP331_REG_ADDR(0x00000884)
 297
 298
 299 #define IOP331_SPDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
 300 #define IOP331_PPDSCR     (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
 301 /* SSP serial port unit 0x00001600 - 0x0000167F */
 302
 303 /* I2C bus interface unit 0x00001680 - 0x000016FF */
 304 /* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
 305
 306 #define IOP331_ICR0       (volatile u32 *)IOP331_REG_ADDR(0x00001680)
 307 #define IOP331_ISR0       (volatile u32 *)IOP331_REG_ADDR(0x00001684)
 308 #define IOP331_ISAR0      (volatile u32 *)IOP331_REG_ADDR(0x00001688)
 309 #define IOP331_IDBR0      (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
 310 /* Reserved 0x00001690 */
 311 #define IOP331_IBMR0      (volatile u32 *)IOP331_REG_ADDR(0x00001694)
 312 /* Reserved 0x00001698 */
 313 /* Reserved 0x0000169C */
 314 #define IOP331_ICR1       (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
 315 #define IOP331_ISR1       (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
 316 #define IOP331_ISAR1      (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
 317 #define IOP331_IDBR1      (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
 318 #define IOP331_IBMR1      (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
 319 /* Reserved 0x000016B8 through 0x000016FF */
 320
 321 /* 0x00001700 through 0x0000172C  UART 0 */
 322
 323 /* Reserved 0x00001730 through 0x0000173F */
 324
 325 /* 0x00001740 through 0x0000176C UART 1 */
 326
 327 /* Reserved 0x00001770 through 0x0000177F */
 328
 329 /* General Purpose I/O Registers */
 330 #define IOP331_GPOE       (volatile u32 *)IOP331_REG_ADDR(0x00001780)
 331 #define IOP331_GPID       (volatile u32 *)IOP331_REG_ADDR(0x00001784)
 332 #define IOP331_GPOD       (volatile u32 *)IOP331_REG_ADDR(0x00001788)
 333
 334 /* Reserved 0x0000178c through 0x000019ff */
 335
 336 #ifndef __ASSEMBLY__
 337 extern void iop331_map_io(void);
 338 extern void iop331_init_irq(void);
 339 extern void iop331_time_init(void);
 340 #endif
 341
 342 #endif // _IOP331_HW_H_