include/asm-arm/arch-h720x/hardware.h

   1 /*
   2  * linux/include/asm-arm/arch-h720x/hardware.h
   3  *
   4  * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
   5  *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
   6  *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
   7  *
   8  * This file contains the hardware definitions of the h720x processors
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * Do not add implementations specific defines here. This files contains
  15  * only defines of the onchip peripherals. Add those defines to boards.h,
  16  * which is included by this file.
  17  */
  18
  19 #ifndef __ASM_ARCH_HARDWARE_H
  20 #define __ASM_ARCH_HARDWARE_H
  21
  22 #define IOCLK (3686400L)
  23
  24 /* Onchip peripherals */
  25
  26 #define IO_VIRT                 0xf0000000      /* IO peripherals */
  27 #define IO_PHYS                 0x80000000
  28 #define IO_SIZE                 0x00050000
  29
  30 #ifdef CONFIG_CPU_H7202
  31 #include "h7202-regs.h"
  32 #elif defined CONFIG_CPU_H7201
  33 #include "h7201-regs.h"
  34 #else
  35 #error machine definition mismatch
  36 #endif
  37
  38 /* Macro to access the CPU IO */
  39 #define CPU_IO(x) (*(volatile u32*)(x))
  40
  41 /* Macro to access general purpose regs (base, offset) */
  42 #define CPU_REG(x,y) CPU_IO(x+y)
  43
  44 /* Macro to access irq related regs */
  45 #define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
  46
  47 /* CPU registers */
  48 /* general purpose I/O */
  49 #define GPIO_VIRT(x)            (IO_VIRT + 0x23000 + ((x)<<5))
  50 #define GPIO_A_VIRT             (GPIO_VIRT(0))
  51 #define GPIO_B_VIRT             (GPIO_VIRT(1))
  52 #define GPIO_C_VIRT             (GPIO_VIRT(2))
  53 #define GPIO_D_VIRT             (GPIO_VIRT(3))
  54 #define GPIO_E_VIRT             (GPIO_VIRT(4))
  55 #define GPIO_AMULSEL            (GPIO_VIRT + 0xA4)
  56 /* Register offsets general purpose I/O */
  57 #define GPIO_DATA               0x00
  58 #define GPIO_DIR                0x04
  59 #define GPIO_MASK               0x08
  60 #define GPIO_STAT               0x0C
  61 #define GPIO_EDGE               0x10
  62 #define GPIO_CLR                0x14
  63 #define GPIO_POL                0x18
  64 #define GPIO_EN                 0x1C
  65
  66 /*interrupt controller */
  67 #define IRQC_VIRT               (IO_VIRT + 0x24000)
  68 /* register offset interrupt controller */
  69 #define IRQC_IER                0x00
  70 #define IRQC_ISR                0x04
  71
  72 /* timer unit */
  73 #define TIMER_VIRT              (IO_VIRT + 0x25000)
  74 /* Register offsets timer unit */
  75 #define TM0_PERIOD              0x00
  76 #define TM0_COUNT               0x08
  77 #define TM0_CTRL                0x10
  78 #define TM1_PERIOD              0x20
  79 #define TM1_COUNT               0x28
  80 #define TM1_CTRL                0x30
  81 #define TM2_PERIOD              0x40
  82 #define TM2_COUNT               0x48
  83 #define TM2_CTRL                0x50
  84 #define TIMER_TOPCTRL           0x60
  85 #define TIMER_TOPSTAT           0x64
  86 #define T64_COUNTL              0x80
  87 #define T64_COUNTH              0x84
  88 #define T64_CTRL                0x88
  89 #define T64_BASEL               0x94
  90 #define T64_BASEH               0x98
  91 /* Bitmaks timer unit TOPSTAT reg */
  92 #define TSTAT_T0INT             0x1
  93 #define TSTAT_T1INT             0x2
  94 #define TSTAT_T2INT             0x4
  95 #define TSTAT_T3INT             0x8
  96 /* Bit description of TMx_CTRL register */
  97 #define TM_START                0x1
  98 #define TM_REPEAT               0x2
  99 #define TM_RESET                0x4
 100 /* Bit description of TIMER_CTRL register */
 101 #define ENABLE_TM0_INTR         0x1
 102 #define ENABLE_TM1_INTR         0x2
 103 #define ENABLE_TM2_INTR         0x4
 104 #define TIMER_ENABLE_BIT        0x8
 105 #define ENABLE_TIMER64          0x10
 106 #define ENABLE_TIMER64_INT      0x20
 107
 108 /* PMU & PLL */
 109 #define PMU_BASE                (IO_VIRT + 0x1000)
 110 #define PMU_MODE                0x00
 111 #define PMU_STAT                0x20
 112 #define PMU_PLL_CTRL            0x28
 113
 114 /* PMU Mode bits */
 115 #define PMU_MODE_SLOW           0x00
 116 #define PMU_MODE_RUN            0x01
 117 #define PMU_MODE_IDLE           0x02
 118 #define PMU_MODE_SLEEP          0x03
 119 #define PMU_MODE_INIT           0x04
 120 #define PMU_MODE_DEEPSLEEP      0x07
 121 #define PMU_MODE_WAKEUP         0x08
 122
 123 /* PMU ... */
 124 #define PLL_2_EN                0x8000
 125 #define PLL_1_EN                0x4000
 126 #define PLL_3_MUTE              0x0080
 127
 128 /* Control bits for PMU/ PLL */
 129 #define PMU_WARMRESET           0x00010000
 130 #define PLL_CTRL_MASK23         0x000080ff
 131
 132 /* LCD Controller */
 133 #define LCD_BASE                (IO_VIRT + 0x10000)
 134 #define LCD_CTRL                0x00
 135 #define LCD_STATUS              0x04
 136 #define LCD_STATUS_M            0x08
 137 #define LCD_INTERRUPT           0x0C
 138 #define LCD_DBAR                0x10
 139 #define LCD_DCAR                0x14
 140 #define LCD_TIMING0             0x20
 141 #define LCD_TIMING1             0x24
 142 #define LCD_TIMING2             0x28
 143 #define LCD_TEST                0x40
 144
 145 /* LCD Control Bits */
 146 #define LCD_CTRL_LCD_ENABLE     0x00000001
 147 /* Bits per pixel */
 148 #define LCD_CTRL_LCD_BPP_MASK   0x00000006
 149 #define LCD_CTRL_LCD_4BPP       0x00000000
 150 #define LCD_CTRL_LCD_8BPP       0x00000002
 151 #define LCD_CTRL_LCD_16BPP      0x00000004
 152 #define LCD_CTRL_LCD_BW         0x00000008
 153 #define LCD_CTRL_LCD_TFT        0x00000010
 154 #define LCD_CTRL_BGR            0x00001000
 155 #define LCD_CTRL_LCD_VCOMP      0x00080000
 156 #define LCD_CTRL_LCD_MONO8      0x00200000
 157 #define LCD_CTRL_LCD_PWR        0x00400000
 158 #define LCD_CTRL_LCD_BLE        0x00800000
 159 #define LCD_CTRL_LDBUSEN        0x01000000
 160
 161 /* Palette */
 162 #define LCD_PALETTE_BASE        (IO_VIRT + 0x10400)
 163
 164 /* Serial ports */
 165 #define SERIAL0_VIRT            (IO_VIRT + 0x20000)
 166 #define SERIAL1_VIRT            (IO_VIRT + 0x21000)
 167
 168 #define SERIAL0_BASE            SERIAL0_VIRT
 169 #define SERIAL1_BASE            SERIAL1_VIRT
 170 #define SERIAL2_BASE            SERIAL2_VIRT
 171 #define SERIAL3_BASE            SERIAL3_VIRT
 172
 173
 174 /* General defines to pacify gcc */
 175 #define PCIO_BASE               (0)     /* for inb, outb and friends */
 176 #define PCIO_VIRT               PCIO_BASE
 177
 178 #define __ASM_ARCH_HARDWARE_INCMACH_H
 179 #include "boards.h"
 180 #undef __ASM_ARCH_HARDWARE_INCMACH_H
 181
 182 #endif                          /* __ASM_ARCH_HARDWARE_H */