drivers/video/sis/sis.h

   1 /*
   2  * SiS 300/630/730/540/315/550/650/651/M650/661FX/M661FX/740/741/330/760
   3  * frame buffer driver for Linux kernels >=2.4.14 and >=2.6.3
   4  *
   5  * Copyright (C) 2001-2004 Thomas Winischhofer, Vienna, Austria.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the named License,
  10  * or any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA
  20  */
  21
  22 #ifndef _SIS_H
  23 #define _SIS_H
  24
  25 #include <linux/config.h>
  26 #include <linux/version.h>
  27
  28 #include "osdef.h"
  29 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
  30 #include <video/sisfb.h>
  31 #else
  32 #include <linux/sisfb.h>
  33 #endif
  34
  35 #include "vgatypes.h"
  36 #include "vstruct.h"
  37
  38 #define VER_MAJOR                 1
  39 #define VER_MINOR                 7
  40 #define VER_LEVEL                 12
  41
  42 #undef SIS_CONFIG_COMPAT
  43
  44 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
  45 #include <linux/spinlock.h>
  46 #ifdef CONFIG_COMPAT
  47 #include <linux/ioctl32.h>
  48 #define SIS_CONFIG_COMPAT
  49 #endif
  50 #elif LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,19)
  51 #ifdef __x86_64__
  52 /* Shouldn't we check for CONFIG_IA32_EMULATION here? */
  53 #include <asm/ioctl32.h>
  54 #define SIS_CONFIG_COMPAT
  55 #endif
  56 #endif
  57
  58 #undef SISFBDEBUG
  59
  60 #ifdef SISFBDEBUG
  61 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  62 #define TWDEBUG(x) printk(KERN_INFO x "\n");
  63 #else
  64 #define DPRINTK(fmt, args...)
  65 #define TWDEBUG(x)
  66 #endif
  67
  68 #define SISFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
  69
  70 /* To be included in pci_ids.h */
  71 #ifndef PCI_DEVICE_ID_SI_650_VGA
  72 #define PCI_DEVICE_ID_SI_650_VGA  0x6325
  73 #endif
  74 #ifndef PCI_DEVICE_ID_SI_650
  75 #define PCI_DEVICE_ID_SI_650      0x0650
  76 #endif
  77 #ifndef PCI_DEVICE_ID_SI_651
  78 #define PCI_DEVICE_ID_SI_651      0x0651
  79 #endif
  80 #ifndef PCI_DEVICE_ID_SI_740
  81 #define PCI_DEVICE_ID_SI_740      0x0740
  82 #endif
  83 #ifndef PCI_DEVICE_ID_SI_330
  84 #define PCI_DEVICE_ID_SI_330      0x0330
  85 #endif
  86 #ifndef PCI_DEVICE_ID_SI_660_VGA
  87 #define PCI_DEVICE_ID_SI_660_VGA  0x6330
  88 #endif
  89 #ifndef PCI_DEVICE_ID_SI_661
  90 #define PCI_DEVICE_ID_SI_661      0x0661
  91 #endif
  92 #ifndef PCI_DEVICE_ID_SI_741
  93 #define PCI_DEVICE_ID_SI_741      0x0741
  94 #endif
  95 #ifndef PCI_DEVICE_ID_SI_660
  96 #define PCI_DEVICE_ID_SI_660      0x0660
  97 #endif
  98 #ifndef PCI_DEVICE_ID_SI_760
  99 #define PCI_DEVICE_ID_SI_760      0x0760
 100 #endif
 101
 102 /* To be included in fb.h */
 103 #ifndef FB_ACCEL_SIS_GLAMOUR_2
 104 #define FB_ACCEL_SIS_GLAMOUR_2    40    /* SiS 315, 65x, 740, 661, 741  */
 105 #endif
 106 #ifndef FB_ACCEL_SIS_XABRE
 107 #define FB_ACCEL_SIS_XABRE        41    /* SiS 330 ("Xabre"), 760       */
 108 #endif
 109
 110 #define MAX_ROM_SCAN              0x10000
 111
 112 /* ivideo->caps */
 113 #define HW_CURSOR_CAP             0x80
 114 #define TURBO_QUEUE_CAP           0x40
 115 #define AGP_CMD_QUEUE_CAP         0x20
 116 #define VM_CMD_QUEUE_CAP          0x10
 117 #define MMIO_CMD_QUEUE_CAP        0x08
 118
 119 /* For 300 series */
 120 #define TURBO_QUEUE_AREA_SIZE     0x80000 /* 512K */
 121 #define HW_CURSOR_AREA_SIZE_300   0x1000  /* 4K */
 122
 123 /* For 315/Xabre series */
 124 #define COMMAND_QUEUE_AREA_SIZE   0x80000 /* 512K */
 125 #define COMMAND_QUEUE_THRESHOLD   0x1F
 126 #define HW_CURSOR_AREA_SIZE_315   0x4000  /* 16K */
 127
 128 #define SIS_OH_ALLOC_SIZE         4000
 129 #define SENTINEL                  0x7fffffff
 130
 131 #define SEQ_ADR                   0x14
 132 #define SEQ_DATA                  0x15
 133 #define DAC_ADR                   0x18
 134 #define DAC_DATA                  0x19
 135 #define CRTC_ADR                  0x24
 136 #define CRTC_DATA                 0x25
 137 #define DAC2_ADR                  (0x16-0x30)
 138 #define DAC2_DATA                 (0x17-0x30)
 139 #define VB_PART1_ADR              (0x04-0x30)
 140 #define VB_PART1_DATA             (0x05-0x30)
 141 #define VB_PART2_ADR              (0x10-0x30)
 142 #define VB_PART2_DATA             (0x11-0x30)
 143 #define VB_PART3_ADR              (0x12-0x30)
 144 #define VB_PART3_DATA             (0x13-0x30)
 145 #define VB_PART4_ADR              (0x14-0x30)
 146 #define VB_PART4_DATA             (0x15-0x30)
 147
 148 #define SISSR                     ivideo->SiS_Pr.SiS_P3c4
 149 #define SISCR                     ivideo->SiS_Pr.SiS_P3d4
 150 #define SISDACA                   ivideo->SiS_Pr.SiS_P3c8
 151 #define SISDACD                   ivideo->SiS_Pr.SiS_P3c9
 152 #define SISPART1                  ivideo->SiS_Pr.SiS_Part1Port
 153 #define SISPART2                  ivideo->SiS_Pr.SiS_Part2Port
 154 #define SISPART3                  ivideo->SiS_Pr.SiS_Part3Port
 155 #define SISPART4                  ivideo->SiS_Pr.SiS_Part4Port
 156 #define SISPART5                  ivideo->SiS_Pr.SiS_Part5Port
 157 #define SISDAC2A                  SISPART5
 158 #define SISDAC2D                  (SISPART5 + 1)
 159 #define SISMISCR                  (ivideo->SiS_Pr.RelIO + 0x1c)
 160 #define SISMISCW                  ivideo->SiS_Pr.SiS_P3c2
 161 #define SISINPSTAT                (ivideo->SiS_Pr.RelIO + 0x2a)
 162 #define SISPEL                    ivideo->SiS_Pr.SiS_P3c6
 163
 164 #define IND_SIS_PASSWORD          0x05  /* SRs */
 165 #define IND_SIS_COLOR_MODE        0x06
 166 #define IND_SIS_RAMDAC_CONTROL    0x07
 167 #define IND_SIS_DRAM_SIZE         0x14
 168 #define IND_SIS_MODULE_ENABLE     0x1E
 169 #define IND_SIS_PCI_ADDRESS_SET   0x20
 170 #define IND_SIS_TURBOQUEUE_ADR    0x26
 171 #define IND_SIS_TURBOQUEUE_SET    0x27
 172 #define IND_SIS_POWER_ON_TRAP     0x38
 173 #define IND_SIS_POWER_ON_TRAP2    0x39
 174 #define IND_SIS_CMDQUEUE_SET      0x26
 175 #define IND_SIS_CMDQUEUE_THRESHOLD  0x27
 176
 177 #define IND_SIS_AGP_IO_PAD        0x48
 178
 179 #define SIS_CRT2_WENABLE_300      0x24  /* Part1 */
 180 #define SIS_CRT2_WENABLE_315      0x2F
 181
 182 #define SIS_PASSWORD              0x86  /* SR05 */
 183 #define SIS_INTERLACED_MODE       0x20  /* SR06 */
 184 #define SIS_8BPP_COLOR_MODE       0x0
 185 #define SIS_15BPP_COLOR_MODE      0x1
 186 #define SIS_16BPP_COLOR_MODE      0x2
 187 #define SIS_32BPP_COLOR_MODE      0x4
 188
 189 #define SIS_ENABLE_2D             0x40  /* SR1E */
 190
 191 #define SIS_MEM_MAP_IO_ENABLE     0x01  /* SR20 */
 192 #define SIS_PCI_ADDR_ENABLE       0x80
 193
 194 #define SIS_AGP_CMDQUEUE_ENABLE   0x80  /* 315/330 series SR26 */
 195 #define SIS_VRAM_CMDQUEUE_ENABLE  0x40
 196 #define SIS_MMIO_CMD_ENABLE       0x20
 197 #define SIS_CMD_QUEUE_SIZE_512k   0x00
 198 #define SIS_CMD_QUEUE_SIZE_1M     0x04
 199 #define SIS_CMD_QUEUE_SIZE_2M     0x08
 200 #define SIS_CMD_QUEUE_SIZE_4M     0x0C
 201 #define SIS_CMD_QUEUE_RESET       0x01
 202 #define SIS_CMD_AUTO_CORR         0x02
 203
 204 #define SIS_SIMULTANEOUS_VIEW_ENABLE  0x01  /* CR30 */
 205 #define SIS_MODE_SELECT_CRT2      0x02
 206 #define SIS_VB_OUTPUT_COMPOSITE   0x04
 207 #define SIS_VB_OUTPUT_SVIDEO      0x08
 208 #define SIS_VB_OUTPUT_SCART       0x10
 209 #define SIS_VB_OUTPUT_LCD         0x20
 210 #define SIS_VB_OUTPUT_CRT2        0x40
 211 #define SIS_VB_OUTPUT_HIVISION    0x80
 212
 213 #define SIS_VB_OUTPUT_DISABLE     0x20  /* CR31 */
 214 #define SIS_DRIVER_MODE           0x40
 215
 216 #define SIS_VB_COMPOSITE          0x01  /* CR32 */
 217 #define SIS_VB_SVIDEO             0x02
 218 #define SIS_VB_SCART              0x04
 219 #define SIS_VB_LCD                0x08
 220 #define SIS_VB_CRT2               0x10
 221 #define SIS_CRT1                  0x20
 222 #define SIS_VB_HIVISION           0x40
 223 #define SIS_VB_YPBPR              0x80
 224 #define SIS_VB_TV                 (SIS_VB_COMPOSITE | SIS_VB_SVIDEO | \
 225                                    SIS_VB_SCART | SIS_VB_HIVISION | SIS_VB_YPBPR)
 226
 227 #define SIS_EXTERNAL_CHIP_MASK             0x0E  /* CR37 (< SiS 660) */
 228 #define SIS_EXTERNAL_CHIP_SIS301           0x01  /* in CR37 << 1 ! */
 229 #define SIS_EXTERNAL_CHIP_LVDS             0x02
 230 #define SIS_EXTERNAL_CHIP_TRUMPION         0x03
 231 #define SIS_EXTERNAL_CHIP_LVDS_CHRONTEL    0x04
 232 #define SIS_EXTERNAL_CHIP_CHRONTEL         0x05
 233 #define SIS310_EXTERNAL_CHIP_LVDS          0x02
 234 #define SIS310_EXTERNAL_CHIP_LVDS_CHRONTEL 0x03
 235
 236 #define SIS_AGP_2X                0x20  /* CR48 */
 237
 238 #define HW_DEVICE_EXTENSION       SIS_HW_INFO
 239 #define PHW_DEVICE_EXTENSION      PSIS_HW_INFO
 240
 241 /* Useful macros */
 242 #define inSISREG(base)          inb(base)
 243 #define outSISREG(base,val)     outb(val,base)
 244 #define orSISREG(base,val)      do { \
 245                                   u8 __Temp = inb(base); \
 246                                   outSISREG(base, __Temp | (val)); \
 247                                 } while (0)
 248 #define andSISREG(base,val)     do { \
 249                                   u8 __Temp = inb(base); \
 250                                   outSISREG(base, __Temp & (val)); \
 251                                 } while (0)
 252 #define inSISIDXREG(base,idx,var)   do { \
 253                                       outb(idx,base); var=inb((base)+1); \
 254                                     } while (0)
 255 #define outSISIDXREG(base,idx,val)  do { \
 256                                       outb(idx,base); outb((val),(base)+1); \
 257                                     } while (0)
 258 #define orSISIDXREG(base,idx,val)   do { \
 259                                       u8 __Temp; \
 260                                       outb(idx,base);   \
 261                                       __Temp = inb((base)+1)|(val); \
 262                                       outSISIDXREG(base,idx,__Temp); \
 263                                     } while (0)
 264 #define andSISIDXREG(base,idx,and)  do { \
 265                                       u8 __Temp; \
 266                                       outb(idx,base);   \
 267                                       __Temp = inb((base)+1)&(and); \
 268                                       outSISIDXREG(base,idx,__Temp); \
 269                                     } while (0)
 270 #define setSISIDXREG(base,idx,and,or)   do { \
 271                                           u8 __Temp; \
 272                                           outb(idx,base);   \
 273                                           __Temp = (inb((base)+1)&(and))|(or); \
 274                                           outSISIDXREG(base,idx,__Temp); \
 275                                         } while (0)
 276
 277 /* MMIO access macros */
 278 #define MMIO_IN8(base, offset)  readb((base+offset))
 279 #define MMIO_IN16(base, offset) readw((base+offset))
 280 #define MMIO_IN32(base, offset) readl((base+offset))
 281
 282 #define MMIO_OUT8(base, offset, val)  writeb(((u8)(val)), (base+offset))
 283 #define MMIO_OUT16(base, offset, val) writew(((u16)(val)), (base+offset))
 284 #define MMIO_OUT32(base, offset, val) writel(((u32)(val)), (base+offset))
 285
 286 /* Queue control MMIO registers */
 287 #define Q_BASE_ADDR             0x85C0  /* Base address of software queue */
 288 #define Q_WRITE_PTR             0x85C4  /* Current write pointer */
 289 #define Q_READ_PTR              0x85C8  /* Current read pointer */
 290 #define Q_STATUS                0x85CC  /* queue status */
 291
 292 #define MMIO_QUEUE_PHYBASE      Q_BASE_ADDR
 293 #define MMIO_QUEUE_WRITEPORT    Q_WRITE_PTR
 294 #define MMIO_QUEUE_READPORT     Q_READ_PTR
 295
 296 enum _SIS_CMDTYPE {
 297         MMIO_CMD = 0,
 298         AGP_CMD_QUEUE,
 299         VM_CMD_QUEUE,
 300 };
 301 typedef unsigned int SIS_CMDTYPE;
 302
 303 /* Our "par" */
 304 struct sis_video_info {
 305         int             cardnumber;
 306         struct fb_info  *memyselfandi;
 307
 308         SIS_HW_INFO     sishw_ext;
 309         SiS_Private     SiS_Pr;
 310
 311         sisfb_info      sisfbinfo;      /* For ioctl SISFB_GET_INFO */
 312
 313         struct fb_var_screeninfo default_var;
 314
 315 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
 316         struct fb_fix_screeninfo sisfb_fix;
 317         u32             pseudo_palette[17];
 318 #endif
 319
 320 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 321         struct display           sis_disp;
 322         struct display_switch    sisfb_sw;
 323         struct {
 324                 u16 red, green, blue, pad;
 325         }               sis_palette[256];
 326         union {
 327 #ifdef FBCON_HAS_CFB16
 328                 u16 cfb16[16];
 329 #endif
 330 #ifdef FBCON_HAS_CFB32
 331                 u32 cfb32[16];
 332 #endif
 333         }               sis_fbcon_cmap;
 334 #endif
 335
 336         struct sisfb_monitor {
 337                 u16 hmin;
 338                 u16 hmax;
 339                 u16 vmin;
 340                 u16 vmax;
 341                 u32 dclockmax;
 342                 u8  feature;
 343                 BOOLEAN datavalid;
 344         }               sisfb_thismonitor;
 345
 346         int             chip_id;
 347         char            myid[40];
 348
 349         struct pci_dev  *nbridge;
 350
 351         int             mni;    /* Mode number index */
 352
 353 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 354         int             currcon;
 355 #endif
 356
 357         unsigned long   video_size;
 358         unsigned long   video_base;
 359         unsigned long   mmio_size;
 360         unsigned long   mmio_base;
 361         unsigned long   vga_base;
 362
 363         void __iomem *  video_vbase;
 364         void __iomem *  mmio_vbase;
 365         void __iomem *  bios_vbase;
 366         void *          bios_abase;
 367
 368         int             mtrr;
 369
 370         u32             sisfb_mem;
 371
 372         u32             sisfb_parm_mem;
 373         int             sisfb_accel;
 374         int             sisfb_ypan;
 375         int             sisfb_max;
 376         int             sisfb_userom;
 377         int             sisfb_useoem;
 378         int             sisfb_mode_idx;
 379         int             sisfb_parm_rate;
 380         int             sisfb_crt1off;
 381         int             sisfb_forcecrt1;
 382         int             sisfb_crt2type;
 383         int             sisfb_crt2flags;
 384         int             sisfb_dstn;
 385         int             sisfb_fstn;
 386         int             sisfb_tvplug;
 387         int             sisfb_tvstd;
 388         int             sisfb_filter;
 389         int             sisfb_nocrt2rate;
 390 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
 391         int             sisfb_inverse;
 392 #endif
 393
 394         u32             heapstart;        /* offset  */
 395         void __iomem *  sisfb_heap_start; /* address */
 396         void __iomem *  sisfb_heap_end;   /* address */
 397         u32             sisfb_heap_size;
 398         int             havenoheap;
 399 #if 0
 400         SIS_HEAP        sisfb_heap;
 401 #endif
 402
 403
 404         int             video_bpp;
 405         int             video_cmap_len;
 406         int             video_width;
 407         int             video_height;
 408         unsigned int    refresh_rate;
 409
 410         unsigned int    chip;
 411         u8              revision_id;
 412
 413         int             video_linelength;       /* real pitch */
 414         int             scrnpitchCRT1;          /* pitch regarding interlace */
 415
 416         u16             DstColor;               /* For 2d acceleration */
 417         u32             SiS310_AccelDepth;
 418         u32             CommandReg;
 419         int             cmdqueuelength;
 420
 421         spinlock_t      lockaccel;              /* Do not use outside of kernel! */
 422
 423         unsigned int    pcibus;
 424         unsigned int    pcislot;
 425         unsigned int    pcifunc;
 426
 427         int             accel;
 428
 429         u16             subsysvendor;
 430         u16             subsysdevice;
 431
 432         u32             vbflags;                /* Replacing deprecated stuff from above */
 433         u32             currentvbflags;
 434
 435         int             lcdxres, lcdyres;
 436         int             lcddefmodeidx, tvdefmodeidx, defmodeidx;
 437
 438         int             current_bpp;
 439         int             current_width;
 440         int             current_height;
 441         int             current_htotal;
 442         int             current_vtotal;
 443         int             current_linelength;
 444         __u32           current_pixclock;
 445         int             current_refresh_rate;
 446
 447         u8              mode_no;
 448         u8              rate_idx;
 449         int             modechanged;
 450         unsigned char   modeprechange;
 451
 452 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
 453         u8              sisfb_lastrates[128];
 454 #endif
 455
 456         int             newrom;
 457         int             registered;
 458 #ifdef SIS_CONFIG_COMPAT
 459         int             ioctl32registered;
 460         int             ioctl32vblankregistered;
 461 #endif
 462
 463         int             sisvga_engine;
 464         int             hwcursor_size;
 465         int             CRT2_write_enable;
 466         u8              caps;
 467
 468         u8              detectedpdc;
 469         u8              detectedpdca;
 470         u8              detectedlcda;
 471
 472         void __iomem *  hwcursor_vbase;
 473
 474         int             chronteltype;
 475         int             tvxpos, tvypos;
 476         u8              p2_1f,p2_20,p2_2b,p2_42,p2_43,p2_01,p2_02;
 477         int             tvx, tvy;
 478
 479         u8              sisfblocked;
 480
 481         struct sis_video_info *next;
 482 };
 483
 484 typedef struct _SIS_OH {
 485         struct _SIS_OH *poh_next;
 486         struct _SIS_OH *poh_prev;
 487         u32            offset;
 488         u32            size;
 489 } SIS_OH;
 490
 491 typedef struct _SIS_OHALLOC {
 492         struct _SIS_OHALLOC *poha_next;
 493         SIS_OH aoh[1];
 494 } SIS_OHALLOC;
 495
 496 typedef struct _SIS_HEAP {
 497         SIS_OH      oh_free;
 498         SIS_OH      oh_used;
 499         SIS_OH      *poh_freelist;
 500         SIS_OHALLOC *poha_chain;
 501         u32         max_freesize;
 502         struct sis_video_info *vinfo;
 503 } SIS_HEAP;
 504
 505 #endif