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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / video / radeonfb.c
blobeedb2b8e93a51fa6018c4888e1f11c79aff0fb26
1 /*
2 * drivers/video/radeonfb.c
3 * framebuffer driver for ATI Radeon chipset video boards
4 *
5 * Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
6 *
7 *
8 * ChangeLog:
9 * 2000-08-03 initial version 0.0.1
10 * 2000-09-10 more bug fixes, public release 0.0.5
11 * 2001-02-19 mode bug fixes, 0.0.7
12 * 2001-07-05 fixed scrolling issues, engine initialization,
13 * and minor mode tweaking, 0.0.9
14 * 2001-09-07 Radeon VE support, Nick Kurshev
15 * blanking, pan_display, and cmap fixes, 0.1.0
16 * 2001-10-10 Radeon 7500 and 8500 support, and experimental
17 * flat panel support, 0.1.1
18 * 2001-11-17 Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
19 * 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
20 * 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
21 * 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
22 * 2002-06-02 console switching, mode set fixes, accel fixes
23 * 2002-06-03 MTRR support, Peter Horton, 0.1.5
24 * 2002-09-21 rv250, r300, m9 initial support,
25 * added mirror option, 0.1.6
26 *
27 * Special thanks to ATI DevRel team for their hardware donations.
28 *
29 */
30
31
32 #define RADEON_VERSION "0.1.6"
33
34
35 #include <linux/config.h>
36 #include <linux/module.h>
37 #include <linux/kernel.h>
38 #include <linux/errno.h>
39 #include <linux/string.h>
40 #include <linux/mm.h>
41 #include <linux/tty.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
44 #include <linux/fb.h>
45 #include <linux/ioport.h>
46 #include <linux/init.h>
47 #include <linux/pci.h>
48 #include <linux/vmalloc.h>
49
50 #include <asm/io.h>
51 #include <asm/uaccess.h>
52 #if defined(__powerpc__)
53 #include <asm/prom.h>
54 #include <asm/pci-bridge.h>
55 #include "macmodes.h"
56
57 #ifdef CONFIG_NVRAM
58 #include <linux/nvram.h>
59 #endif
60
61 #ifdef CONFIG_PMAC_BACKLIGHT
62 #include <asm/backlight.h>
63 #endif
64
65 #ifdef CONFIG_BOOTX_TEXT
66 #include <asm/btext.h>
67 #endif
68
69 #ifdef CONFIG_ADB_PMU
70 #include <linux/adb.h>
71 #include <linux/pmu.h>
72 #endif
73
74 #endif /* __powerpc__ */
75
76 #ifdef CONFIG_MTRR
77 #include <asm/mtrr.h>
78 #endif
79
80 #include <video/radeon.h>
81 #include <linux/radeonfb.h>
82
83 #define DEBUG 1
84
85 #if DEBUG
86 #define RTRACE printk
87 #else
88 #define RTRACE if(0) printk
89 #endif
90
91 // XXX
92 #undef CONFIG_PMAC_PBOOK
93
94
95 enum radeon_chips {
96 RADEON_QD,
97 RADEON_QE,
98 RADEON_QF,
99 RADEON_QG,
100 RADEON_QY,
101 RADEON_QZ,
102 RADEON_LW,
103 RADEON_LX,
104 RADEON_LY,
105 RADEON_LZ,
106 RADEON_QL,
107 RADEON_QN,
108 RADEON_QO,
109 RADEON_Ql,
110 RADEON_BB,
111 RADEON_QW,
112 RADEON_QX,
113 RADEON_Id,
114 RADEON_Ie,
115 RADEON_If,
116 RADEON_Ig,
117 RADEON_Ya,
118 RADEON_Yd,
119 RADEON_Ld,
120 RADEON_Le,
121 RADEON_Lf,
122 RADEON_Lg,
123 RADEON_ND,
124 RADEON_NE,
125 RADEON_NF,
126 RADEON_NG,
127 RADEON_QM
128 };
129
130 enum radeon_arch {
131 RADEON_R100,
132 RADEON_RV100,
133 RADEON_R200,
134 RADEON_RV200,
135 RADEON_RV250,
136 RADEON_R300,
137 RADEON_M6,
138 RADEON_M7,
139 RADEON_M9
140 };
141
142 static struct radeon_chip_info {
143 const char *name;
144 unsigned char arch;
145 } radeon_chip_info[] __devinitdata = {
146 { "QD", RADEON_R100 },
147 { "QE", RADEON_R100 },
148 { "QF", RADEON_R100 },
149 { "QG", RADEON_R100 },
150 { "VE QY", RADEON_RV100 },
151 { "VE QZ", RADEON_RV100 },
152 { "M7 LW", RADEON_M7 },
153 { "M7 LX", RADEON_M7 },
154 { "M6 LY", RADEON_M6 },
155 { "M6 LZ", RADEON_M6 },
156 { "8500 QL", RADEON_R200 },
157 { "8500 QN", RADEON_R200 },
158 { "8500 QO", RADEON_R200 },
159 { "8500 Ql", RADEON_R200 },
160 { "8500 BB", RADEON_R200 },
161 { "7500 QW", RADEON_RV200 },
162 { "7500 QX", RADEON_RV200 },
163 { "9000 Id", RADEON_RV250 },
164 { "9000 Ie", RADEON_RV250 },
165 { "9000 If", RADEON_RV250 },
166 { "9000 Ig", RADEON_RV250 },
167 { "M9 Ld", RADEON_M9 },
168 { "M9 Le", RADEON_M9 },
169 { "M9 Lf", RADEON_M9 },
170 { "M9 Lg", RADEON_M9 },
171 { "9700 ND", RADEON_R300 },
172 { "9700 NE", RADEON_R300 },
173 { "9700 NF", RADEON_R300 },
174 { "9700 NG", RADEON_R300 },
175 { "9100 QM", RADEON_R200 }
176 };
177
178
179 enum radeon_montype
180 {
181 MT_NONE,
182 MT_CRT, /* CRT */
183 MT_LCD, /* LCD */
184 MT_DFP, /* DVI */
185 MT_CTV, /* composite TV */
186 MT_STV /* S-Video out */
187 };
188
189
190 static struct pci_device_id radeonfb_pci_table[] = {
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
192 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
194 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
196 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
198 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
200 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
202 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
204 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
206 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
208 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
210 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
212 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ya, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ya},
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Yd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Yd},
214 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
216 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
218 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
220 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
222 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
223 { 0, }
224 };
225 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
226
227
228 typedef struct {
229 u16 reg;
230 u32 val;
231 } reg_val;
232
233
234 /* these common regs are cleared before mode setting so they do not
235 * interfere with anything
236 */
237 static reg_val common_regs[] = {
238 { OVR_CLR, 0 },
239 { OVR_WID_LEFT_RIGHT, 0 },
240 { OVR_WID_TOP_BOTTOM, 0 },
241 { OV0_SCALE_CNTL, 0 },
242 { SUBPIC_CNTL, 0 },
243 { VIPH_CONTROL, 0 },
244 { I2C_CNTL_1, 0 },
245 { GEN_INT_CNTL, 0 },
246 { CAP0_TRIG_CNTL, 0 },
247 };
248
249 static reg_val common_regs_m6[] = {
250 { OVR_CLR, 0 },
251 { OVR_WID_LEFT_RIGHT, 0 },
252 { OVR_WID_TOP_BOTTOM, 0 },
253 { OV0_SCALE_CNTL, 0 },
254 { SUBPIC_CNTL, 0 },
255 { GEN_INT_CNTL, 0 },
256 { CAP0_TRIG_CNTL, 0 }
257 };
258
259 typedef struct {
260 u8 clock_chip_type;
261 u8 struct_size;
262 u8 accelerator_entry;
263 u8 VGA_entry;
264 u16 VGA_table_offset;
265 u16 POST_table_offset;
266 u16 XCLK;
267 u16 MCLK;
268 u8 num_PLL_blocks;
269 u8 size_PLL_blocks;
270 u16 PCLK_ref_freq;
271 u16 PCLK_ref_divider;
272 u32 PCLK_min_freq;
273 u32 PCLK_max_freq;
274 u16 MCLK_ref_freq;
275 u16 MCLK_ref_divider;
276 u32 MCLK_min_freq;
277 u32 MCLK_max_freq;
278 u16 XCLK_ref_freq;
279 u16 XCLK_ref_divider;
280 u32 XCLK_min_freq;
281 u32 XCLK_max_freq;
282 } __attribute__ ((packed)) PLL_BLOCK;
283
284
285 struct pll_info {
286 int ppll_max;
287 int ppll_min;
288 int xclk;
289 int ref_div;
290 int ref_clk;
291 };
292
293
294 struct ram_info {
295 int ml;
296 int mb;
297 int trcd;
298 int trp;
299 int twr;
300 int cl;
301 int tr2w;
302 int loop_latency;
303 int rloop;
304 };
305
306
307 struct radeon_regs {
308 /* CRTC regs */
309 u32 crtc_h_total_disp;
310 u32 crtc_h_sync_strt_wid;
311 u32 crtc_v_total_disp;
312 u32 crtc_v_sync_strt_wid;
313 u32 crtc_pitch;
314 u32 crtc_gen_cntl;
315 u32 crtc_ext_cntl;
316 u32 dac_cntl;
317
318 u32 flags;
319 u32 pix_clock;
320 int xres, yres;
321
322 /* DDA regs */
323 u32 dda_config;
324 u32 dda_on_off;
325
326 /* PLL regs */
327 u32 ppll_div_3;
328 u32 ppll_ref_div;
329 u32 vclk_ecp_cntl;
330
331 /* Flat panel regs */
332 u32 fp_crtc_h_total_disp;
333 u32 fp_crtc_v_total_disp;
334 u32 fp_gen_cntl;
335 u32 fp_h_sync_strt_wid;
336 u32 fp_horz_stretch;
337 u32 fp_panel_cntl;
338 u32 fp_v_sync_strt_wid;
339 u32 fp_vert_stretch;
340 u32 lvds_gen_cntl;
341 u32 lvds_pll_cntl;
342 u32 tmds_crc;
343 u32 tmds_transmitter_cntl;
344
345 #if defined(__BIG_ENDIAN)
346 u32 surface_cntl;
347 #endif
348 };
349
350
351 struct radeonfb_info {
352 struct fb_info info;
353
354 struct radeon_regs state;
355 struct radeon_regs init_state;
356
357 char name[32];
358 char ram_type[12];
359
360 unsigned long mmio_base_phys;
361 unsigned long fb_base_phys;
362
363 void __iomem *mmio_base;
364 void __iomem *fb_base;
365
366 struct pci_dev *pdev;
367
368 unsigned char *EDID;
369 unsigned char __iomem *bios_seg;
370
371 u32 pseudo_palette[17];
372 struct { u8 red, green, blue, pad; } palette[256];
373
374 int chipset;
375 unsigned char arch;
376 int video_ram;
377 u8 rev;
378 int pitch, bpp, depth;
379 int xres, yres, pixclock;
380 int xres_virtual, yres_virtual;
381 u32 accel_flags;
382
383 int use_default_var;
384 int got_dfpinfo;
385
386 int hasCRTC2;
387 int crtDisp_type;
388 int dviDisp_type;
389
390 int panel_xres, panel_yres;
391 int clock;
392 int hOver_plus, hSync_width, hblank;
393 int vOver_plus, vSync_width, vblank;
394 int hAct_high, vAct_high, interlaced;
395 int synct, misc;
396
397 u32 dp_gui_master_cntl;
398
399 struct pll_info pll;
400 int pll_output_freq, post_div, fb_div;
401
402 struct ram_info ram;
403
404 int mtrr_hdl;
405
406 #ifdef CONFIG_PMAC_PBOOK
407 int pm_reg;
408 u32 save_regs[64];
409 u32 mdll, mdll2;
410 #endif /* CONFIG_PMAC_PBOOK */
411 int asleep;
412
413 struct radeonfb_info *next;
414 };
415
416
417 static struct fb_var_screeninfo radeonfb_default_var = {
418 640, 480, 640, 480, 0, 0, 8, 0,
419 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
420 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
421 0, FB_VMODE_NONINTERLACED
422 };
423
424 /*
425 * IO macros
426 */
427
428 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
429 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
430 #define INREG(addr) readl((rinfo->mmio_base)+addr)
431 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
432
433 #define OUTPLL(addr,val) \
434 do { \
435 OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) | 0x00000080); \
436 OUTREG(CLOCK_CNTL_DATA, val); \
437 } while(0)
438
439 #define OUTPLLP(addr,val,mask) \
440 do { \
441 unsigned int _tmp = INPLL(addr); \
442 _tmp &= (mask); \
443 _tmp |= (val); \
444 OUTPLL(addr, _tmp); \
445 } while (0)
446
447 #define OUTREGP(addr,val,mask) \
448 do { \
449 unsigned int _tmp = INREG(addr); \
450 _tmp &= (mask); \
451 _tmp |= (val); \
452 OUTREG(addr, _tmp); \
453 } while (0)
454
455
456 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
457 {
458 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
459 return (INREG(CLOCK_CNTL_DATA));
460 }
461
462 #define INPLL(addr) _INPLL(rinfo, addr)
463
464 #define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
465 (rinfo->dviDisp_type != MT_STV) && \
466 (rinfo->dviDisp_type != MT_CTV) ? \
467 rinfo->dviDisp_type : rinfo->crtDisp_type)
468
469 static char *GET_MON_NAME(int type)
470 {
471 char *pret = NULL;
472
473 switch (type) {
474 case MT_NONE:
475 pret = "no";
476 break;
477 case MT_CRT:
478 pret = "CRT";
479 break;
480 case MT_DFP:
481 pret = "DFP";
482 break;
483 case MT_LCD:
484 pret = "LCD";
485 break;
486 case MT_CTV:
487 pret = "CTV";
488 break;
489 case MT_STV:
490 pret = "STV";
491 break;
492 }
493
494 return pret;
495 }
496
497
498 /*
499 * 2D engine routines
500 */
501
502 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
503 {
504 int i;
505
506 /* initiate flush */
507 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
508 ~RB2D_DC_FLUSH_ALL);
509
510 for (i=0; i < 2000000; i++) {
511 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
512 break;
513 }
514 }
515
516
517 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
518 {
519 int i;
520
521 for (i=0; i<2000000; i++)
522 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
523 return;
524 }
525
526
527 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
528 {
529 int i;
530
531 /* ensure FIFO is empty before waiting for idle */
532 _radeon_fifo_wait (rinfo, 64);
533
534 for (i=0; i<2000000; i++) {
535 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
536 radeon_engine_flush (rinfo);
537 return;
538 }
539 }
540 }
541
542
543 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
544 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
545
546
547
548 /*
549 * helper routines
550 */
551
552 static __inline__ u32 radeon_get_dstbpp(u16 depth)
553 {
554 switch (depth) {
555 case 8:
556 return DST_8BPP;
557 case 15:
558 return DST_15BPP;
559 case 16:
560 return DST_16BPP;
561 case 32:
562 return DST_32BPP;
563 default:
564 return 0;
565 }
566 }
567
568
569 static inline int var_to_depth(const struct fb_var_screeninfo *var)
570 {
571 if (var->bits_per_pixel != 16)
572 return var->bits_per_pixel;
573 return (var->green.length == 6) ? 16 : 15;
574 }
575
576
577 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
578 {
579 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
580
581 radeon_engine_flush (rinfo);
582
583 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
584 mclk_cntl = INPLL(MCLK_CNTL);
585
586 OUTPLL(MCLK_CNTL, (mclk_cntl |
587 FORCEON_MCLKA |
588 FORCEON_MCLKB |
589 FORCEON_YCLKA |
590 FORCEON_YCLKB |
591 FORCEON_MC |
592 FORCEON_AIC));
593 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
594
595 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
596 SOFT_RESET_CP |
597 SOFT_RESET_HI |
598 SOFT_RESET_SE |
599 SOFT_RESET_RE |
600 SOFT_RESET_PP |
601 SOFT_RESET_E2 |
602 SOFT_RESET_RB);
603 INREG(RBBM_SOFT_RESET);
604 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
605 ~(SOFT_RESET_CP |
606 SOFT_RESET_HI |
607 SOFT_RESET_SE |
608 SOFT_RESET_RE |
609 SOFT_RESET_PP |
610 SOFT_RESET_E2 |
611 SOFT_RESET_RB));
612 INREG(RBBM_SOFT_RESET);
613
614 OUTPLL(MCLK_CNTL, mclk_cntl);
615 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
616 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
617
618 return;
619 }
620
621 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
622
623
624 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
625 {
626 switch (post_div) {
627 case 1:
628 return 0x00;
629 case 2:
630 return 0x01;
631 case 3:
632 return 0x04;
633 case 4:
634 return 0x02;
635 case 6:
636 return 0x06;
637 case 8:
638 return 0x03;
639 case 12:
640 return 0x07;
641 default:
642 return 0x02;
643 }
644 }
645
646
647
648 static __inline__ int round_div(int num, int den)
649 {
650 return (num + (den / 2)) / den;
651 }
652
653
654
655 static __inline__ int min_bits_req(int val)
656 {
657 int bits_req = 0;
658
659 if (val == 0)
660 bits_req = 1;
661
662 while (val) {
663 val >>= 1;
664 bits_req++;
665 }
666
667 return (bits_req);
668 }
669
670
671 static __inline__ int _max(int val1, int val2)
672 {
673 if (val1 >= val2)
674 return val1;
675 else
676 return val2;
677 }
678
679
680
681 /*
682 * globals
683 */
684
685 static char *mode_option __initdata;
686 static char noaccel = 0;
687 static char mirror = 0;
688 static int panel_yres __initdata = 0;
689 static char force_dfp __initdata = 0;
690 static struct radeonfb_info *board_list = NULL;
691 static char nomtrr __initdata = 0;
692
693 /*
694 * prototypes
695 */
696
697 static void radeon_save_state (struct radeonfb_info *rinfo,
698 struct radeon_regs *save);
699 static void radeon_engine_init (struct radeonfb_info *rinfo);
700 static void radeon_write_mode (struct radeonfb_info *rinfo,
701 struct radeon_regs *mode);
702 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
703 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
704 static int radeon_init_disp_var (struct radeonfb_info *rinfo, struct fb_var_screeninfo *var);
705 static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo);
706 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg);
707 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
708 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
709 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
710 static void radeon_get_EDID(struct radeonfb_info *rinfo);
711 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
712 static void radeon_update_default_var(struct radeonfb_info *rinfo);
713
714 #ifdef CONFIG_PPC_OF
715
716 static int radeon_read_OF (struct radeonfb_info *rinfo);
717 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
718 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
719
720 #ifdef CONFIG_PMAC_PBOOK
721 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
722 static struct pmu_sleep_notifier radeon_sleep_notifier = {
723 radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
724 };
725 #endif /* CONFIG_PMAC_PBOOK */
726 #ifdef CONFIG_PMAC_BACKLIGHT
727 static int radeon_set_backlight_enable(int on, int level, void *data);
728 static int radeon_set_backlight_level(int level, void *data);
729 static struct backlight_controller radeon_backlight_controller = {
730 radeon_set_backlight_enable,
731 radeon_set_backlight_level
732 };
733 #endif /* CONFIG_PMAC_BACKLIGHT */
734
735 #endif /* CONFIG_PPC_OF */
736
737
738 static void __iomem *radeon_find_rom(struct radeonfb_info *rinfo)
739 {
740 #if defined(__i386__)
741 u32 segstart;
742 char __iomem *rom_base;
743 char __iomem *rom;
744 int stage;
745 int i,j;
746 char aty_rom_sig[] = "761295520";
747 char *radeon_sig[] = {
748 "RG6",
749 "RADEON"
750 };
751
752 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
753
754 stage = 1;
755
756 rom_base = ioremap(segstart, 0x1000);
757
758 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
759 stage = 2;
760
761
762 if (stage != 2) {
763 iounmap(rom_base);
764 continue;
765 }
766
767 rom = rom_base;
768
769 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
770 if (aty_rom_sig[0] == *rom)
771 if (strncmp(aty_rom_sig, rom,
772 strlen(aty_rom_sig)) == 0)
773 stage = 3;
774 rom++;
775 }
776 if (stage != 3) {
777 iounmap(rom_base);
778 continue;
779 }
780 rom = rom_base;
781
782 for (i = 0; (i < 512) && (stage != 4); i++) {
783 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
784 if (radeon_sig[j][0] == *rom)
785 if (strncmp(radeon_sig[j], rom,
786 strlen(radeon_sig[j])) == 0) {
787 stage = 4;
788 break;
789 }
790 }
791 rom++;
792 }
793 if (stage != 4) {
794 iounmap(rom_base);
795 continue;
796 }
797
798 return rom_base;
799 }
800 #endif
801 return NULL;
802 }
803
804
805
806
807 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, void __iomem *bios_seg)
808 {
809 void __iomem *bios_header;
810 void __iomem *header_ptr;
811 u16 bios_header_offset, pll_info_offset;
812 PLL_BLOCK pll;
813
814 if (bios_seg) {
815 bios_header = bios_seg + 0x48L;
816 header_ptr = bios_header;
817
818 bios_header_offset = readw(header_ptr);
819 bios_header = bios_seg + bios_header_offset;
820 bios_header += 0x30;
821
822 header_ptr = bios_header;
823 pll_info_offset = readw(header_ptr);
824 header_ptr = bios_seg + pll_info_offset;
825
826 memcpy_fromio(&pll, header_ptr, 50);
827
828 rinfo->pll.xclk = (u32)pll.XCLK;
829 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
830 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
831 rinfo->pll.ppll_min = pll.PCLK_min_freq;
832 rinfo->pll.ppll_max = pll.PCLK_max_freq;
833
834 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
835 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
836 } else {
837 #ifdef CONFIG_PPC_OF
838 if (radeon_read_OF(rinfo)) {
839 unsigned int tmp, Nx, M, ref_div, xclk;
840
841 tmp = INPLL(X_MPLL_REF_FB_DIV);
842 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
843
844 Nx = (tmp & 0xff00) >> 8;
845 M = (tmp & 0xff);
846 xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
847 (2 * M)));
848
849 rinfo->pll.xclk = xclk;
850 rinfo->pll.ref_div = ref_div;
851 rinfo->pll.ppll_min = 12000;
852 rinfo->pll.ppll_max = 35000;
853
854 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
855 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
856
857 return;
858 }
859 #endif
860 /* no BIOS or BIOS not found, use defaults */
861 switch (rinfo->chipset) {
862 case PCI_DEVICE_ID_ATI_RADEON_QW:
863 case PCI_DEVICE_ID_ATI_RADEON_QX:
864 rinfo->pll.ppll_max = 35000;
865 rinfo->pll.ppll_min = 12000;
866 rinfo->pll.xclk = 23000;
867 rinfo->pll.ref_div = 12;
868 rinfo->pll.ref_clk = 2700;
869 break;
870 case PCI_DEVICE_ID_ATI_RADEON_QL:
871 case PCI_DEVICE_ID_ATI_RADEON_QN:
872 case PCI_DEVICE_ID_ATI_RADEON_QO:
873 case PCI_DEVICE_ID_ATI_RADEON_Ql:
874 case PCI_DEVICE_ID_ATI_RADEON_BB:
875 rinfo->pll.ppll_max = 35000;
876 rinfo->pll.ppll_min = 12000;
877 rinfo->pll.xclk = 27500;
878 rinfo->pll.ref_div = 12;
879 rinfo->pll.ref_clk = 2700;
880 break;
881 case PCI_DEVICE_ID_ATI_RADEON_Id:
882 case PCI_DEVICE_ID_ATI_RADEON_Ie:
883 case PCI_DEVICE_ID_ATI_RADEON_If:
884 case PCI_DEVICE_ID_ATI_RADEON_Ig:
885 rinfo->pll.ppll_max = 35000;
886 rinfo->pll.ppll_min = 12000;
887 rinfo->pll.xclk = 25000;
888 rinfo->pll.ref_div = 12;
889 rinfo->pll.ref_clk = 2700;
890 break;
891 case PCI_DEVICE_ID_ATI_RADEON_ND:
892 case PCI_DEVICE_ID_ATI_RADEON_NE:
893 case PCI_DEVICE_ID_ATI_RADEON_NF:
894 case PCI_DEVICE_ID_ATI_RADEON_NG:
895 rinfo->pll.ppll_max = 40000;
896 rinfo->pll.ppll_min = 20000;
897 rinfo->pll.xclk = 27000;
898 rinfo->pll.ref_div = 12;
899 rinfo->pll.ref_clk = 2700;
900 break;
901 case PCI_DEVICE_ID_ATI_RADEON_QD:
902 case PCI_DEVICE_ID_ATI_RADEON_QE:
903 case PCI_DEVICE_ID_ATI_RADEON_QF:
904 case PCI_DEVICE_ID_ATI_RADEON_QG:
905 default:
906 rinfo->pll.ppll_max = 35000;
907 rinfo->pll.ppll_min = 12000;
908 rinfo->pll.xclk = 16600;
909 rinfo->pll.ref_div = 67;
910 rinfo->pll.ref_clk = 2700;
911 break;
912 }
913
914 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
915 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
916 }
917 }
918
919
920 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
921 {
922 unsigned int tmp;
923
924 if (force_dfp) {
925 rinfo->dviDisp_type = MT_DFP;
926 return;
927 }
928
929 tmp = INREG(BIOS_4_SCRATCH);
930 printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
931
932 if (rinfo->hasCRTC2) {
933 /* primary DVI port */
934 if (tmp & 0x08)
935 rinfo->dviDisp_type = MT_DFP;
936 else if (tmp & 0x4)
937 rinfo->dviDisp_type = MT_LCD;
938 else if (tmp & 0x200)
939 rinfo->dviDisp_type = MT_CRT;
940 else if (tmp & 0x10)
941 rinfo->dviDisp_type = MT_CTV;
942 else if (tmp & 0x20)
943 rinfo->dviDisp_type = MT_STV;
944
945 /* secondary CRT port */
946 if (tmp & 0x2)
947 rinfo->crtDisp_type = MT_CRT;
948 else if (tmp & 0x800)
949 rinfo->crtDisp_type = MT_DFP;
950 else if (tmp & 0x400)
951 rinfo->crtDisp_type = MT_LCD;
952 else if (tmp & 0x1000)
953 rinfo->crtDisp_type = MT_CTV;
954 else if (tmp & 0x2000)
955 rinfo->crtDisp_type = MT_STV;
956 } else {
957 rinfo->dviDisp_type = MT_NONE;
958
959 tmp = INREG(FP_GEN_CNTL);
960
961 if (tmp & FP_EN_TMDS)
962 rinfo->crtDisp_type = MT_DFP;
963 else
964 rinfo->crtDisp_type = MT_CRT;
965 }
966 }
967
968
969
970 static void radeon_get_EDID(struct radeonfb_info *rinfo)
971 {
972 #ifdef CONFIG_PPC_OF
973 if (!radeon_get_EDID_OF(rinfo))
974 RTRACE("radeonfb: could not retrieve EDID from OF\n");
975 #else
976 /* XXX use other methods later */
977 #endif
978 }
979
980
981 #ifdef CONFIG_PPC_OF
982 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
983 {
984 struct device_node *dp;
985 unsigned char *pedid = NULL;
986 static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
987 int i;
988
989 dp = pci_device_to_OF_node(rinfo->pdev);
990 while (dp != NULL) {
991 for (i = 0; propnames[i] != NULL; ++i) {
992 pedid = (unsigned char *)
993 get_property(dp, propnames[i], NULL);
994 if (pedid != NULL) {
995 rinfo->EDID = pedid;
996 return 1;
997 }
998 }
999 dp = dp->child;
1000 }
1001 return 0;
1002 }
1003 #endif /* CONFIG_PPC_OF */
1004
1005
1006 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
1007 {
1008 unsigned char *block = rinfo->EDID;
1009
1010 if (!block)
1011 return 0;
1012
1013 /* jump to the detailed timing block section */
1014 block += 54;
1015
1016 rinfo->clock = (block[0] + (block[1] << 8));
1017 rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1018 rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1019 rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1020 rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1021 rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1022 rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1023 rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1024 rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1025 rinfo->interlaced = ((block[17] & 0x80) >> 7);
1026 rinfo->synct = ((block[17] & 0x18) >> 3);
1027 rinfo->misc = ((block[17] & 0x06) >> 1);
1028 rinfo->hAct_high = rinfo->vAct_high = 0;
1029 if (rinfo->synct == 3) {
1030 if (rinfo->misc & 2)
1031 rinfo->hAct_high = 1;
1032 if (rinfo->misc & 1)
1033 rinfo->vAct_high = 1;
1034 }
1035
1036 printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1037 rinfo->panel_xres, rinfo->panel_yres);
1038
1039 rinfo->got_dfpinfo = 1;
1040
1041 return 1;
1042 }
1043
1044
1045 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1046 {
1047 struct fb_var_screeninfo *var = &radeonfb_default_var;
1048
1049 var->xres = rinfo->panel_xres;
1050 var->yres = rinfo->panel_yres;
1051 var->xres_virtual = rinfo->panel_xres;
1052 var->yres_virtual = rinfo->panel_yres;
1053 var->xoffset = var->yoffset = 0;
1054 var->bits_per_pixel = 8;
1055 var->pixclock = 100000000 / rinfo->clock;
1056 var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1057 var->right_margin = rinfo->hOver_plus;
1058 var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1059 var->lower_margin = rinfo->vOver_plus;
1060 var->hsync_len = rinfo->hSync_width;
1061 var->vsync_len = rinfo->vSync_width;
1062 var->sync = 0;
1063 if (rinfo->synct == 3) {
1064 if (rinfo->hAct_high)
1065 var->sync |= FB_SYNC_HOR_HIGH_ACT;
1066 if (rinfo->vAct_high)
1067 var->sync |= FB_SYNC_VERT_HIGH_ACT;
1068 }
1069
1070 var->vmode = 0;
1071 if (rinfo->interlaced)
1072 var->vmode |= FB_VMODE_INTERLACED;
1073
1074 rinfo->use_default_var = 1;
1075 }
1076
1077
1078 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1079 {
1080 char __iomem *fpbiosstart, *tmp, *tmp0;
1081 char stmp[30];
1082 int i;
1083
1084 if (!rinfo->bios_seg)
1085 return 0;
1086
1087 if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1088 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1089 return 0;
1090 }
1091
1092 if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1093 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1094 return 0;
1095 }
1096
1097 for(i=0; i<24; i++)
1098 stmp[i] = readb(tmp+i+1);
1099 stmp[24] = 0;
1100 printk("radeonfb: panel ID string: %s\n", stmp);
1101 rinfo->panel_xres = readw(tmp + 25);
1102 rinfo->panel_yres = readw(tmp + 27);
1103 printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1104 rinfo->panel_xres, rinfo->panel_yres);
1105
1106 for(i=0; i<32; i++) {
1107 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1108 if (tmp0 == 0)
1109 break;
1110 if ((readw(tmp0) == rinfo->panel_xres) &&
1111 (readw(tmp0+2) == rinfo->panel_yres)) {
1112 rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1113 rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1114 rinfo->hSync_width = readb(tmp0+23) * 8;
1115 rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1116 rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1117 rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1118 rinfo->clock = readw(tmp0+9);
1119
1120 rinfo->got_dfpinfo = 1;
1121 return 1;
1122 }
1123 }
1124
1125 return 0;
1126 }
1127
1128
1129
1130 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1131 {
1132 unsigned int tmp;
1133 unsigned short a, b;
1134
1135 if (radeon_get_dfpinfo_BIOS(rinfo))
1136 radeon_update_default_var(rinfo);
1137
1138 if (radeon_dfp_parse_EDID(rinfo))
1139 radeon_update_default_var(rinfo);
1140
1141 if (!rinfo->got_dfpinfo) {
1142 /*
1143 * it seems all else has failed now and we
1144 * resort to probing registers for our DFP info
1145 */
1146 if (panel_yres) {
1147 rinfo->panel_yres = panel_yres;
1148 } else {
1149 tmp = INREG(FP_VERT_STRETCH);
1150 tmp &= 0x00fff000;
1151 rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1152 }
1153
1154 switch (rinfo->panel_yres) {
1155 case 480:
1156 rinfo->panel_xres = 640;
1157 break;
1158 case 600:
1159 rinfo->panel_xres = 800;
1160 break;
1161 case 768:
1162 #if defined(__powerpc__)
1163 if (rinfo->dviDisp_type == MT_LCD)
1164 rinfo->panel_xres = 1152;
1165 else
1166 #endif
1167 rinfo->panel_xres = 1024;
1168 break;
1169 case 1024:
1170 rinfo->panel_xres = 1280;
1171 break;
1172 case 1050:
1173 rinfo->panel_xres = 1400;
1174 break;
1175 case 1200:
1176 rinfo->panel_xres = 1600;
1177 break;
1178 default:
1179 printk("radeonfb: Failed to detect DFP panel size\n");
1180 return 0;
1181 }
1182
1183 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1184 rinfo->panel_xres, rinfo->panel_yres);
1185
1186 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1187 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1188 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1189 rinfo->hblank = (a - b + 1) * 8;
1190
1191 tmp = INREG(FP_H_SYNC_STRT_WID);
1192 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1193 FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1194 rinfo->hOver_plus *= 8;
1195 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1196 FP_H_SYNC_WID_SHIFT);
1197 rinfo->hSync_width *= 8;
1198 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1199 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1200 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1201 rinfo->vblank = a - b /* + 24 */ ;
1202
1203 tmp = INREG(FP_V_SYNC_STRT_WID);
1204 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1205 - b + 1;
1206 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1207 FP_V_SYNC_WID_SHIFT);
1208
1209 return 1;
1210 }
1211
1212 return 1;
1213 }
1214
1215
1216 #ifdef CONFIG_PPC_OF
1217 static int radeon_read_OF (struct radeonfb_info *rinfo)
1218 {
1219 struct device_node *dp;
1220 unsigned int *xtal;
1221
1222 dp = pci_device_to_OF_node(rinfo->pdev);
1223
1224 xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", NULL);
1225
1226 rinfo->pll.ref_clk = *xtal / 10;
1227
1228 if (*xtal)
1229 return 1;
1230 else
1231 return 0;
1232 }
1233 #endif
1234
1235
1236 static void radeon_engine_init (struct radeonfb_info *rinfo)
1237 {
1238 u32 temp;
1239
1240 /* disable 3D engine */
1241 OUTREG(RB3D_CNTL, 0);
1242
1243 radeon_engine_reset ();
1244
1245 radeon_fifo_wait (1);
1246 OUTREG(RB2D_DSTCACHE_MODE, 0);
1247
1248 radeon_fifo_wait (1);
1249 temp = INREG(DEFAULT_PITCH_OFFSET);
1250 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1251 (rinfo->pitch << 0x16)));
1252
1253 radeon_fifo_wait (1);
1254 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1255
1256 radeon_fifo_wait (1);
1257 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1258 DEFAULT_SC_BOTTOM_MAX));
1259
1260 temp = radeon_get_dstbpp(rinfo->depth);
1261 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1262 radeon_fifo_wait (1);
1263 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1264 GMC_BRUSH_SOLID_COLOR |
1265 GMC_SRC_DATATYPE_COLOR));
1266
1267 radeon_fifo_wait (7);
1268
1269 /* clear line drawing regs */
1270 OUTREG(DST_LINE_START, 0);
1271 OUTREG(DST_LINE_END, 0);
1272
1273 /* set brush color regs */
1274 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1275 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1276
1277 /* set source color regs */
1278 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1279 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1280
1281 /* default write mask */
1282 OUTREG(DP_WRITE_MSK, 0xffffffff);
1283
1284 radeon_engine_idle ();
1285 }
1286
1287
1288 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1289 {
1290 struct fb_info *info = &rinfo->info;
1291 struct fb_var_screeninfo var;
1292
1293 var = radeonfb_default_var;
1294 if ((radeon_init_disp_var(rinfo, &var)) < 0)
1295 return -1;
1296
1297 rinfo->depth = var_to_depth(&var);
1298 rinfo->bpp = var.bits_per_pixel;
1299
1300 info->var = var;
1301 fb_alloc_cmap(&info->cmap, 256, 0);
1302
1303 var.activate = FB_ACTIVATE_NOW;
1304 return 0;
1305 }
1306
1307
1308 static int radeon_init_disp_var (struct radeonfb_info *rinfo,
1309 struct fb_var_screeninfo *var)
1310 {
1311 #ifndef MODULE
1312 if (mode_option)
1313 fb_find_mode (var, &rinfo->info, mode_option,
1314 NULL, 0, NULL, 8);
1315 else
1316 #endif
1317 if (rinfo->use_default_var)
1318 /* We will use the modified default far */
1319 *var = radeonfb_default_var;
1320 else
1321
1322 fb_find_mode (var, &rinfo->info, "640x480-8@60",
1323 NULL, 0, NULL, 0);
1324
1325 if (noaccel)
1326 var->accel_flags &= ~FB_ACCELF_TEXT;
1327 else
1328 var->accel_flags |= FB_ACCELF_TEXT;
1329
1330 return 0;
1331 }
1332
1333
1334 static int radeon_do_maximize(struct radeonfb_info *rinfo,
1335 struct fb_var_screeninfo *var,
1336 struct fb_var_screeninfo *v,
1337 int nom, int den)
1338 {
1339 static struct {
1340 int xres, yres;
1341 } modes[] = {
1342 {1600, 1280},
1343 {1280, 1024},
1344 {1024, 768},
1345 {800, 600},
1346 {640, 480},
1347 {-1, -1}
1348 };
1349 int i;
1350
1351 /* use highest possible virtual resolution */
1352 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1353 printk("radeonfb: using max available virtual resolution\n");
1354 for (i=0; modes[i].xres != -1; i++) {
1355 if (modes[i].xres * nom / den * modes[i].yres <
1356 rinfo->video_ram / 2)
1357 break;
1358 }
1359 if (modes[i].xres == -1) {
1360 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1361 return -EINVAL;
1362 }
1363 v->xres_virtual = modes[i].xres;
1364 v->yres_virtual = modes[i].yres;
1365
1366 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1367 v->xres_virtual, v->yres_virtual);
1368 } else if (v->xres_virtual == -1) {
1369 v->xres_virtual = (rinfo->video_ram * den /
1370 (nom * v->yres_virtual * 2)) & ~15;
1371 } else if (v->yres_virtual == -1) {
1372 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1373 v->yres_virtual = rinfo->video_ram * den /
1374 (nom * v->xres_virtual *2);
1375 } else {
1376 if (v->xres_virtual * nom / den * v->yres_virtual >
1377 rinfo->video_ram) {
1378 return -EINVAL;
1379 }
1380 }
1381
1382 if (v->xres_virtual * nom / den >= 8192) {
1383 v->xres_virtual = 8192 * den / nom - 16;
1384 }
1385
1386 if (v->xres_virtual < v->xres)
1387 return -EINVAL;
1388
1389 if (v->yres_virtual < v->yres)
1390 return -EINVAL;
1391
1392 return 0;
1393 }
1394
1395
1396 static int radeonfb_check_var (struct fb_var_screeninfo *var, struct fb_info *info)
1397 {
1398 struct radeonfb_info *rinfo = (struct radeonfb_info *) info->par;
1399 struct fb_var_screeninfo v;
1400 int nom, den;
1401
1402 memcpy (&v, var, sizeof (v));
1403
1404 switch (v.bits_per_pixel) {
1405 case 0 ... 8:
1406 v.bits_per_pixel = 8;
1407 break;
1408 case 9 ... 16:
1409 v.bits_per_pixel = 16;
1410 break;
1411 case 17 ... 24:
1412 #if 0 /* Doesn't seem to work */
1413 v.bits_per_pixel = 24;
1414 break;
1415 #endif
1416 return -EINVAL;
1417 case 25 ... 32:
1418 v.bits_per_pixel = 32;
1419 break;
1420 default:
1421 return -EINVAL;
1422 }
1423
1424 switch (var_to_depth(&v)) {
1425 case 8:
1426 nom = den = 1;
1427 v.red.offset = v.green.offset = v.blue.offset = 0;
1428 v.red.length = v.green.length = v.blue.length = 8;
1429 v.transp.offset = v.transp.length = 0;
1430 break;
1431 case 15:
1432 nom = 2;
1433 den = 1;
1434 v.red.offset = 10;
1435 v.green.offset = 5;
1436 v.blue.offset = 0;
1437 v.red.length = v.green.length = v.blue.length = 5;
1438 v.transp.offset = v.transp.length = 0;
1439 break;
1440 case 16:
1441 nom = 2;
1442 den = 1;
1443 v.red.offset = 11;
1444 v.green.offset = 5;
1445 v.blue.offset = 0;
1446 v.red.length = 5;
1447 v.green.length = 6;
1448 v.blue.length = 5;
1449 v.transp.offset = v.transp.length = 0;
1450 break;
1451 case 24:
1452 nom = 4;
1453 den = 1;
1454 v.red.offset = 16;
1455 v.green.offset = 8;
1456 v.blue.offset = 0;
1457 v.red.length = v.blue.length = v.green.length = 8;
1458 v.transp.offset = v.transp.length = 0;
1459 break;
1460 case 32:
1461 nom = 4;
1462 den = 1;
1463 v.red.offset = 16;
1464 v.green.offset = 8;
1465 v.blue.offset = 0;
1466 v.red.length = v.blue.length = v.green.length = 8;
1467 v.transp.offset = 24;
1468 v.transp.length = 8;
1469 break;
1470 default:
1471 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
1472 var->xres, var->yres, var->bits_per_pixel);
1473 return -EINVAL;
1474 }
1475
1476 if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
1477 return -EINVAL;
1478
1479 if (v.xoffset < 0)
1480 v.xoffset = 0;
1481 if (v.yoffset < 0)
1482 v.yoffset = 0;
1483
1484 if (v.xoffset > v.xres_virtual - v.xres)
1485 v.xoffset = v.xres_virtual - v.xres - 1;
1486
1487 if (v.yoffset > v.yres_virtual - v.yres)
1488 v.yoffset = v.yres_virtual - v.yres - 1;
1489
1490 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
1491 v.transp.offset = v.transp.length =
1492 v.transp.msb_right = 0;
1493
1494 if (noaccel)
1495 v.accel_flags = 0;
1496
1497 memcpy(var, &v, sizeof(v));
1498
1499 return 0;
1500 }
1501
1502
1503 static int radeonfb_pan_display (struct fb_var_screeninfo *var,
1504 struct fb_info *info)
1505 {
1506 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1507
1508 if ((var->xoffset + var->xres > var->xres_virtual)
1509 || (var->yoffset + var->yres > var->yres_virtual))
1510 return -EINVAL;
1511
1512 if (rinfo->asleep)
1513 return 0;
1514
1515 OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
1516 * var->bits_per_pixel / 8) & ~7);
1517 return 0;
1518 }
1519
1520
1521 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
1522 unsigned long arg, struct fb_info *info)
1523 {
1524 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1525 unsigned int tmp;
1526 u32 value = 0;
1527 int rc;
1528
1529 switch (cmd) {
1530 /*
1531 * TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
1532 */
1533 case FBIO_RADEON_SET_MIRROR:
1534 switch (rinfo->arch) {
1535 case RADEON_R100:
1536 case RADEON_RV100:
1537 case RADEON_R200:
1538 case RADEON_RV200:
1539 case RADEON_RV250:
1540 case RADEON_R300:
1541 return -EINVAL;
1542 default:
1543 /* RADEON M6, RADEON_M7, RADEON_M9 */
1544 break;
1545 }
1546
1547 rc = get_user(value, (__u32 __user *)arg);
1548
1549 if (rc)
1550 return rc;
1551
1552 if (value & 0x01) {
1553 tmp = INREG(LVDS_GEN_CNTL);
1554
1555 tmp |= (LVDS_ON | LVDS_BLON);
1556 } else {
1557 tmp = INREG(LVDS_GEN_CNTL);
1558
1559 tmp &= ~(LVDS_ON | LVDS_BLON);
1560 }
1561
1562 OUTREG(LVDS_GEN_CNTL, tmp);
1563
1564 if (value & 0x02) {
1565 tmp = INREG(CRTC_EXT_CNTL);
1566 tmp |= CRTC_CRT_ON;
1567
1568 mirror = 1;
1569 } else {
1570 tmp = INREG(CRTC_EXT_CNTL);
1571 tmp &= ~CRTC_CRT_ON;
1572
1573 mirror = 0;
1574 }
1575
1576 OUTREG(CRTC_EXT_CNTL, tmp);
1577
1578 break;
1579 case FBIO_RADEON_GET_MIRROR:
1580 switch (rinfo->arch) {
1581 case RADEON_R100:
1582 case RADEON_RV100:
1583 case RADEON_R200:
1584 case RADEON_RV200:
1585 case RADEON_RV250:
1586 case RADEON_R300:
1587 return -EINVAL;
1588 default:
1589 /* RADEON M6, RADEON_M7, RADEON_M9 */
1590 break;
1591 }
1592
1593 tmp = INREG(LVDS_GEN_CNTL);
1594 if ((LVDS_ON | LVDS_BLON) & tmp)
1595 value |= 0x01;
1596
1597 tmp = INREG(CRTC_EXT_CNTL);
1598 if (CRTC_CRT_ON & tmp)
1599 value |= 0x02;
1600
1601 return put_user(value, (__u32 __user *)arg);
1602 default:
1603 return -EINVAL;
1604 }
1605
1606 return -EINVAL;
1607 }
1608
1609
1610 static int radeonfb_blank (int blank, struct fb_info *info)
1611 {
1612 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1613 u32 val = INREG(CRTC_EXT_CNTL);
1614 u32 val2 = INREG(LVDS_GEN_CNTL);
1615
1616 if (rinfo->asleep)
1617 return 0;
1618
1619 #ifdef CONFIG_PMAC_BACKLIGHT
1620 if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
1621 set_backlight_enable(!blank);
1622 return 0;
1623 }
1624 #endif
1625
1626 /* reset it */
1627 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
1628 CRTC_VSYNC_DIS);
1629 val2 &= ~(LVDS_DISPLAY_DIS);
1630
1631 switch (blank) {
1632 case VESA_NO_BLANKING:
1633 break;
1634 case VESA_VSYNC_SUSPEND:
1635 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
1636 break;
1637 case VESA_HSYNC_SUSPEND:
1638 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
1639 break;
1640 case VESA_POWERDOWN:
1641 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
1642 CRTC_HSYNC_DIS);
1643 val2 |= (LVDS_DISPLAY_DIS);
1644 break;
1645 }
1646
1647 switch (rinfo->dviDisp_type) {
1648 case MT_LCD:
1649 OUTREG(LVDS_GEN_CNTL, val2);
1650 break;
1651 case MT_CRT:
1652 default:
1653 OUTREG(CRTC_EXT_CNTL, val);
1654 break;
1655 }
1656
1657 return 0;
1658 }
1659
1660
1661 static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
1662 unsigned blue, unsigned transp, struct fb_info *info)
1663 {
1664 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1665 u32 pindex, vclk_cntl;
1666 unsigned int i;
1667
1668 if (regno > 255)
1669 return 1;
1670
1671 red >>= 8;
1672 green >>= 8;
1673 blue >>= 8;
1674 rinfo->palette[regno].red = red;
1675 rinfo->palette[regno].green = green;
1676 rinfo->palette[regno].blue = blue;
1677
1678 /* default */
1679 pindex = regno;
1680
1681 if (!rinfo->asleep) {
1682 vclk_cntl = INPLL(VCLK_ECP_CNTL);
1683 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
1684
1685 if (rinfo->bpp == 16) {
1686 pindex = regno * 8;
1687
1688 if (rinfo->depth == 16 && regno > 63)
1689 return 1;
1690 if (rinfo->depth == 15 && regno > 31)
1691 return 1;
1692
1693 /* For 565, the green component is mixed one order below */
1694 if (rinfo->depth == 16) {
1695 OUTREG(PALETTE_INDEX, pindex>>1);
1696 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
1697 (green << 8) | (rinfo->palette[regno>>1].blue));
1698 green = rinfo->palette[regno<<1].green;
1699 }
1700 }
1701
1702 if (rinfo->depth != 16 || regno < 32) {
1703 OUTREG(PALETTE_INDEX, pindex);
1704 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
1705 }
1706
1707 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
1708 }
1709 if (regno < 16) {
1710 switch (rinfo->depth) {
1711 case 15:
1712 ((u16 *) (info->pseudo_palette))[regno] =
1713 (regno << 10) | (regno << 5) | regno;
1714 break;
1715 case 16:
1716 ((u16 *) (info->pseudo_palette))[regno] =
1717 (regno << 11) | (regno << 6) | regno;
1718 break;
1719 case 24:
1720 ((u32 *) (info->pseudo_palette))[regno] =
1721 (regno << 16) | (regno << 8) | regno;
1722 break;
1723 case 32:
1724 i = (regno << 8) | regno;
1725 ((u32 *) (info->pseudo_palette))[regno] =
1726 (i << 16) | i;
1727 break;
1728 }
1729 }
1730 return 0;
1731 }
1732
1733
1734
1735 static void radeon_save_state (struct radeonfb_info *rinfo,
1736 struct radeon_regs *save)
1737 {
1738 /* CRTC regs */
1739 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
1740 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
1741 save->dac_cntl = INREG(DAC_CNTL);
1742 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
1743 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
1744 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
1745 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
1746 save->crtc_pitch = INREG(CRTC_PITCH);
1747 #if defined(__BIG_ENDIAN)
1748 save->surface_cntl = INREG(SURFACE_CNTL);
1749 #endif
1750
1751 /* FP regs */
1752 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
1753 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
1754 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
1755 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
1756 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
1757 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
1758 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
1759 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
1760 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
1761 save->tmds_crc = INREG(TMDS_CRC);
1762 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
1763 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
1764 }
1765
1766
1767
1768 static int radeonfb_set_par (struct fb_info *info)
1769 {
1770 struct radeonfb_info *rinfo = (struct radeonfb_info *)info->par;
1771 struct fb_var_screeninfo *mode = &info->var;
1772 struct radeon_regs newmode;
1773 int hTotal, vTotal, hSyncStart, hSyncEnd,
1774 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
1775 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
1776 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
1777 u32 dotClock = 1000000000 / mode->pixclock,
1778 sync, h_sync_pol, v_sync_pol;
1779 int freq = dotClock / 10; /* x 100 */
1780 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
1781 int useable_precision, roff, ron;
1782 int min_bits, format = 0;
1783 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
1784 int primary_mon = PRIMARY_MONITOR(rinfo);
1785 int depth = var_to_depth(mode);
1786 int accel = (mode->accel_flags & FB_ACCELF_TEXT) != 0;
1787
1788 rinfo->xres = mode->xres;
1789 rinfo->yres = mode->yres;
1790 rinfo->xres_virtual = mode->xres_virtual;
1791 rinfo->yres_virtual = mode->yres_virtual;
1792 rinfo->pixclock = mode->pixclock;
1793
1794 hSyncStart = mode->xres + mode->right_margin;
1795 hSyncEnd = hSyncStart + mode->hsync_len;
1796 hTotal = hSyncEnd + mode->left_margin;
1797
1798 vSyncStart = mode->yres + mode->lower_margin;
1799 vSyncEnd = vSyncStart + mode->vsync_len;
1800 vTotal = vSyncEnd + mode->upper_margin;
1801
1802 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1803 if (rinfo->panel_xres < mode->xres)
1804 rinfo->xres = mode->xres = rinfo->panel_xres;
1805 if (rinfo->panel_yres < mode->yres)
1806 rinfo->yres = mode->yres = rinfo->panel_yres;
1807
1808 hTotal = mode->xres + rinfo->hblank;
1809 hSyncStart = mode->xres + rinfo->hOver_plus;
1810 hSyncEnd = hSyncStart + rinfo->hSync_width;
1811
1812 vTotal = mode->yres + rinfo->vblank;
1813 vSyncStart = mode->yres + rinfo->vOver_plus;
1814 vSyncEnd = vSyncStart + rinfo->vSync_width;
1815 }
1816
1817 sync = mode->sync;
1818 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1819 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1820
1821 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
1822 hSyncStart, hSyncEnd, hTotal);
1823 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
1824 vSyncStart, vSyncEnd, vTotal);
1825
1826 hsync_wid = (hSyncEnd - hSyncStart) / 8;
1827 vsync_wid = vSyncEnd - vSyncStart;
1828 if (hsync_wid == 0)
1829 hsync_wid = 1;
1830 else if (hsync_wid > 0x3f) /* max */
1831 hsync_wid = 0x3f;
1832
1833 if (vsync_wid == 0)
1834 vsync_wid = 1;
1835 else if (vsync_wid > 0x1f) /* max */
1836 vsync_wid = 0x1f;
1837
1838 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1839 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1840
1841 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1842
1843 format = radeon_get_dstbpp(depth);
1844 bytpp = mode->bits_per_pixel >> 3;
1845
1846 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
1847 hsync_fudge = hsync_fudge_fp[format-1];
1848 else
1849 hsync_fudge = hsync_adj_tab[format-1];
1850
1851 hsync_start = hSyncStart - 8 + hsync_fudge;
1852
1853 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
1854 (format << 8);
1855
1856 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
1857 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
1858 if (mirror)
1859 newmode.crtc_ext_cntl |= CRTC_CRT_ON;
1860
1861 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
1862 CRTC_INTERLACE_EN);
1863 } else {
1864 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
1865 CRTC_CRT_ON;
1866 }
1867
1868 newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
1869 DAC_8BIT_EN;
1870
1871 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
1872 (((mode->xres / 8) - 1) << 16));
1873
1874 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
1875 (hsync_wid << 16) | (h_sync_pol << 23));
1876
1877 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
1878 ((mode->yres - 1) << 16);
1879
1880 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
1881 (vsync_wid << 16) | (v_sync_pol << 23));
1882
1883 if (accel) {
1884 /* We first calculate the engine pitch */
1885 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1886 & ~(0x3f)) >> 6;
1887
1888 /* Then, re-multiply it to get the CRTC pitch */
1889 newmode.crtc_pitch = (rinfo->pitch << 3) / ((mode->bits_per_pixel + 1) / 8);
1890 } else
1891 newmode.crtc_pitch = (mode->xres_virtual >> 3);
1892 newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
1893
1894 #if defined(__BIG_ENDIAN)
1895 /*
1896 * It looks like recent chips have a problem with SURFACE_CNTL,
1897 * setting SURF_TRANSLATION_DIS completely disables the
1898 * swapper as well, so we leave it unset now.
1899 */
1900 newmode.surface_cntl = 0;
1901
1902 /* Setup swapping on both apertures, though we currently
1903 * only use aperture 0, enabling swapper on aperture 1
1904 * won't harm
1905 */
1906 switch (mode->bits_per_pixel) {
1907 case 16:
1908 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
1909 newmode.surface_cntl |= NONSURF_AP1_SWP_16BPP;
1910 break;
1911 case 24:
1912 case 32:
1913 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
1914 newmode.surface_cntl |= NONSURF_AP1_SWP_32BPP;
1915 break;
1916 }
1917 #endif
1918
1919 rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
1920 & ~(0x3f)) / 64;
1921
1922 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
1923 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
1924 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
1925 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
1926
1927 newmode.xres = mode->xres;
1928 newmode.yres = mode->yres;
1929
1930 rinfo->bpp = mode->bits_per_pixel;
1931 rinfo->depth = depth;
1932
1933 if (freq > rinfo->pll.ppll_max)
1934 freq = rinfo->pll.ppll_max;
1935 if (freq*12 < rinfo->pll.ppll_min)
1936 freq = rinfo->pll.ppll_min / 12;
1937
1938 {
1939 struct {
1940 int divider;
1941 int bitvalue;
1942 } *post_div,
1943 post_divs[] = {
1944 { 1, 0 },
1945 { 2, 1 },
1946 { 4, 2 },
1947 { 8, 3 },
1948 { 3, 4 },
1949 { 16, 5 },
1950 { 6, 6 },
1951 { 12, 7 },
1952 { 0, 0 },
1953 };
1954
1955 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
1956 rinfo->pll_output_freq = post_div->divider * freq;
1957 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
1958 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
1959 break;
1960 }
1961
1962 rinfo->post_div = post_div->divider;
1963 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
1964 rinfo->pll.ref_clk);
1965 newmode.ppll_ref_div = rinfo->pll.ref_div;
1966 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
1967 }
1968 newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
1969
1970 #ifdef CONFIG_PPC_OF
1971 /* Gross hack for iBook with M7 until I find out a proper fix */
1972 if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
1973 newmode.ppll_div_3 = 0x000600ad;
1974 #endif /* CONFIG_PPC_OF */
1975
1976 RTRACE("post div = 0x%x\n", rinfo->post_div);
1977 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
1978 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
1979
1980 /* DDA */
1981 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
1982 rinfo->pll.ref_div * rinfo->post_div);
1983 xclk_freq = rinfo->pll.xclk;
1984
1985 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
1986
1987 min_bits = min_bits_req(xclk_per_trans);
1988 useable_precision = min_bits + 1;
1989
1990 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
1991 vclk_freq * mode->bits_per_pixel);
1992
1993 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
1994 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
1995 xclk_per_trans) << (11 - useable_precision);
1996 roff = xclk_per_trans_precise * (32 - 4);
1997
1998 RTRACE("ron = %d, roff = %d\n", ron, roff);
1999 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
2000
2001 if ((ron + rinfo->ram.rloop) >= roff) {
2002 printk("radeonfb: error ron out of range\n");
2003 return -EINVAL;
2004 }
2005
2006 newmode.dda_config = (xclk_per_trans_precise |
2007 (useable_precision << 16) |
2008 (rinfo->ram.rloop << 20));
2009 newmode.dda_on_off = (ron << 16) | roff;
2010
2011 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2012 unsigned int hRatio, vRatio;
2013
2014 /* We force the pixel clock to be always enabled. Allowing it
2015 * to be power managed during blanking would save power, but has
2016 * nasty interactions with the 2D engine & sleep code that haven't
2017 * been solved yet. --BenH
2018 */
2019 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2020
2021 if (mode->xres > rinfo->panel_xres)
2022 mode->xres = rinfo->panel_xres;
2023 if (mode->yres > rinfo->panel_yres)
2024 mode->yres = rinfo->panel_yres;
2025
2026 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2027 << HORZ_PANEL_SHIFT);
2028 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2029 << VERT_PANEL_SHIFT);
2030
2031 if (mode->xres != rinfo->panel_xres) {
2032 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2033 rinfo->panel_xres);
2034 newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2035 (newmode.fp_horz_stretch &
2036 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2037 HORZ_AUTO_RATIO_INC)));
2038 newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2039 HORZ_STRETCH_ENABLE);
2040 }
2041 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2042
2043 if (mode->yres != rinfo->panel_yres) {
2044 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2045 rinfo->panel_yres);
2046 newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2047 (newmode.fp_vert_stretch &
2048 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2049 newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2050 VERT_STRETCH_ENABLE);
2051 }
2052 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2053
2054 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2055 ~(FP_SEL_CRTC2 |
2056 FP_RMX_HVSYNC_CONTROL_EN |
2057 FP_DFP_SYNC_SEL |
2058 FP_CRT_SYNC_SEL |
2059 FP_CRTC_LOCK_8DOT |
2060 FP_USE_SHADOW_EN |
2061 FP_CRTC_USE_SHADOW_VEND |
2062 FP_CRT_SYNC_ALT));
2063
2064 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2065 FP_CRTC_DONT_SHADOW_HEND);
2066
2067 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2068 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2069 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2070 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2071
2072 if (primary_mon == MT_LCD) {
2073 newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2074 newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2075 } else {
2076 /* DFP */
2077 newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2078 newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2079 TMDS_ICHCSEL | TMDS_PLL_EN) &
2080 ~(TMDS_PLLRST);
2081 newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2082 }
2083
2084 newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) |
2085 (((mode->xres / 8) - 1) << 16));
2086 newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) |
2087 ((mode->yres - 1) << 16);
2088 newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) |
2089 (hsync_wid << 16) | (h_sync_pol << 23));
2090 newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) |
2091 (vsync_wid << 16) | (v_sync_pol << 23));
2092 }
2093
2094 /* do it! */
2095 if (!rinfo->asleep) {
2096 radeon_write_mode (rinfo, &newmode);
2097 /* (re)initialize the engine */
2098 if (noaccel)
2099 radeon_engine_init (rinfo);
2100
2101 }
2102 /* Update fix */
2103 if (accel)
2104 info->fix.line_length = rinfo->pitch*64;
2105 else
2106 info->fix.line_length = mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8);
2107 info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
2108
2109 #ifdef CONFIG_BOOTX_TEXT
2110 /* Update debug text engine */
2111 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2112 rinfo->depth, info->fix.line_length);
2113 #endif
2114
2115 return 0;
2116 }
2117
2118
2119 static void radeon_write_mode (struct radeonfb_info *rinfo,
2120 struct radeon_regs *mode)
2121 {
2122 int i;
2123 int primary_mon = PRIMARY_MONITOR(rinfo);
2124
2125 radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
2126
2127
2128 if (rinfo->arch == RADEON_M6) {
2129 for (i=0; i<8; i++)
2130 OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
2131 } else {
2132 for (i=0; i<9; i++)
2133 OUTREG(common_regs[i].reg, common_regs[i].val);
2134 }
2135
2136 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2137 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2138 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2139 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2140 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2141 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2142 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2143 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2144 OUTREG(CRTC_OFFSET, 0);
2145 OUTREG(CRTC_OFFSET_CNTL, 0);
2146 OUTREG(CRTC_PITCH, mode->crtc_pitch);
2147
2148 #if defined(__BIG_ENDIAN)
2149 OUTREG(SURFACE_CNTL, mode->surface_cntl);
2150 #endif
2151
2152 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2153 PPLL_DIV_SEL_MASK) {
2154 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2155 }
2156
2157 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2158
2159 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2160 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2161 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2162 }
2163
2164 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2165 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2166 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2167 }
2168
2169 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2170 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2171 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2172 }
2173
2174 OUTPLL(HTOTAL_CNTL, 0);
2175
2176 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2177
2178 // OUTREG(DDA_CONFIG, mode->dda_config);
2179 // OUTREG(DDA_ON_OFF, mode->dda_on_off);
2180
2181 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2182 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2183 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2184 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2185 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2186 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2187 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2188 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2189 OUTREG(TMDS_CRC, mode->tmds_crc);
2190 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2191
2192 if (primary_mon == MT_LCD) {
2193 unsigned int tmp = INREG(LVDS_GEN_CNTL);
2194
2195 mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2196 mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2197
2198 if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2199 (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2200 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2201 } else {
2202 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2203 udelay(1000);
2204 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2205 } else {
2206 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2207 LVDS_BLON);
2208 udelay(1000);
2209 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2210 }
2211 }
2212 }
2213 }
2214
2215 radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
2216
2217 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2218
2219 return;
2220 }
2221
2222 static struct fb_ops radeonfb_ops = {
2223 .owner = THIS_MODULE,
2224 .fb_check_var = radeonfb_check_var,
2225 .fb_set_par = radeonfb_set_par,
2226 .fb_setcolreg = radeonfb_setcolreg,
2227 .fb_pan_display = radeonfb_pan_display,
2228 .fb_blank = radeonfb_blank,
2229 .fb_ioctl = radeonfb_ioctl,
2230 #if 0
2231 .fb_fillrect = radeonfb_fillrect,
2232 .fb_copyarea = radeonfb_copyarea,
2233 .fb_imageblit = radeonfb_imageblit,
2234 .fb_rasterimg = radeonfb_rasterimg,
2235 #else
2236 .fb_fillrect = cfb_fillrect,
2237 .fb_copyarea = cfb_copyarea,
2238 .fb_imageblit = cfb_imageblit,
2239 #endif
2240 .fb_cursor = soft_cursor,
2241 };
2242
2243
2244 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
2245 {
2246 struct fb_info *info;
2247
2248 info = &rinfo->info;
2249
2250 info->currcon = -1;
2251 info->par = rinfo;
2252 info->pseudo_palette = rinfo->pseudo_palette;
2253 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
2254 info->fbops = &radeonfb_ops;
2255 info->screen_base = rinfo->fb_base;
2256
2257 /* Fill fix common fields */
2258 strlcpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
2259 info->fix.smem_start = rinfo->fb_base_phys;
2260 info->fix.smem_len = rinfo->video_ram;
2261 info->fix.type = FB_TYPE_PACKED_PIXELS;
2262 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
2263 info->fix.xpanstep = 8;
2264 info->fix.ypanstep = 1;
2265 info->fix.ywrapstep = 0;
2266 info->fix.type_aux = 0;
2267 info->fix.mmio_start = rinfo->mmio_base_phys;
2268 info->fix.mmio_len = RADEON_REGSIZE;
2269 if (noaccel)
2270 info->fix.accel = FB_ACCEL_NONE;
2271 else
2272 info->fix.accel = FB_ACCEL_ATI_RADEON;
2273
2274 if (radeon_init_disp (rinfo) < 0)
2275 return -1;
2276
2277 return 0;
2278 }
2279
2280
2281 #ifdef CONFIG_PMAC_BACKLIGHT
2282
2283 /* TODO: Dbl check these tables, we don't go up to full ON backlight
2284 * in these, possibly because we noticed MacOS doesn't, but I'd prefer
2285 * having some more official numbers from ATI
2286 */
2287 static int backlight_conv_m6[] = {
2288 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2289 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2290 };
2291 static int backlight_conv_m7[] = {
2292 0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
2293 0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
2294 };
2295
2296 #define BACKLIGHT_LVDS_OFF
2297 #undef BACKLIGHT_DAC_OFF
2298
2299 /* We turn off the LCD completely instead of just dimming the backlight.
2300 * This provides some greater power saving and the display is useless
2301 * without backlight anyway.
2302 */
2303
2304 static int radeon_set_backlight_enable(int on, int level, void *data)
2305 {
2306 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2307 unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2308 int* conv_table;
2309
2310 /* Pardon me for that hack... maybe some day we can figure
2311 * out in what direction backlight should work on a given
2312 * panel ?
2313 */
2314 if ((rinfo->arch == RADEON_M7 || rinfo->arch == RADEON_M9)
2315 && !machine_is_compatible("PowerBook4,3"))
2316 conv_table = backlight_conv_m7;
2317 else
2318 conv_table = backlight_conv_m6;
2319
2320 lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2321 if (on && (level > BACKLIGHT_OFF)) {
2322 lvds_gen_cntl |= LVDS_DIGON;
2323 if (!(lvds_gen_cntl & LVDS_ON)) {
2324 lvds_gen_cntl &= ~LVDS_BLON;
2325 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2326 (void)INREG(LVDS_GEN_CNTL);
2327 mdelay(10);
2328 lvds_gen_cntl |= LVDS_BLON;
2329 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2330 }
2331 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2332 lvds_gen_cntl |= (conv_table[level] <<
2333 LVDS_BL_MOD_LEVEL_SHIFT);
2334 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2335 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2336 } else {
2337 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2338 lvds_gen_cntl |= (conv_table[0] <<
2339 LVDS_BL_MOD_LEVEL_SHIFT);
2340 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2341 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2342 udelay(10);
2343 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2344 }
2345
2346 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2347 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2348 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2349
2350 return 0;
2351 }
2352
2353 static int radeon_set_backlight_level(int level, void *data)
2354 {
2355 return radeon_set_backlight_enable(1, level, data);
2356 }
2357 #endif /* CONFIG_PMAC_BACKLIGHT */
2358
2359
2360 #ifdef CONFIG_PMAC_PBOOK
2361
2362 static u32 dbg_clk;
2363
2364 /*
2365 * Radeon M6 Power Management code. This code currently only supports
2366 * the mobile chips, it's based from some informations provided by ATI
2367 * along with hours of tracing of MacOS drivers
2368 */
2369
2370 static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
2371 {
2372 rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
2373 rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
2374 rinfo->save_regs[2] = INPLL(MCLK_CNTL);
2375 rinfo->save_regs[3] = INPLL(SCLK_CNTL);
2376 rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
2377 rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
2378 rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
2379 rinfo->save_regs[7] = INPLL(MCLK_MISC);
2380 rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
2381
2382 rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
2383 rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
2384 rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
2385 rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
2386 rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
2387 rinfo->save_regs[14] = INREG(BUS_CNTL1);
2388 rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
2389 rinfo->save_regs[16] = INREG(AGP_CNTL);
2390 rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2391 rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) | 0x04000000;
2392 rinfo->save_regs[19] = INREG(GPIOPAD_A);
2393 rinfo->save_regs[20] = INREG(GPIOPAD_EN);
2394 rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
2395 rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
2396 rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
2397 rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
2398 rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
2399 rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
2400 rinfo->save_regs[27] = INREG(GPIO_MONID);
2401 rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
2402
2403 rinfo->save_regs[29] = INREG(SURFACE_CNTL);
2404 rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
2405 rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
2406 rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
2407 rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
2408 }
2409
2410 static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
2411 {
2412 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
2413
2414 OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
2415 OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
2416 OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
2417 OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
2418 OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
2419 OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
2420 OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
2421 OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
2422
2423 OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
2424 OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
2425 OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
2426 OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
2427 OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
2428 OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
2429 OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
2430 OUTREG(AGP_CNTL, rinfo->save_regs[16]);
2431 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
2432 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
2433
2434 // wait VBL before that one ?
2435 OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
2436
2437 OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
2438 OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
2439 OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
2440 OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
2441 OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
2442 OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
2443 OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
2444 OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
2445 OUTREG(GPIO_MONID, rinfo->save_regs[27]);
2446 OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
2447 }
2448
2449 static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
2450 {
2451 OUTREG(GPIOPAD_MASK, 0x0001ffff);
2452 OUTREG(GPIOPAD_EN, 0x00000400);
2453 OUTREG(GPIOPAD_A, 0x00000000);
2454 OUTREG(ZV_LCDPAD_MASK, 0x00000000);
2455 OUTREG(ZV_LCDPAD_EN, 0x00000000);
2456 OUTREG(ZV_LCDPAD_A, 0x00000000);
2457 OUTREG(GPIO_VGA_DDC, 0x00030000);
2458 OUTREG(GPIO_DVI_DDC, 0x00000000);
2459 OUTREG(GPIO_MONID, 0x00030000);
2460 OUTREG(GPIO_CRT2_DDC, 0x00000000);
2461 }
2462
2463 static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
2464 {
2465 //
2466 // u32 reg;
2467 //
2468 // OUTPLL(P2PLL_REF_DIV, 0x0c);
2469 //
2470 // .../... figure out what macos does here
2471 }
2472
2473 static void radeon_pm_low_current(struct radeonfb_info *rinfo)
2474 {
2475 u32 reg;
2476
2477 reg = INREG(BUS_CNTL1);
2478 reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
2479 reg |= BUS_CNTL1_AGPCLK_VALID | (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
2480 OUTREG(BUS_CNTL1, reg);
2481
2482 reg = INPLL(PLL_PWRMGT_CNTL);
2483 reg |= PLL_PWRMGT_CNTL_SPLL_TURNOFF | PLL_PWRMGT_CNTL_PPLL_TURNOFF |
2484 PLL_PWRMGT_CNTL_P2PLL_TURNOFF | PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
2485 reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
2486 reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
2487 OUTPLL(PLL_PWRMGT_CNTL, reg);
2488
2489 // reg = INPLL(TV_PLL_CNTL1);
2490 // reg |= TV_PLL_CNTL1__TVPLL_RESET | TV_PLL_CNTL1__TVPLL_SLEEP;
2491 // OUTPLL(TV_PLL_CNTL1, reg);
2492
2493 reg = INREG(TV_DAC_CNTL);
2494 reg &= ~(TV_DAC_CNTL_BGADJ_MASK |TV_DAC_CNTL_DACADJ_MASK);
2495 reg |=TV_DAC_CNTL_BGSLEEP | TV_DAC_CNTL_RDACPD | TV_DAC_CNTL_GDACPD |
2496 TV_DAC_CNTL_BDACPD |
2497 (8<<TV_DAC_CNTL_BGADJ__SHIFT) | (8<<TV_DAC_CNTL_DACADJ__SHIFT);
2498 OUTREG(TV_DAC_CNTL, reg);
2499
2500 reg = INREG(TMDS_TRANSMITTER_CNTL);
2501 reg &= ~(TMDS_PLL_EN |TMDS_PLLRST);
2502 OUTREG(TMDS_TRANSMITTER_CNTL, reg);
2503
2504 // lvds_pll_cntl = regr32(g, LVDS_PLL_CNTL);
2505 // lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
2506 // lvds_pll_cntl |= LVDS_PLL_CNTL__LVDS_PLL_RESET;
2507 // regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
2508
2509 reg = INREG(DAC_CNTL);
2510 reg &= ~DAC_CMP_EN;
2511 OUTREG(DAC_CNTL, reg);
2512
2513 reg = INREG(DAC_CNTL2);
2514 reg &= ~DAC2_CMP_EN;
2515 OUTREG(DAC_CNTL2, reg);
2516
2517 reg = INREG(TV_DAC_CNTL);
2518 reg &= ~TV_DAC_CNTL_DETECT;
2519 OUTREG(TV_DAC_CNTL, reg);
2520 }
2521
2522 static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
2523 {
2524 /* This code is disabled. It does what is in the pm_init
2525 * function of the MacOS driver code ATI sent me. However,
2526 * it doesn't fix my sleep problem, and is causing other issues
2527 * on wakeup (bascially the machine dying when switching consoles
2528 * I haven't had time to investigate this yet
2529 */
2530 #if 0
2531 u32 disp_misc_cntl;
2532 u32 disp_pwr_man;
2533 u32 temp;
2534
2535 // set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
2536 // TCLK and TEST_MODE to 0
2537 temp = INPLL(CLK_PWRMGT_CNTL);
2538 OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
2539
2540 // Turn on Power Management
2541 temp = INPLL(CLK_PWRMGT_CNTL);
2542 OUTPLL(CLK_PWRMGT_CNTL , temp | 0x00000400);
2543
2544 // Turn off display clock if using mobile chips
2545 temp = INPLL(CLK_PWRMGT_CNTL);
2546 OUTREG(CLK_PWRMGT_CNTL , temp | 0x00100000);
2547
2548 // Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
2549 temp = INPLL(VCLK_ECP_CNTL);
2550 OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
2551
2552 // Force ECP_FORCE_ON to 1
2553 temp = INPLL(VCLK_ECP_CNTL);
2554 OUTPLL(VCLK_ECP_CNTL, temp | 0x00040000);
2555
2556 // Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
2557 temp = INPLL(PIXCLKS_CNTL);
2558 OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
2559
2560 // Forcing SCLK_CNTL to ON
2561 OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) | 0xffff8000 );
2562
2563 // Set PM control over XTALIN pad
2564 temp = INPLL(CLK_PIN_CNTL);
2565 OUTPLL(CLK_PIN_CNTL, temp | 0x00080000);
2566
2567 // Force MCLK and YCLK and MC as dynamic
2568 temp = INPLL(MCLK_CNTL);
2569 OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
2570
2571 // PLL_TURNOFF
2572 temp = INPLL(PLL_PWRMGT_CNTL);
2573 OUTPLL(PLL_PWRMGT_CNTL, temp | 0x0000001f);
2574
2575 // set MOBILE_SU to 1 if M6 or DDR64 is detected
2576 temp = INPLL(PLL_PWRMGT_CNTL);
2577 OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00010000);
2578
2579 // select PM access mode (PM_MODE_SEL) (use ACPI mode)
2580 // temp = INPLL(PLL_PWRMGT_CNTL);
2581 // OUTPLL(PLL_PWRMGT_CNTL, temp | 0x00002000);
2582 temp = INPLL(PLL_PWRMGT_CNTL);
2583 OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
2584
2585 // set DISP_MISC_CNTL register
2586 disp_misc_cntl = INREG(DISP_MISC_CNTL);
2587 disp_misc_cntl &= ~( DISP_MISC_CNTL_SOFT_RESET_GRPH_PP |
2588 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP |
2589 DISP_MISC_CNTL_SOFT_RESET_OV0_PP |
2590 DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK |
2591 DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK |
2592 DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK |
2593 DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP |
2594 DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK |
2595 DISP_MISC_CNTL_SOFT_RESET_LVDS |
2596 DISP_MISC_CNTL_SOFT_RESET_TMDS |
2597 DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS |
2598 DISP_MISC_CNTL_SOFT_RESET_TV);
2599 OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
2600
2601 // set DISP_PWR_MAN register
2602 disp_pwr_man = INREG(DISP_PWR_MAN);
2603 // clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
2604 disp_pwr_man |= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST |
2605 DISP_PWR_MAN_TV_ENABLE_RST |
2606 // DISP_PWR_MAN_AUTO_PWRUP_EN |
2607 DISP_PWR_MAN_DISP_D3_GRPH_RST |
2608 DISP_PWR_MAN_DISP_D3_SUBPIC_RST |
2609 DISP_PWR_MAN_DISP_D3_OV0_RST |
2610 DISP_PWR_MAN_DISP_D1D2_GRPH_RST |
2611 DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST |
2612 DISP_PWR_MAN_DISP_D1D2_OV0_RST);
2613 disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN |
2614 DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN|
2615 DISP_PWR_MAN_DISP_D3_RST |
2616 DISP_PWR_MAN_DISP_D3_REG_RST);
2617 OUTREG(DISP_PWR_MAN, disp_pwr_man);
2618
2619 // clau - 10.24.2000
2620 // - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
2621 // - add in setting for AGP_CNTL b7:0 = 0x20
2622 // - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
2623
2624 // the following settings (two lines) are applied at a later part of this function, only on mobile platform
2625 // requres -mobile flag
2626 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) | 0x04000000);
2627 OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) | 0x80000000);
2628 OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) | 0x20);
2629 OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
2630
2631 // yulee - 12.12.2000
2632 // A12 only
2633 // EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
2634 // ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
2635 // only on mobile platform
2636 OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) | 0x00040000 );
2637
2638 // yulee -12.12.2000
2639 // AGPCLK_VALID@BUS_CNTL1 = 1
2640 // MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
2641 // CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
2642 // CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
2643 // only on mobile platform
2644 OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
2645 OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) | 0x84000000 );
2646 OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
2647
2648 mdelay(100);
2649 #endif
2650
2651 /* Disable CRTCs */
2652 OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2653 OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2654 (void)INREG(CRTC2_GEN_CNTL);
2655 mdelay(17);
2656 }
2657
2658 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2659 {
2660 u16 pwr_cmd;
2661
2662 if (!rinfo->pm_reg)
2663 return;
2664
2665 /* Set the chip into appropriate suspend mode (we use D2,
2666 * D3 would require a compete re-initialization of the chip,
2667 * including PCI config registers, clocks, AGP conf, ...)
2668 */
2669 if (suspend) {
2670 /* According to ATI, we should program V2CLK here, I have
2671 * to verify what's up exactly
2672 */
2673 /* Save some registers */
2674 radeon_pm_save_regs(rinfo);
2675
2676 /* Check that on M7 too, might work might not. M7 may also
2677 * need explicit enabling of PM
2678 */
2679 if (rinfo->arch == RADEON_M6) {
2680 /* Program V2CLK */
2681 radeon_pm_program_v2clk(rinfo);
2682
2683 /* Disable IO PADs */
2684 radeon_pm_disable_iopad(rinfo);
2685
2686 /* Set low current */
2687 radeon_pm_low_current(rinfo);
2688
2689 /* Prepare chip for power management */
2690 radeon_pm_setup_for_suspend(rinfo);
2691
2692 /* Reset the MDLL */
2693 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2694 (void)INPLL(MDLL_RDCKA);
2695 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2696 (void)INPLL(MDLL_RDCKA);
2697 }
2698
2699 /* Switch PCI power managment to D2. */
2700 for (;;) {
2701 pci_read_config_word(
2702 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2703 &pwr_cmd);
2704 if (pwr_cmd & 2)
2705 break;
2706 pci_write_config_word(
2707 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2708 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2709 mdelay(500);
2710 }
2711 } else {
2712 /* Switch back PCI powermanagment to D0 */
2713 mdelay(200);
2714 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2715 mdelay(500);
2716
2717 dbg_clk = INPLL(1);
2718
2719 /* Do we need that on M7 ? */
2720 if (rinfo->arch == RADEON_M6) {
2721 /* Restore the MDLL */
2722 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2723 (void)INPLL(MDLL_CKO);
2724 }
2725
2726 /* Restore some registers */
2727 radeon_pm_restore_regs(rinfo);
2728 }
2729 }
2730
2731 /*
2732 * Save the contents of the framebuffer when we go to sleep,
2733 * and restore it when we wake up again.
2734 */
2735
2736 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2737 {
2738 struct radeonfb_info *rinfo;
2739
2740 for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2741 struct fb_fix_screeninfo fix;
2742 int nb;
2743 struct display *disp;
2744
2745 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2746
2747 switch (rinfo->arch) {
2748 case RADEON_M6:
2749 case RADEON_M7:
2750 case RADEON_M9:
2751 break;
2752 default:
2753 return PBOOK_SLEEP_REFUSE;
2754 }
2755
2756 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2757 nb = fb_display[fg_console].var.yres * fix.line_length;
2758
2759 switch (when) {
2760 case PBOOK_SLEEP_NOW:
2761 acquire_console_sem();
2762 disp->dispsw = &fbcon_dummy;
2763
2764 if (!noaccel) {
2765 /* Make sure engine is reset */
2766 radeon_engine_reset();
2767 radeon_engine_idle();
2768 }
2769
2770 /* Blank display and LCD */
2771 radeonfb_blank(VESA_POWERDOWN+1,
2772 (struct fb_info *)rinfo);
2773
2774 /* Sleep */
2775 rinfo->asleep = 1;
2776 radeon_set_suspend(rinfo, 1);
2777 release_console_sem();
2778
2779 break;
2780 case PBOOK_WAKE:
2781 acquire_console_sem();
2782 /* Wakeup */
2783 radeon_set_suspend(rinfo, 0);
2784
2785 if (!noaccel)
2786 radeon_engine_init(rinfo);
2787 rinfo->asleep = 0;
2788 radeon_set_dispsw(rinfo, disp);
2789 radeon_load_video_mode(rinfo, &disp->var);
2790 do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
2791 (struct fb_info *)rinfo);
2792
2793 radeonfb_blank(0, (struct fb_info *)rinfo);
2794 release_console_sem();
2795 printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
2796 break;
2797 }
2798 }
2799
2800 return PBOOK_SLEEP_OK;
2801 }
2802
2803 #endif /* CONFIG_PMAC_PBOOK */
2804
2805 static int radeonfb_pci_register (struct pci_dev *pdev,
2806 const struct pci_device_id *ent)
2807 {
2808 struct radeonfb_info *rinfo;
2809 struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
2810 u32 tmp;
2811
2812 RTRACE("radeonfb_pci_register BEGIN\n");
2813
2814 /* Enable device in PCI config */
2815 if (pci_enable_device(pdev) != 0) {
2816 printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
2817 return -ENODEV;
2818 }
2819
2820 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
2821 if (!rinfo) {
2822 printk ("radeonfb: could not allocate memory\n");
2823 return -ENODEV;
2824 }
2825
2826 memset (rinfo, 0, sizeof (struct radeonfb_info));
2827 //info = &rinfo->info;
2828 rinfo->pdev = pdev;
2829 strcpy(rinfo->name, rci->name);
2830 rinfo->arch = rci->arch;
2831
2832 /* Set base addrs */
2833 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
2834 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
2835
2836 /* request the mem regions */
2837 if (!request_mem_region (rinfo->fb_base_phys,
2838 pci_resource_len(pdev, 0), "radeonfb")) {
2839 printk ("radeonfb: cannot reserve FB region\n");
2840 kfree (rinfo);
2841 return -ENODEV;
2842 }
2843
2844 if (!request_mem_region (rinfo->mmio_base_phys,
2845 pci_resource_len(pdev, 2), "radeonfb")) {
2846 printk ("radeonfb: cannot reserve MMIO region\n");
2847 release_mem_region (rinfo->fb_base_phys,
2848 pci_resource_len(pdev, 0));
2849 kfree (rinfo);
2850 return -ENODEV;
2851 }
2852
2853 /* map the regions */
2854 rinfo->mmio_base = ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
2855 if (!rinfo->mmio_base) {
2856 printk ("radeonfb: cannot map MMIO\n");
2857 release_mem_region (rinfo->mmio_base_phys,
2858 pci_resource_len(pdev, 2));
2859 release_mem_region (rinfo->fb_base_phys,
2860 pci_resource_len(pdev, 0));
2861 kfree (rinfo);
2862 return -ENODEV;
2863 }
2864
2865 rinfo->chipset = pdev->device;
2866
2867 switch (rinfo->arch) {
2868 case RADEON_R100:
2869 rinfo->hasCRTC2 = 0;
2870 break;
2871 default:
2872 /* all the rest have it */
2873 rinfo->hasCRTC2 = 1;
2874 break;
2875 }
2876 #if 0
2877 if (rinfo->arch == RADEON_M7) {
2878 /*
2879 * Noticed some errors in accel with M7, will have to work these out...
2880 */
2881 noaccel = 1;
2882 }
2883 #endif
2884 if (mirror)
2885 printk("radeonfb: mirroring display to CRT\n");
2886
2887 /* framebuffer size */
2888 tmp = INREG(CONFIG_MEMSIZE);
2889
2890 /* mem size is bits [28:0], mask off the rest */
2891 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
2892
2893 /* ram type */
2894 tmp = INREG(MEM_SDRAM_MODE_REG);
2895 switch ((MEM_CFG_TYPE & tmp) >> 30) {
2896 case 0:
2897 /* SDR SGRAM (2:1) */
2898 strcpy(rinfo->ram_type, "SDR SGRAM");
2899 rinfo->ram.ml = 4;
2900 rinfo->ram.mb = 4;
2901 rinfo->ram.trcd = 1;
2902 rinfo->ram.trp = 2;
2903 rinfo->ram.twr = 1;
2904 rinfo->ram.cl = 2;
2905 rinfo->ram.loop_latency = 16;
2906 rinfo->ram.rloop = 16;
2907
2908 break;
2909 case 1:
2910 /* DDR SGRAM */
2911 strcpy(rinfo->ram_type, "DDR SGRAM");
2912 rinfo->ram.ml = 4;
2913 rinfo->ram.mb = 4;
2914 rinfo->ram.trcd = 3;
2915 rinfo->ram.trp = 3;
2916 rinfo->ram.twr = 2;
2917 rinfo->ram.cl = 3;
2918 rinfo->ram.tr2w = 1;
2919 rinfo->ram.loop_latency = 16;
2920 rinfo->ram.rloop = 16;
2921
2922 break;
2923 default:
2924 /* 64-bit SDR SGRAM */
2925 strcpy(rinfo->ram_type, "SDR SGRAM 64");
2926 rinfo->ram.ml = 4;
2927 rinfo->ram.mb = 8;
2928 rinfo->ram.trcd = 3;
2929 rinfo->ram.trp = 3;
2930 rinfo->ram.twr = 1;
2931 rinfo->ram.cl = 3;
2932 rinfo->ram.tr2w = 1;
2933 rinfo->ram.loop_latency = 17;
2934 rinfo->ram.rloop = 17;
2935
2936 break;
2937 }
2938
2939 rinfo->bios_seg = radeon_find_rom(rinfo);
2940 radeon_get_pllinfo(rinfo, rinfo->bios_seg);
2941
2942 /*
2943 * Hack to get around some busted production M6's
2944 * reporting no ram
2945 */
2946 if (rinfo->video_ram == 0) {
2947 switch (pdev->device) {
2948 case PCI_DEVICE_ID_ATI_RADEON_LY:
2949 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2950 rinfo->video_ram = 8192 * 1024;
2951 break;
2952 default:
2953 break;
2954 }
2955 }
2956
2957
2958 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
2959
2960 #if !defined(__powerpc__)
2961 radeon_get_moninfo(rinfo);
2962 #else
2963 switch (pdev->device) {
2964 case PCI_DEVICE_ID_ATI_RADEON_LW:
2965 case PCI_DEVICE_ID_ATI_RADEON_LX:
2966 case PCI_DEVICE_ID_ATI_RADEON_LY:
2967 case PCI_DEVICE_ID_ATI_RADEON_LZ:
2968 rinfo->dviDisp_type = MT_LCD;
2969 break;
2970 default:
2971 radeon_get_moninfo(rinfo);
2972 break;
2973 }
2974 #endif
2975
2976 radeon_get_EDID(rinfo);
2977
2978 if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
2979 (rinfo->crtDisp_type == MT_DFP)) {
2980 if (!radeon_get_dfpinfo(rinfo)) {
2981 iounmap(rinfo->mmio_base);
2982 release_mem_region (rinfo->mmio_base_phys,
2983 pci_resource_len(pdev, 2));
2984 release_mem_region (rinfo->fb_base_phys,
2985 pci_resource_len(pdev, 0));
2986 kfree (rinfo);
2987 return -ENODEV;
2988 }
2989 }
2990
2991 rinfo->fb_base = ioremap (rinfo->fb_base_phys, rinfo->video_ram);
2992 if (!rinfo->fb_base) {
2993 printk ("radeonfb: cannot map FB\n");
2994 iounmap(rinfo->mmio_base);
2995 release_mem_region (rinfo->mmio_base_phys,
2996 pci_resource_len(pdev, 2));
2997 release_mem_region (rinfo->fb_base_phys,
2998 pci_resource_len(pdev, 0));
2999 kfree (rinfo);
3000 return -ENODEV;
3001 }
3002
3003 /* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
3004 * driver setup here.
3005 *
3006 * On PPC, OF based cards setup the internal memory
3007 * mapping in strange ways. We change it so that the
3008 * framebuffer is mapped at 0 and given half of the card's
3009 * address space (2Gb). AGP is mapped high (0xe0000000) and
3010 * can use up to 512Mb. Once DRI is fully implemented, we
3011 * will have to setup the PCI remapper to remap the agp_special_page
3012 * memory page somewhere between those regions so that the card
3013 * use a normal PCI bus master cycle to access the ring read ptr.
3014 * --BenH.
3015 */
3016 #ifdef CONFIG_ALL_PPC
3017 if (rinfo->hasCRTC2)
3018 OUTREG(CRTC2_GEN_CNTL,
3019 (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
3020 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
3021 OUTREG(MC_FB_LOCATION, 0x7fff0000);
3022 OUTREG(MC_AGP_LOCATION, 0xffffe000);
3023 OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
3024 if (rinfo->hasCRTC2)
3025 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
3026 OUTREG(SRC_OFFSET, 0x00000000);
3027 OUTREG(DST_OFFSET, 0x00000000);
3028 mdelay(10);
3029 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
3030 #endif /* CONFIG_ALL_PPC */
3031
3032 /* save current mode regs before we switch into the new one
3033 * so we can restore this upon __exit
3034 */
3035 radeon_save_state (rinfo, &rinfo->init_state);
3036
3037 /* set all the vital stuff */
3038 radeon_set_fbinfo (rinfo);
3039
3040 pci_set_drvdata(pdev, rinfo);
3041 rinfo->next = board_list;
3042 board_list = rinfo;
3043
3044 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
3045 printk ("radeonfb: could not register framebuffer\n");
3046 iounmap(rinfo->fb_base);
3047 iounmap(rinfo->mmio_base);
3048 release_mem_region (rinfo->mmio_base_phys,
3049 pci_resource_len(pdev, 2));
3050 release_mem_region (rinfo->fb_base_phys,
3051 pci_resource_len(pdev, 0));
3052 kfree (rinfo);
3053 return -ENODEV;
3054 }
3055
3056 #ifdef CONFIG_MTRR
3057 rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
3058 rinfo->video_ram,
3059 MTRR_TYPE_WRCOMB, 1);
3060 #endif
3061
3062 #ifdef CONFIG_PMAC_BACKLIGHT
3063 if (rinfo->dviDisp_type == MT_LCD)
3064 register_backlight_controller(&radeon_backlight_controller,
3065 rinfo, "ati");
3066 #endif
3067
3068 #ifdef CONFIG_PMAC_PBOOK
3069 if (rinfo->dviDisp_type == MT_LCD) {
3070 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
3071 pmu_register_sleep_notifier(&radeon_sleep_notifier);
3072 }
3073 #endif
3074
3075 printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
3076 (rinfo->video_ram/(1024*1024)));
3077
3078 if (rinfo->hasCRTC2) {
3079 printk("radeonfb: DVI port %s monitor connected\n",
3080 GET_MON_NAME(rinfo->dviDisp_type));
3081 printk("radeonfb: CRT port %s monitor connected\n",
3082 GET_MON_NAME(rinfo->crtDisp_type));
3083 } else {
3084 printk("radeonfb: CRT port %s monitor connected\n",
3085 GET_MON_NAME(rinfo->crtDisp_type));
3086 }
3087
3088 RTRACE("radeonfb_pci_register END\n");
3089
3090 return 0;
3091 }
3092
3093
3094
3095 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
3096 {
3097 struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
3098
3099 if (!rinfo)
3100 return;
3101
3102 /* restore original state
3103 *
3104 * Doesn't quite work yet, possibly because of the PPC hacking
3105 * I do on startup, disable for now. --BenH
3106 */
3107 radeon_write_mode (rinfo, &rinfo->init_state);
3108
3109 #ifdef CONFIG_MTRR
3110 if (rinfo->mtrr_hdl >= 0)
3111 mtrr_del(rinfo->mtrr_hdl, 0, 0);
3112 #endif
3113
3114 unregister_framebuffer ((struct fb_info *) rinfo);
3115
3116 iounmap(rinfo->mmio_base);
3117 iounmap(rinfo->fb_base);
3118
3119 release_mem_region (rinfo->mmio_base_phys,
3120 pci_resource_len(pdev, 2));
3121 release_mem_region (rinfo->fb_base_phys,
3122 pci_resource_len(pdev, 0));
3123
3124 kfree (rinfo);
3125 }
3126
3127
3128 static struct pci_driver radeonfb_driver = {
3129 .name = "radeonfb",
3130 .id_table = radeonfb_pci_table,
3131 .probe = radeonfb_pci_register,
3132 .remove = __devexit_p(radeonfb_pci_unregister),
3133 };
3134
3135 int __init radeonfb_old_setup (char *options);
3136
3137 int __init radeonfb_old_init (void)
3138 {
3139 #ifndef MODULE
3140 char *option = NULL;
3141
3142 if (fb_get_options("radeonfb_old", &option))
3143 return -ENODEV;
3144 radeonfb_old_setup(option);
3145 #endif
3146 return pci_module_init (&radeonfb_driver);
3147 }
3148
3149
3150 void __exit radeonfb_old_exit (void)
3151 {
3152 pci_unregister_driver (&radeonfb_driver);
3153 }
3154
3155
3156 int __init radeonfb_old_setup (char *options)
3157 {
3158 char *this_opt;
3159
3160 if (!options || !*options)
3161 return 0;
3162
3163 while ((this_opt = strsep (&options, ",")) != NULL) {
3164 if (!*this_opt)
3165 continue;
3166 if (!strncmp(this_opt, "noaccel", 7)) {
3167 noaccel = 1;
3168 } else if (!strncmp(this_opt, "mirror", 6)) {
3169 mirror = 1;
3170 } else if (!strncmp(this_opt, "dfp", 3)) {
3171 force_dfp = 1;
3172 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
3173 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
3174 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3175 nomtrr = 1;
3176 } else
3177 mode_option = this_opt;
3178 }
3179
3180 return 0;
3181 }
3182
3183 module_init(radeonfb_old_init);
3184
3185 #ifdef MODULE
3186 module_exit(radeonfb_old_exit);
3187 #endif
3188
3189
3190 MODULE_AUTHOR("Ani Joshi");
3191 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
3192 MODULE_LICENSE("GPL");
MOXA 2.6.9 from sdlinux-moxaart.tgz