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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / video / pxafb.c
blob3e2bb2d887ac1f7e6ddba766325460dbb08cd562
1 /*
2 * linux/drivers/video/pxafb.c
3 *
4 * Copyright (C) 1999 Eric A. Thomas.
5 * Copyright (C) 2004 Jean-Frederic Clere.
6 * Copyright (C) 2004 Ian Campbell.
7 * Copyright (C) 2004 Jeff Lackey.
8 * Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
9 * which in turn is
10 * Based on acornfb.c Copyright (C) Russell King.
11 *
12 * This file is subject to the terms and conditions of the GNU General Public
13 * License. See the file COPYING in the main directory of this archive for
14 * more details.
15 *
16 * Intel PXA250/210 LCD Controller Frame Buffer Driver
17 *
18 * Please direct your questions and comments on this driver to the following
19 * email address:
20 *
21 * linux-arm-kernel@lists.arm.linux.org.uk
22 *
23 */
24
25 #include <linux/config.h>
26 #include <linux/module.h>
27 #include <linux/moduleparam.h>
28 #include <linux/kernel.h>
29 #include <linux/sched.h>
30 #include <linux/errno.h>
31 #include <linux/string.h>
32 #include <linux/interrupt.h>
33 #include <linux/slab.h>
34 #include <linux/fb.h>
35 #include <linux/delay.h>
36 #include <linux/init.h>
37 #include <linux/ioport.h>
38 #include <linux/cpufreq.h>
39 #include <linux/device.h>
40 #include <linux/dma-mapping.h>
41
42 #include <asm/hardware.h>
43 #include <asm/io.h>
44 #include <asm/irq.h>
45 #include <asm/uaccess.h>
46 #include <asm/arch/pxa-regs.h>
47 #include <asm/arch/bitfield.h>
48 #include <asm/arch/pxafb.h>
49
50 /*
51 * Complain if VAR is out of range.
52 */
53 #define DEBUG_VAR 1
54
55 #include "pxafb.h"
56
57 /* Bits which should not be set in machine configuration structures */
58 #define LCCR0_INVALID_CONFIG_MASK (LCCR0_OUM|LCCR0_BM|LCCR0_QDM|LCCR0_DIS|LCCR0_EFM|LCCR0_IUM|LCCR0_SFM|LCCR0_LDM|LCCR0_ENB)
59 #define LCCR3_INVALID_CONFIG_MASK (LCCR3_HSP|LCCR3_VSP|LCCR3_PCD|LCCR3_BPP)
60
61 static void (*pxafb_backlight_power)(int);
62 static void (*pxafb_lcd_power)(int);
63
64 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *);
65 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
66
67 #ifdef CONFIG_FB_PXA_PARAMETERS
68 #define PXAFB_OPTIONS_SIZE 256
69 static char g_options[PXAFB_OPTIONS_SIZE] __initdata = "";
70 #endif
71
72 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
73 {
74 unsigned long flags;
75
76 local_irq_save(flags);
77 /*
78 * We need to handle two requests being made at the same time.
79 * There are two important cases:
80 * 1. When we are changing VT (C_REENABLE) while unblanking (C_ENABLE)
81 * We must perform the unblanking, which will do our REENABLE for us.
82 * 2. When we are blanking, but immediately unblank before we have
83 * blanked. We do the "REENABLE" thing here as well, just to be sure.
84 */
85 if (fbi->task_state == C_ENABLE && state == C_REENABLE)
86 state = (u_int) -1;
87 if (fbi->task_state == C_DISABLE && state == C_ENABLE)
88 state = C_REENABLE;
89
90 if (state != (u_int)-1) {
91 fbi->task_state = state;
92 schedule_work(&fbi->task);
93 }
94 local_irq_restore(flags);
95 }
96
97 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
98 {
99 chan &= 0xffff;
100 chan >>= 16 - bf->length;
101 return chan << bf->offset;
102 }
103
104 static int
105 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
106 u_int trans, struct fb_info *info)
107 {
108 struct pxafb_info *fbi = (struct pxafb_info *)info;
109 u_int val, ret = 1;
110
111 if (regno < fbi->palette_size) {
112 if (fbi->fb.var.grayscale) {
113 val = ((blue >> 8) & 0x00ff);
114 } else {
115 val = ((red >> 0) & 0xf800);
116 val |= ((green >> 5) & 0x07e0);
117 val |= ((blue >> 11) & 0x001f);
118 }
119 fbi->palette_cpu[regno] = val;
120 ret = 0;
121 }
122 return ret;
123 }
124
125 static int
126 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
127 u_int trans, struct fb_info *info)
128 {
129 struct pxafb_info *fbi = (struct pxafb_info *)info;
130 unsigned int val;
131 int ret = 1;
132
133 /*
134 * If inverse mode was selected, invert all the colours
135 * rather than the register number. The register number
136 * is what you poke into the framebuffer to produce the
137 * colour you requested.
138 */
139 if (fbi->cmap_inverse) {
140 red = 0xffff - red;
141 green = 0xffff - green;
142 blue = 0xffff - blue;
143 }
144
145 /*
146 * If greyscale is true, then we convert the RGB value
147 * to greyscale no matter what visual we are using.
148 */
149 if (fbi->fb.var.grayscale)
150 red = green = blue = (19595 * red + 38470 * green +
151 7471 * blue) >> 16;
152
153 switch (fbi->fb.fix.visual) {
154 case FB_VISUAL_TRUECOLOR:
155 /*
156 * 16-bit True Colour. We encode the RGB value
157 * according to the RGB bitfield information.
158 */
159 if (regno < 16) {
160 u32 *pal = fbi->fb.pseudo_palette;
161
162 val = chan_to_field(red, &fbi->fb.var.red);
163 val |= chan_to_field(green, &fbi->fb.var.green);
164 val |= chan_to_field(blue, &fbi->fb.var.blue);
165
166 pal[regno] = val;
167 ret = 0;
168 }
169 break;
170
171 case FB_VISUAL_STATIC_PSEUDOCOLOR:
172 case FB_VISUAL_PSEUDOCOLOR:
173 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
174 break;
175 }
176
177 return ret;
178 }
179
180 /*
181 * pxafb_bpp_to_lccr3():
182 * Convert a bits per pixel value to the correct bit pattern for LCCR3
183 */
184 static int pxafb_bpp_to_lccr3(struct fb_var_screeninfo *var)
185 {
186 int ret = 0;
187 switch (var->bits_per_pixel) {
188 case 1: ret = LCCR3_1BPP; break;
189 case 2: ret = LCCR3_2BPP; break;
190 case 4: ret = LCCR3_4BPP; break;
191 case 8: ret = LCCR3_8BPP; break;
192 case 16: ret = LCCR3_16BPP; break;
193 }
194 return ret;
195 }
196
197 #ifdef CONFIG_CPU_FREQ
198 /*
199 * pxafb_display_dma_period()
200 * Calculate the minimum period (in picoseconds) between two DMA
201 * requests for the LCD controller. If we hit this, it means we're
202 * doing nothing but LCD DMA.
203 */
204 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
205 {
206 /*
207 * Period = pixclock * bits_per_byte * bytes_per_transfer
208 * / memory_bits_per_pixel;
209 */
210 return var->pixclock * 8 * 16 / var->bits_per_pixel;
211 }
212
213 extern unsigned int get_clk_frequency_khz(int info);
214 #endif
215
216 /*
217 * pxafb_check_var():
218 * Get the video params out of 'var'. If a value doesn't fit, round it up,
219 * if it's too big, return -EINVAL.
220 *
221 * Round up in the following order: bits_per_pixel, xres,
222 * yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
223 * bitfields, horizontal timing, vertical timing.
224 */
225 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
226 {
227 struct pxafb_info *fbi = (struct pxafb_info *)info;
228
229 if (var->xres < MIN_XRES)
230 var->xres = MIN_XRES;
231 if (var->yres < MIN_YRES)
232 var->yres = MIN_YRES;
233 if (var->xres > fbi->max_xres)
234 var->xres = fbi->max_xres;
235 if (var->yres > fbi->max_yres)
236 var->yres = fbi->max_yres;
237 var->xres_virtual =
238 max(var->xres_virtual, var->xres);
239 var->yres_virtual =
240 max(var->yres_virtual, var->yres);
241
242 /*
243 * Setup the RGB parameters for this display.
244 *
245 * The pixel packing format is described on page 7-11 of the
246 * PXA2XX Developer's Manual.
247 */
248 if (var->bits_per_pixel == 16) {
249 var->red.offset = 11; var->red.length = 5;
250 var->green.offset = 5; var->green.length = 6;
251 var->blue.offset = 0; var->blue.length = 5;
252 var->transp.offset = var->transp.length = 0;
253 } else {
254 var->red.offset = var->green.offset = var->blue.offset = var->transp.offset = 0;
255 var->red.length = 8;
256 var->green.length = 8;
257 var->blue.length = 8;
258 var->transp.length = 0;
259 }
260
261 #ifdef CONFIG_CPU_FREQ
262 DPRINTK("dma period = %d ps, clock = %d kHz\n",
263 pxafb_display_dma_period(var),
264 get_clk_frequency_khz(0));
265 #endif
266
267 return 0;
268 }
269
270 static inline void pxafb_set_truecolor(u_int is_true_color)
271 {
272 DPRINTK("true_color = %d\n", is_true_color);
273 // do your machine-specific setup if needed
274 }
275
276 /*
277 * pxafb_set_par():
278 * Set the user defined part of the display for the specified console
279 */
280 static int pxafb_set_par(struct fb_info *info)
281 {
282 struct pxafb_info *fbi = (struct pxafb_info *)info;
283 struct fb_var_screeninfo *var = &info->var;
284 unsigned long palette_mem_size;
285
286 DPRINTK("set_par\n");
287
288 if (var->bits_per_pixel == 16)
289 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
290 else if (!fbi->cmap_static)
291 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
292 else {
293 /*
294 * Some people have weird ideas about wanting static
295 * pseudocolor maps. I suspect their user space
296 * applications are broken.
297 */
298 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
299 }
300
301 fbi->fb.fix.line_length = var->xres_virtual *
302 var->bits_per_pixel / 8;
303 if (var->bits_per_pixel == 16)
304 fbi->palette_size = 0;
305 else
306 fbi->palette_size = var->bits_per_pixel == 1 ? 4 : 1 << var->bits_per_pixel;
307
308 palette_mem_size = fbi->palette_size * sizeof(u16);
309
310 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
311
312 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
313 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
314
315 /*
316 * Set (any) board control register to handle new color depth
317 */
318 pxafb_set_truecolor(fbi->fb.fix.visual == FB_VISUAL_TRUECOLOR);
319
320 if (fbi->fb.var.bits_per_pixel == 16)
321 fb_dealloc_cmap(&fbi->fb.cmap);
322 else
323 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
324
325 pxafb_activate_var(var, fbi);
326
327 return 0;
328 }
329
330 /*
331 * Formal definition of the VESA spec:
332 * On
333 * This refers to the state of the display when it is in full operation
334 * Stand-By
335 * This defines an optional operating state of minimal power reduction with
336 * the shortest recovery time
337 * Suspend
338 * This refers to a level of power management in which substantial power
339 * reduction is achieved by the display. The display can have a longer
340 * recovery time from this state than from the Stand-by state
341 * Off
342 * This indicates that the display is consuming the lowest level of power
343 * and is non-operational. Recovery from this state may optionally require
344 * the user to manually power on the monitor
345 *
346 * Now, the fbdev driver adds an additional state, (blank), where they
347 * turn off the video (maybe by colormap tricks), but don't mess with the
348 * video itself: think of it semantically between on and Stand-By.
349 *
350 * So here's what we should do in our fbdev blank routine:
351 *
352 * VESA_NO_BLANKING (mode 0) Video on, front/back light on
353 * VESA_VSYNC_SUSPEND (mode 1) Video on, front/back light off
354 * VESA_HSYNC_SUSPEND (mode 2) Video on, front/back light off
355 * VESA_POWERDOWN (mode 3) Video off, front/back light off
356 *
357 * This will match the matrox implementation.
358 */
359
360 /*
361 * pxafb_blank():
362 * Blank the display by setting all palette values to zero. Note, the
363 * 16 bpp mode does not really use the palette, so this will not
364 * blank the display in all modes.
365 */
366 static int pxafb_blank(int blank, struct fb_info *info)
367 {
368 struct pxafb_info *fbi = (struct pxafb_info *)info;
369 int i;
370
371 DPRINTK("pxafb_blank: blank=%d\n", blank);
372
373 switch (blank) {
374 case VESA_POWERDOWN:
375 case VESA_VSYNC_SUSPEND:
376 case VESA_HSYNC_SUSPEND:
377 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
378 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
379 for (i = 0; i < fbi->palette_size; i++)
380 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
381
382 pxafb_schedule_work(fbi, C_DISABLE);
383 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
384 break;
385
386 case VESA_NO_BLANKING:
387 //TODO if (pxafb_blank_helper) pxafb_blank_helper(blank);
388 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
389 fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
390 fb_set_cmap(&fbi->fb.cmap, info);
391 pxafb_schedule_work(fbi, C_ENABLE);
392 }
393 return 0;
394 }
395
396 static struct fb_ops pxafb_ops = {
397 .owner = THIS_MODULE,
398 .fb_check_var = pxafb_check_var,
399 .fb_set_par = pxafb_set_par,
400 .fb_setcolreg = pxafb_setcolreg,
401 .fb_fillrect = cfb_fillrect,
402 .fb_copyarea = cfb_copyarea,
403 .fb_imageblit = cfb_imageblit,
404 .fb_blank = pxafb_blank,
405 .fb_cursor = soft_cursor,
406 };
407
408 /*
409 * Calculate the PCD value from the clock rate (in picoseconds).
410 * We take account of the PPCR clock setting.
411 * From PXA Developer's Manual:
412 *
413 * PixelClock = LCLK
414 * -------------
415 * 2 ( PCD + 1 )
416 *
417 * PCD = LCLK
418 * ------------- - 1
419 * 2(PixelClock)
420 *
421 * Where:
422 * LCLK = LCD/Memory Clock
423 * PCD = LCCR3[7:0]
424 *
425 * PixelClock here is in Hz while the pixclock argument given is the
426 * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
427 *
428 * The function get_lclk_frequency_10khz returns LCLK in units of
429 * 10khz. Calling the result of this function lclk gives us the
430 * following
431 *
432 * PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
433 * -------------------------------------- - 1
434 * 2
435 *
436 * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
437 */
438 static inline unsigned int get_pcd(unsigned int pixclock)
439 {
440 unsigned long long pcd;
441
442 /* FIXME: Need to take into account Double Pixel Clock mode
443 * (DPC) bit? or perhaps set it based on the various clock
444 * speeds */
445
446 pcd = (unsigned long long)get_lcdclk_frequency_10khz() * pixclock;
447 pcd /= 100000000 * 2;
448 /* no need for this, since we should subtract 1 anyway. they cancel */
449 /* pcd += 1; */ /* make up for integer math truncations */
450 return (unsigned int)pcd;
451 }
452
453 /*
454 * pxafb_activate_var():
455 * Configures LCD Controller based on entries in var parameter. Settings are
456 * only written to the controller if changes were made.
457 */
458 static int pxafb_activate_var(struct fb_var_screeninfo *var, struct pxafb_info *fbi)
459 {
460 struct pxafb_lcd_reg new_regs;
461 u_long flags;
462 u_int lines_per_panel, pcd = get_pcd(var->pixclock);
463
464 DPRINTK("Configuring PXA LCD\n");
465
466 DPRINTK("var: xres=%d hslen=%d lm=%d rm=%d\n",
467 var->xres, var->hsync_len,
468 var->left_margin, var->right_margin);
469 DPRINTK("var: yres=%d vslen=%d um=%d bm=%d\n",
470 var->yres, var->vsync_len,
471 var->upper_margin, var->lower_margin);
472 DPRINTK("var: pixclock=%d pcd=%d\n", var->pixclock, pcd);
473
474 #if DEBUG_VAR
475 if (var->xres < 16 || var->xres > 1024)
476 printk(KERN_ERR "%s: invalid xres %d\n",
477 fbi->fb.fix.id, var->xres);
478 switch(var->bits_per_pixel) {
479 case 1:
480 case 2:
481 case 4:
482 case 8:
483 case 16:
484 break;
485 default:
486 printk(KERN_ERR "%s: invalid bit depth %d\n",
487 fbi->fb.fix.id, var->bits_per_pixel);
488 break;
489 }
490 if (var->hsync_len < 1 || var->hsync_len > 64)
491 printk(KERN_ERR "%s: invalid hsync_len %d\n",
492 fbi->fb.fix.id, var->hsync_len);
493 if (var->left_margin < 1 || var->left_margin > 255)
494 printk(KERN_ERR "%s: invalid left_margin %d\n",
495 fbi->fb.fix.id, var->left_margin);
496 if (var->right_margin < 1 || var->right_margin > 255)
497 printk(KERN_ERR "%s: invalid right_margin %d\n",
498 fbi->fb.fix.id, var->right_margin);
499 if (var->yres < 1 || var->yres > 1024)
500 printk(KERN_ERR "%s: invalid yres %d\n",
501 fbi->fb.fix.id, var->yres);
502 if (var->vsync_len < 1 || var->vsync_len > 64)
503 printk(KERN_ERR "%s: invalid vsync_len %d\n",
504 fbi->fb.fix.id, var->vsync_len);
505 if (var->upper_margin < 0 || var->upper_margin > 255)
506 printk(KERN_ERR "%s: invalid upper_margin %d\n",
507 fbi->fb.fix.id, var->upper_margin);
508 if (var->lower_margin < 0 || var->lower_margin > 255)
509 printk(KERN_ERR "%s: invalid lower_margin %d\n",
510 fbi->fb.fix.id, var->lower_margin);
511 #endif
512
513 new_regs.lccr0 = fbi->lccr0 |
514 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
515 LCCR0_QDM | LCCR0_BM | LCCR0_OUM);
516
517 new_regs.lccr1 =
518 LCCR1_DisWdth(var->xres) +
519 LCCR1_HorSnchWdth(var->hsync_len) +
520 LCCR1_BegLnDel(var->left_margin) +
521 LCCR1_EndLnDel(var->right_margin);
522
523 /*
524 * If we have a dual scan LCD, we need to halve
525 * the YRES parameter.
526 */
527 lines_per_panel = var->yres;
528 if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
529 lines_per_panel /= 2;
530
531 new_regs.lccr2 =
532 LCCR2_DisHght(lines_per_panel) +
533 LCCR2_VrtSnchWdth(var->vsync_len) +
534 LCCR2_BegFrmDel(var->upper_margin) +
535 LCCR2_EndFrmDel(var->lower_margin);
536
537 new_regs.lccr3 = fbi->lccr3 |
538 pxafb_bpp_to_lccr3(var) |
539 (var->sync & FB_SYNC_HOR_HIGH_ACT ? LCCR3_HorSnchH : LCCR3_HorSnchL) |
540 (var->sync & FB_SYNC_VERT_HIGH_ACT ? LCCR3_VrtSnchH : LCCR3_VrtSnchL);
541
542 if (pcd)
543 new_regs.lccr3 |= LCCR3_PixClkDiv(pcd);
544
545 DPRINTK("nlccr0 = 0x%08x\n", new_regs.lccr0);
546 DPRINTK("nlccr1 = 0x%08x\n", new_regs.lccr1);
547 DPRINTK("nlccr2 = 0x%08x\n", new_regs.lccr2);
548 DPRINTK("nlccr3 = 0x%08x\n", new_regs.lccr3);
549
550 /* Update shadow copy atomically */
551 local_irq_save(flags);
552
553 /* setup dma descriptors */
554 fbi->dmadesc_fblow_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 3*16);
555 fbi->dmadesc_fbhigh_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 2*16);
556 fbi->dmadesc_palette_cpu = (struct pxafb_dma_descriptor *)((unsigned int)fbi->palette_cpu - 1*16);
557
558 fbi->dmadesc_fblow_dma = fbi->palette_dma - 3*16;
559 fbi->dmadesc_fbhigh_dma = fbi->palette_dma - 2*16;
560 fbi->dmadesc_palette_dma = fbi->palette_dma - 1*16;
561
562 #define BYTES_PER_PANEL (lines_per_panel * fbi->fb.fix.line_length)
563
564 /* populate descriptors */
565 fbi->dmadesc_fblow_cpu->fdadr = fbi->dmadesc_fblow_dma;
566 fbi->dmadesc_fblow_cpu->fsadr = fbi->screen_dma + BYTES_PER_PANEL;
567 fbi->dmadesc_fblow_cpu->fidr = 0;
568 fbi->dmadesc_fblow_cpu->ldcmd = BYTES_PER_PANEL;
569
570 fbi->fdadr1 = fbi->dmadesc_fblow_dma; /* only used in dual-panel mode */
571
572 fbi->dmadesc_fbhigh_cpu->fsadr = fbi->screen_dma;
573 fbi->dmadesc_fbhigh_cpu->fidr = 0;
574 fbi->dmadesc_fbhigh_cpu->ldcmd = BYTES_PER_PANEL;
575
576 fbi->dmadesc_palette_cpu->fsadr = fbi->palette_dma;
577 fbi->dmadesc_palette_cpu->fidr = 0;
578 fbi->dmadesc_palette_cpu->ldcmd = (fbi->palette_size * 2) | LDCMD_PAL;
579
580 if (var->bits_per_pixel == 16) {
581 /* palette shouldn't be loaded in true-color mode */
582 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
583 fbi->fdadr0 = fbi->dmadesc_fbhigh_dma; /* no pal just fbhigh */
584 /* init it to something, even though we won't be using it */
585 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_palette_dma;
586 } else {
587 fbi->dmadesc_palette_cpu->fdadr = fbi->dmadesc_fbhigh_dma;
588 fbi->dmadesc_fbhigh_cpu->fdadr = fbi->dmadesc_palette_dma;
589 fbi->fdadr0 = fbi->dmadesc_palette_dma; /* flips back and forth between pal and fbhigh */
590 }
591
592 #if 0
593 DPRINTK("fbi->dmadesc_fblow_cpu = 0x%p\n", fbi->dmadesc_fblow_cpu);
594 DPRINTK("fbi->dmadesc_fbhigh_cpu = 0x%p\n", fbi->dmadesc_fbhigh_cpu);
595 DPRINTK("fbi->dmadesc_palette_cpu = 0x%p\n", fbi->dmadesc_palette_cpu);
596 DPRINTK("fbi->dmadesc_fblow_dma = 0x%x\n", fbi->dmadesc_fblow_dma);
597 DPRINTK("fbi->dmadesc_fbhigh_dma = 0x%x\n", fbi->dmadesc_fbhigh_dma);
598 DPRINTK("fbi->dmadesc_palette_dma = 0x%x\n", fbi->dmadesc_palette_dma);
599
600 DPRINTK("fbi->dmadesc_fblow_cpu->fdadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fdadr);
601 DPRINTK("fbi->dmadesc_fbhigh_cpu->fdadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fdadr);
602 DPRINTK("fbi->dmadesc_palette_cpu->fdadr = 0x%x\n", fbi->dmadesc_palette_cpu->fdadr);
603
604 DPRINTK("fbi->dmadesc_fblow_cpu->fsadr = 0x%x\n", fbi->dmadesc_fblow_cpu->fsadr);
605 DPRINTK("fbi->dmadesc_fbhigh_cpu->fsadr = 0x%x\n", fbi->dmadesc_fbhigh_cpu->fsadr);
606 DPRINTK("fbi->dmadesc_palette_cpu->fsadr = 0x%x\n", fbi->dmadesc_palette_cpu->fsadr);
607
608 DPRINTK("fbi->dmadesc_fblow_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fblow_cpu->ldcmd);
609 DPRINTK("fbi->dmadesc_fbhigh_cpu->ldcmd = 0x%x\n", fbi->dmadesc_fbhigh_cpu->ldcmd);
610 DPRINTK("fbi->dmadesc_palette_cpu->ldcmd = 0x%x\n", fbi->dmadesc_palette_cpu->ldcmd);
611 #endif
612
613 fbi->reg_lccr0 = new_regs.lccr0;
614 fbi->reg_lccr1 = new_regs.lccr1;
615 fbi->reg_lccr2 = new_regs.lccr2;
616 fbi->reg_lccr3 = new_regs.lccr3;
617 local_irq_restore(flags);
618
619 /*
620 * Only update the registers if the controller is enabled
621 * and something has changed.
622 */
623 if ((LCCR0 != fbi->reg_lccr0) || (LCCR1 != fbi->reg_lccr1) ||
624 (LCCR2 != fbi->reg_lccr2) || (LCCR3 != fbi->reg_lccr3) ||
625 (FDADR0 != fbi->fdadr0) || (FDADR1 != fbi->fdadr1))
626 pxafb_schedule_work(fbi, C_REENABLE);
627
628 return 0;
629 }
630
631 /*
632 * NOTE! The following functions are purely helpers for set_ctrlr_state.
633 * Do not call them directly; set_ctrlr_state does the correct serialisation
634 * to ensure that things happen in the right way 100% of time time.
635 * -- rmk
636 */
637 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
638 {
639 DPRINTK("backlight o%s\n", on ? "n" : "ff");
640
641 if (pxafb_backlight_power)
642 pxafb_backlight_power(on);
643 }
644
645 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
646 {
647 DPRINTK("LCD power o%s\n", on ? "n" : "ff");
648
649 if (pxafb_lcd_power)
650 pxafb_lcd_power(on);
651 }
652
653 static void pxafb_setup_gpio(struct pxafb_info *fbi)
654 {
655 unsigned int lccr0 = fbi->lccr0;
656
657 /*
658 * setup is based on type of panel supported
659 */
660
661 /* 4 bit interface */
662 if ((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
663 (lccr0 & LCCR0_SDS) == LCCR0_Sngl &&
664 (lccr0 & LCCR0_DPD) == LCCR0_4PixMono)
665 {
666 // bits 58-61
667 GPDR1 |= (0xf << 26);
668 GAFR1_U = (GAFR1_U & ~(0xff << 20)) | (0xaa << 20);
669
670 // bits 74-77
671 GPDR2 |= (0xf << 10);
672 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
673 }
674
675 /* 8 bit interface */
676 else if (((lccr0 & LCCR0_CMS) == LCCR0_Mono &&
677 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_DPD) == LCCR0_8PixMono)) ||
678 ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
679 (lccr0 & LCCR0_PAS) == LCCR0_Pas && (lccr0 & LCCR0_SDS) == LCCR0_Sngl))
680 {
681 // bits 58-65
682 GPDR1 |= (0x3f << 26);
683 GPDR2 |= (0x3);
684
685 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
686 GAFR2_L = (GAFR2_L & ~0xf) | (0xa);
687
688 // bits 74-77
689 GPDR2 |= (0xf << 10);
690 GAFR2_L = (GAFR2_L & ~(0xff << 20)) | (0xaa << 20);
691 }
692
693 /* 16 bit interface */
694 else if ((lccr0 & LCCR0_CMS) == LCCR0_Color &&
695 ((lccr0 & LCCR0_SDS) == LCCR0_Dual || (lccr0 & LCCR0_PAS) == LCCR0_Act))
696 {
697 // bits 58-77
698 GPDR1 |= (0x3f << 26);
699 GPDR2 |= 0x00003fff;
700
701 GAFR1_U = (GAFR1_U & ~(0xfff << 20)) | (0xaaa << 20);
702 GAFR2_L = (GAFR2_L & 0xf0000000) | 0x0aaaaaaa;
703 }
704
705 else {
706 printk(KERN_ERR "pxafb_setup_gpio: unable to determine bits per pixel\n");
707 }
708 }
709
710 static void pxafb_enable_controller(struct pxafb_info *fbi)
711 {
712 DPRINTK("Enabling LCD controller\n");
713 DPRINTK("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr0);
714 DPRINTK("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr1);
715 DPRINTK("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
716 DPRINTK("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
717 DPRINTK("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
718 DPRINTK("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
719
720 /* Sequence from 11.7.10 */
721 LCCR3 = fbi->reg_lccr3;
722 LCCR2 = fbi->reg_lccr2;
723 LCCR1 = fbi->reg_lccr1;
724 LCCR0 = fbi->reg_lccr0 & ~LCCR0_ENB;
725
726 FDADR0 = fbi->fdadr0;
727 FDADR1 = fbi->fdadr1;
728 LCCR0 |= LCCR0_ENB;
729
730 DPRINTK("FDADR0 0x%08x\n", (unsigned int) FDADR0);
731 DPRINTK("FDADR1 0x%08x\n", (unsigned int) FDADR1);
732 DPRINTK("LCCR0 0x%08x\n", (unsigned int) LCCR0);
733 DPRINTK("LCCR1 0x%08x\n", (unsigned int) LCCR1);
734 DPRINTK("LCCR2 0x%08x\n", (unsigned int) LCCR2);
735 DPRINTK("LCCR3 0x%08x\n", (unsigned int) LCCR3);
736 }
737
738 static void pxafb_disable_controller(struct pxafb_info *fbi)
739 {
740 DECLARE_WAITQUEUE(wait, current);
741
742 DPRINTK("Disabling LCD controller\n");
743
744 add_wait_queue(&fbi->ctrlr_wait, &wait);
745 set_current_state(TASK_UNINTERRUPTIBLE);
746
747 LCSR = 0xffffffff; /* Clear LCD Status Register */
748 LCCR0 &= ~LCCR0_LDM; /* Enable LCD Disable Done Interrupt */
749 LCCR0 |= LCCR0_DIS; /* Disable LCD Controller */
750
751 schedule_timeout(20 * HZ / 1000);
752 remove_wait_queue(&fbi->ctrlr_wait, &wait);
753 }
754
755 /*
756 * pxafb_handle_irq: Handle 'LCD DONE' interrupts.
757 */
758 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id, struct pt_regs *regs)
759 {
760 struct pxafb_info *fbi = dev_id;
761 unsigned int lcsr = LCSR;
762
763 if (lcsr & LCSR_LDD) {
764 LCCR0 |= LCCR0_LDM;
765 wake_up(&fbi->ctrlr_wait);
766 }
767
768 LCSR = lcsr;
769 return IRQ_HANDLED;
770 }
771
772 /*
773 * This function must be called from task context only, since it will
774 * sleep when disabling the LCD controller, or if we get two contending
775 * processes trying to alter state.
776 */
777 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
778 {
779 u_int old_state;
780
781 down(&fbi->ctrlr_sem);
782
783 old_state = fbi->state;
784
785 /*
786 * Hack around fbcon initialisation.
787 */
788 if (old_state == C_STARTUP && state == C_REENABLE)
789 state = C_ENABLE;
790
791 switch (state) {
792 case C_DISABLE_CLKCHANGE:
793 /*
794 * Disable controller for clock change. If the
795 * controller is already disabled, then do nothing.
796 */
797 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
798 fbi->state = state;
799 //TODO __pxafb_lcd_power(fbi, 0);
800 pxafb_disable_controller(fbi);
801 }
802 break;
803
804 case C_DISABLE_PM:
805 case C_DISABLE:
806 /*
807 * Disable controller
808 */
809 if (old_state != C_DISABLE) {
810 fbi->state = state;
811 __pxafb_backlight_power(fbi, 0);
812 __pxafb_lcd_power(fbi, 0);
813 if (old_state != C_DISABLE_CLKCHANGE)
814 pxafb_disable_controller(fbi);
815 }
816 break;
817
818 case C_ENABLE_CLKCHANGE:
819 /*
820 * Enable the controller after clock change. Only
821 * do this if we were disabled for the clock change.
822 */
823 if (old_state == C_DISABLE_CLKCHANGE) {
824 fbi->state = C_ENABLE;
825 pxafb_enable_controller(fbi);
826 //TODO __pxafb_lcd_power(fbi, 1);
827 }
828 break;
829
830 case C_REENABLE:
831 /*
832 * Re-enable the controller only if it was already
833 * enabled. This is so we reprogram the control
834 * registers.
835 */
836 if (old_state == C_ENABLE) {
837 pxafb_disable_controller(fbi);
838 pxafb_setup_gpio(fbi);
839 pxafb_enable_controller(fbi);
840 }
841 break;
842
843 case C_ENABLE_PM:
844 /*
845 * Re-enable the controller after PM. This is not
846 * perfect - think about the case where we were doing
847 * a clock change, and we suspended half-way through.
848 */
849 if (old_state != C_DISABLE_PM)
850 break;
851 /* fall through */
852
853 case C_ENABLE:
854 /*
855 * Power up the LCD screen, enable controller, and
856 * turn on the backlight.
857 */
858 if (old_state != C_ENABLE) {
859 fbi->state = C_ENABLE;
860 pxafb_setup_gpio(fbi);
861 pxafb_enable_controller(fbi);
862 __pxafb_lcd_power(fbi, 1);
863 __pxafb_backlight_power(fbi, 1);
864 }
865 break;
866 }
867 up(&fbi->ctrlr_sem);
868 }
869
870 /*
871 * Our LCD controller task (which is called when we blank or unblank)
872 * via keventd.
873 */
874 static void pxafb_task(void *dummy)
875 {
876 struct pxafb_info *fbi = dummy;
877 u_int state = xchg(&fbi->task_state, -1);
878
879 set_ctrlr_state(fbi, state);
880 }
881
882 #ifdef CONFIG_CPU_FREQ
883 /*
884 * CPU clock speed change handler. We need to adjust the LCD timing
885 * parameters when the CPU clock is adjusted by the power management
886 * subsystem.
887 *
888 * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
889 */
890 static int
891 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
892 {
893 struct pxafb_info *fbi = TO_INF(nb, freq_transition);
894 //TODO struct cpufreq_freqs *f = data;
895 u_int pcd;
896
897 switch (val) {
898 case CPUFREQ_PRECHANGE:
899 set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
900 break;
901
902 case CPUFREQ_POSTCHANGE:
903 pcd = get_pcd(fbi->fb.var.pixclock);
904 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) | LCCR3_PixClkDiv(pcd);
905 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
906 break;
907 }
908 return 0;
909 }
910
911 static int
912 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
913 {
914 struct pxafb_info *fbi = TO_INF(nb, freq_policy);
915 struct fb_var_screeninfo *var = &fbi->fb.var;
916 struct cpufreq_policy *policy = data;
917
918 switch (val) {
919 case CPUFREQ_ADJUST:
920 case CPUFREQ_INCOMPATIBLE:
921 printk(KERN_DEBUG "min dma period: %d ps, "
922 "new clock %d kHz\n", pxafb_display_dma_period(var),
923 policy->max);
924 // TODO: fill in min/max values
925 break;
926 #if 0
927 case CPUFREQ_NOTIFY:
928 printk(KERN_ERR "%s: got CPUFREQ_NOTIFY\n", __FUNCTION__);
929 do {} while(0);
930 /* todo: panic if min/max values aren't fulfilled
931 * [can't really happen unless there's a bug in the
932 * CPU policy verification process *
933 */
934 break;
935 #endif
936 }
937 return 0;
938 }
939 #endif
940
941 #ifdef CONFIG_PM
942 /*
943 * Power management hooks. Note that we won't be called from IRQ context,
944 * unlike the blank functions above, so we may sleep.
945 */
946 static int pxafb_suspend(struct device *dev, u32 state, u32 level)
947 {
948 struct pxafb_info *fbi = dev_get_drvdata(dev);
949
950 if (level == SUSPEND_DISABLE || level == SUSPEND_POWER_DOWN)
951 set_ctrlr_state(fbi, C_DISABLE_PM);
952 return 0;
953 }
954
955 static int pxafb_resume(struct device *dev, u32 level)
956 {
957 struct pxafb_info *fbi = dev_get_drvdata(dev);
958
959 if (level == RESUME_ENABLE)
960 set_ctrlr_state(fbi, C_ENABLE_PM);
961 return 0;
962 }
963 #else
964 #define pxafb_suspend NULL
965 #define pxafb_resume NULL
966 #endif
967
968 /*
969 * pxafb_map_video_memory():
970 * Allocates the DRAM memory for the frame buffer. This buffer is
971 * remapped into a non-cached, non-buffered, memory region to
972 * allow palette and pixel writes to occur without flushing the
973 * cache. Once this area is remapped, all virtual memory
974 * access to the video memory should occur at the new region.
975 */
976 static int __init pxafb_map_video_memory(struct pxafb_info *fbi)
977 {
978 u_long palette_mem_size;
979
980 /*
981 * We reserve one page for the palette, plus the size
982 * of the framebuffer.
983 */
984 fbi->map_size = PAGE_ALIGN(fbi->fb.fix.smem_len + PAGE_SIZE);
985 fbi->map_cpu = dma_alloc_writecombine(fbi->dev, fbi->map_size,
986 &fbi->map_dma, GFP_KERNEL);
987
988 if (fbi->map_cpu) {
989 /* prevent initial garbage on screen */
990 memset(fbi->map_cpu, 0, fbi->map_size);
991 fbi->fb.screen_base = fbi->map_cpu + PAGE_SIZE;
992 fbi->screen_dma = fbi->map_dma + PAGE_SIZE;
993 /*
994 * FIXME: this is actually the wrong thing to place in
995 * smem_start. But fbdev suffers from the problem that
996 * it needs an API which doesn't exist (in this case,
997 * dma_writecombine_mmap)
998 */
999 fbi->fb.fix.smem_start = fbi->screen_dma;
1000
1001 fbi->palette_size = fbi->fb.var.bits_per_pixel == 8 ? 256 : 16;
1002
1003 palette_mem_size = fbi->palette_size * sizeof(u16);
1004 DPRINTK("palette_mem_size = 0x%08lx\n", (u_long) palette_mem_size);
1005
1006 fbi->palette_cpu = (u16 *)(fbi->map_cpu + PAGE_SIZE - palette_mem_size);
1007 fbi->palette_dma = fbi->map_dma + PAGE_SIZE - palette_mem_size;
1008 }
1009
1010 return fbi->map_cpu ? 0 : -ENOMEM;
1011 }
1012
1013 static struct pxafb_info * __init pxafb_init_fbinfo(struct device *dev)
1014 {
1015 struct pxafb_info *fbi;
1016 void *addr;
1017 struct pxafb_mach_info *inf = dev->platform_data;
1018
1019 /* Alloc the pxafb_info and pseudo_palette in one step */
1020 fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1021 if (!fbi)
1022 return NULL;
1023
1024 memset(fbi, 0, sizeof(struct pxafb_info));
1025 fbi->dev = dev;
1026
1027 strcpy(fbi->fb.fix.id, PXA_NAME);
1028
1029 fbi->fb.fix.type = FB_TYPE_PACKED_PIXELS;
1030 fbi->fb.fix.type_aux = 0;
1031 fbi->fb.fix.xpanstep = 0;
1032 fbi->fb.fix.ypanstep = 0;
1033 fbi->fb.fix.ywrapstep = 0;
1034 fbi->fb.fix.accel = FB_ACCEL_NONE;
1035
1036 fbi->fb.var.nonstd = 0;
1037 fbi->fb.var.activate = FB_ACTIVATE_NOW;
1038 fbi->fb.var.height = -1;
1039 fbi->fb.var.width = -1;
1040 fbi->fb.var.accel_flags = 0;
1041 fbi->fb.var.vmode = FB_VMODE_NONINTERLACED;
1042
1043 fbi->fb.fbops = &pxafb_ops;
1044 fbi->fb.flags = FBINFO_DEFAULT;
1045 fbi->fb.node = -1;
1046 fbi->fb.currcon = -1;
1047
1048 addr = fbi;
1049 addr = addr + sizeof(struct pxafb_info);
1050 fbi->fb.pseudo_palette = addr;
1051
1052 fbi->max_xres = inf->xres;
1053 fbi->fb.var.xres = inf->xres;
1054 fbi->fb.var.xres_virtual = inf->xres;
1055 fbi->max_yres = inf->yres;
1056 fbi->fb.var.yres = inf->yres;
1057 fbi->fb.var.yres_virtual = inf->yres;
1058 fbi->max_bpp = inf->bpp;
1059 fbi->fb.var.bits_per_pixel = inf->bpp;
1060 fbi->fb.var.pixclock = inf->pixclock;
1061 fbi->fb.var.hsync_len = inf->hsync_len;
1062 fbi->fb.var.left_margin = inf->left_margin;
1063 fbi->fb.var.right_margin = inf->right_margin;
1064 fbi->fb.var.vsync_len = inf->vsync_len;
1065 fbi->fb.var.upper_margin = inf->upper_margin;
1066 fbi->fb.var.lower_margin = inf->lower_margin;
1067 fbi->fb.var.sync = inf->sync;
1068 fbi->fb.var.grayscale = inf->cmap_greyscale;
1069 fbi->cmap_inverse = inf->cmap_inverse;
1070 fbi->cmap_static = inf->cmap_static;
1071 fbi->lccr0 = inf->lccr0;
1072 fbi->lccr3 = inf->lccr3;
1073 fbi->state = C_STARTUP;
1074 fbi->task_state = (u_char)-1;
1075 fbi->fb.fix.smem_len = fbi->max_xres * fbi->max_yres *
1076 fbi->max_bpp / 8;
1077
1078 init_waitqueue_head(&fbi->ctrlr_wait);
1079 INIT_WORK(&fbi->task, pxafb_task, fbi);
1080 init_MUTEX(&fbi->ctrlr_sem);
1081
1082 return fbi;
1083 }
1084
1085 #ifdef CONFIG_FB_PXA_PARAMETERS
1086 static int __init pxafb_parse_options(struct device *dev, char *options)
1087 {
1088 struct pxafb_mach_info *inf = dev->platform_data;
1089 char *this_opt;
1090
1091 if (!options || !*options)
1092 return 0;
1093
1094 dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
1095
1096 /* could be made table driven or similar?... */
1097 while ((this_opt = strsep(&options, ",")) != NULL) {
1098 if (!strncmp(this_opt, "mode:", 5)) {
1099 const char *name = this_opt+5;
1100 unsigned int namelen = strlen(name);
1101 int res_specified = 0, bpp_specified = 0;
1102 unsigned int xres = 0, yres = 0, bpp = 0;
1103 int yres_specified = 0;
1104 int i;
1105 for (i = namelen-1; i >= 0; i--) {
1106 switch (name[i]) {
1107 case '-':
1108 namelen = i;
1109 if (!bpp_specified && !yres_specified) {
1110 bpp = simple_strtoul(&name[i+1], NULL, 0);
1111 bpp_specified = 1;
1112 } else
1113 goto done;
1114 break;
1115 case 'x':
1116 if (!yres_specified) {
1117 yres = simple_strtoul(&name[i+1], NULL, 0);
1118 yres_specified = 1;
1119 } else
1120 goto done;
1121 break;
1122 case '0'...'9':
1123 break;
1124 default:
1125 goto done;
1126 }
1127 }
1128 if (i < 0 && yres_specified) {
1129 xres = simple_strtoul(name, NULL, 0);
1130 res_specified = 1;
1131 }
1132 done:
1133 if (res_specified) {
1134 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1135 inf->xres = xres; inf->yres = yres;
1136 }
1137 if (bpp_specified)
1138 switch (bpp) {
1139 case 1:
1140 case 2:
1141 case 4:
1142 case 8:
1143 case 16:
1144 inf->bpp = bpp;
1145 dev_info(dev, "overriding bit depth: %d\n", bpp);
1146 break;
1147 default:
1148 dev_err(dev, "Depth %d is not valid\n", bpp);
1149 }
1150 } else if (!strncmp(this_opt, "pixclock:", 9)) {
1151 inf->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1152 dev_info(dev, "override pixclock: %ld\n", inf->pixclock);
1153 } else if (!strncmp(this_opt, "left:", 5)) {
1154 inf->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1155 dev_info(dev, "override left: %u\n", inf->left_margin);
1156 } else if (!strncmp(this_opt, "right:", 6)) {
1157 inf->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1158 dev_info(dev, "override right: %u\n", inf->right_margin);
1159 } else if (!strncmp(this_opt, "upper:", 6)) {
1160 inf->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1161 dev_info(dev, "override upper: %u\n", inf->upper_margin);
1162 } else if (!strncmp(this_opt, "lower:", 6)) {
1163 inf->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1164 dev_info(dev, "override lower: %u\n", inf->lower_margin);
1165 } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1166 inf->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1167 dev_info(dev, "override hsynclen: %u\n", inf->hsync_len);
1168 } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1169 inf->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1170 dev_info(dev, "override vsynclen: %u\n", inf->vsync_len);
1171 } else if (!strncmp(this_opt, "hsync:", 6)) {
1172 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1173 dev_info(dev, "override hsync: Active Low\n");
1174 inf->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1175 } else {
1176 dev_info(dev, "override hsync: Active High\n");
1177 inf->sync |= FB_SYNC_HOR_HIGH_ACT;
1178 }
1179 } else if (!strncmp(this_opt, "vsync:", 6)) {
1180 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1181 dev_info(dev, "override vsync: Active Low\n");
1182 inf->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1183 } else {
1184 dev_info(dev, "override vsync: Active High\n");
1185 inf->sync |= FB_SYNC_VERT_HIGH_ACT;
1186 }
1187 } else if (!strncmp(this_opt, "dpc:", 4)) {
1188 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1189 dev_info(dev, "override double pixel clock: false\n");
1190 inf->lccr3 &= ~LCCR3_DPC;
1191 } else {
1192 dev_info(dev, "override double pixel clock: true\n");
1193 inf->lccr3 |= LCCR3_DPC;
1194 }
1195 } else if (!strncmp(this_opt, "outputen:", 9)) {
1196 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1197 dev_info(dev, "override output enable: active low\n");
1198 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1199 } else {
1200 dev_info(dev, "override output enable: active high\n");
1201 inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1202 }
1203 } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1204 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1205 dev_info(dev, "override pixel clock polarity: falling edge\n");
1206 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1207 } else {
1208 dev_info(dev, "override pixel clock polarity: rising edge\n");
1209 inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1210 }
1211 } else if (!strncmp(this_opt, "color", 5)) {
1212 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1213 } else if (!strncmp(this_opt, "mono", 4)) {
1214 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1215 } else if (!strncmp(this_opt, "active", 6)) {
1216 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1217 } else if (!strncmp(this_opt, "passive", 7)) {
1218 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1219 } else if (!strncmp(this_opt, "single", 6)) {
1220 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1221 } else if (!strncmp(this_opt, "dual", 4)) {
1222 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
1223 } else if (!strncmp(this_opt, "4pix", 4)) {
1224 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
1225 } else if (!strncmp(this_opt, "8pix", 4)) {
1226 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
1227 } else {
1228 dev_err(dev, "unknown option: %s\n", this_opt);
1229 return -EINVAL;
1230 }
1231 }
1232 return 0;
1233
1234 }
1235 #endif
1236
1237 int __init pxafb_probe(struct device *dev)
1238 {
1239 struct pxafb_info *fbi;
1240 struct pxafb_mach_info *inf;
1241 int ret;
1242
1243 dev_dbg(dev, "pxafb_probe\n");
1244
1245 inf = dev->platform_data;
1246 ret = -ENOMEM;
1247 fbi = NULL;
1248 if (!inf)
1249 goto failed;
1250
1251 #ifdef CONFIG_FB_PXA_PARAMETERS
1252 ret = pxafb_parse_options(dev, g_options);
1253 if (ret < 0)
1254 goto failed;
1255 #endif
1256
1257 #ifdef DEBUG_VAR
1258 /* Check for various illegal bit-combinations. Currently only
1259 * a warning is given. */
1260
1261 if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
1262 dev_warn(dev, "machine LCCR0 setting contains illegal bits: %08x\n",
1263 inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
1264 if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
1265 dev_warn(dev, "machine LCCR3 setting contains illegal bits: %08x\n",
1266 inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
1267 if (inf->lccr0 & LCCR0_DPD &&
1268 ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
1269 (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
1270 (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
1271 dev_warn(dev, "Double Pixel Data (DPD) mode is only valid in passive mono"
1272 " single panel mode\n");
1273 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
1274 (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1275 dev_warn(dev, "Dual panel only valid in passive mode\n");
1276 if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
1277 (inf->upper_margin || inf->lower_margin))
1278 dev_warn(dev, "Upper and lower margins must be 0 in passive mode\n");
1279 #endif
1280
1281 dev_dbg(dev, "got a %dx%dx%d LCD\n",inf->xres, inf->yres, inf->bpp);
1282 if (inf->xres == 0 || inf->yres == 0 || inf->bpp == 0) {
1283 dev_err(dev, "Invalid resolution or bit depth\n");
1284 ret = -EINVAL;
1285 goto failed;
1286 }
1287 pxafb_backlight_power = inf->pxafb_backlight_power;
1288 pxafb_lcd_power = inf->pxafb_lcd_power;
1289 fbi = pxafb_init_fbinfo(dev);
1290 if (!fbi) {
1291 dev_err(dev, "Failed to initialize framebuffer device\n");
1292 ret = -ENOMEM; // only reason for pxafb_init_fbinfo to fail is kmalloc
1293 goto failed;
1294 }
1295
1296 /* Initialize video memory */
1297 ret = pxafb_map_video_memory(fbi);
1298 if (ret) {
1299 dev_err(dev, "Failed to allocate video RAM: %d\n", ret);
1300 ret = -ENOMEM;
1301 goto failed;
1302 }
1303 /* enable LCD controller clock */
1304 pxa_set_cken(CKEN16_LCD, 1);
1305
1306 ret = request_irq(IRQ_LCD, pxafb_handle_irq, SA_INTERRUPT, "LCD", fbi);
1307 if (ret) {
1308 dev_err(dev, "request_irq failed: %d\n", ret);
1309 ret = -EBUSY;
1310 goto failed;
1311 }
1312
1313 /*
1314 * This makes sure that our colour bitfield
1315 * descriptors are correctly initialised.
1316 */
1317 pxafb_check_var(&fbi->fb.var, &fbi->fb);
1318 pxafb_set_par(&fbi->fb);
1319
1320 dev_set_drvdata(dev, fbi);
1321
1322 ret = register_framebuffer(&fbi->fb);
1323 if (ret < 0) {
1324 dev_err(dev, "Failed to register framebuffer device: %d\n", ret);
1325 goto failed;
1326 }
1327
1328 #ifdef CONFIG_PM
1329 // TODO
1330 #endif
1331
1332 #ifdef CONFIG_CPU_FREQ
1333 fbi->freq_transition.notifier_call = pxafb_freq_transition;
1334 fbi->freq_policy.notifier_call = pxafb_freq_policy;
1335 cpufreq_register_notifier(&fbi->freq_transition, CPUFREQ_TRANSITION_NOTIFIER);
1336 cpufreq_register_notifier(&fbi->freq_policy, CPUFREQ_POLICY_NOTIFIER);
1337 #endif
1338
1339 /*
1340 * Ok, now enable the LCD controller
1341 */
1342 set_ctrlr_state(fbi, C_ENABLE);
1343
1344 return 0;
1345
1346 failed:
1347 dev_set_drvdata(dev, NULL);
1348 if (fbi)
1349 kfree(fbi);
1350 return ret;
1351 }
1352
1353 static struct device_driver pxafb_driver = {
1354 .name = "pxa2xx-fb",
1355 .bus = &platform_bus_type,
1356 .probe = pxafb_probe,
1357 #ifdef CONFIG_PM
1358 .suspend = pxafb_suspend,
1359 .resume = pxafb_resume,
1360 #endif
1361 };
1362
1363 #ifndef MODULE
1364 int __devinit pxafb_setup(char *options)
1365 {
1366 # ifdef CONFIG_FB_PXA_PARAMETERS
1367 strlcpy(g_options, options, sizeof(g_options));
1368 # endif
1369 return 0;
1370 }
1371 #else
1372 # ifdef CONFIG_FB_PXA_PARAMETERS
1373 module_param_string(options, g_options, sizeof(g_options), 0);
1374 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
1375 # endif
1376 #endif
1377
1378 int __devinit pxafb_init(void)
1379 {
1380 #ifndef MODULE
1381 char *option = NULL;
1382
1383 if (fb_get_options("pxafb", &option))
1384 return -ENODEV;
1385 pxafb_setup(option);
1386 #endif
1387 return driver_register(&pxafb_driver);
1388 }
1389
1390 module_init(pxafb_init);
1391
1392 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
1393 MODULE_LICENSE("GPL");
MOXA 2.6.9 from sdlinux-moxaart.tgz