drivers/serial/sh-sci.h

   1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
   2  *
   3  *  linux/drivers/serial/sh-sci.h
   4  *
   5  *  SuperH on-chip serial module support.  (SCI with no FIFO / with FIFO)
   6  *  Copyright (C) 1999, 2000  Niibe Yutaka
   7  *  Copyright (C) 2000  Greg Banks
   8  *  Copyright (C) 2002, 2003  Paul Mundt
   9  *  Modified to support multiple serial ports. Stuart Menefy (May 2000).
  10  *  Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
  11  *  Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
  12  */
  13 #include <linux/config.h>
  14 #include <linux/serial_core.h>
  15
  16 #if defined(__H8300H__) || defined(__H8300S__)
  17 #include <asm/gpio.h>
  18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
  19 #include <asm/regs306x.h>
  20 #endif
  21 #if defined(CONFIG_H8S2678)
  22 #include <asm/regs267x.h>
  23 #endif
  24 #endif
  25
  26 /* Offsets into the sci_port->irqs array */
  27 #define SCIx_ERI_IRQ 0
  28 #define SCIx_RXI_IRQ 1
  29 #define SCIx_TXI_IRQ 2
  30
  31 /*                     ERI, RXI, TXI, BRI */
  32 #define SCI_IRQS      { 23,  24,  25,   0 }
  33 #define SH3_SCIF_IRQS { 56,  57,  59,  58 }
  34 #define SH3_IRDA_IRQS { 52,  53,  55,  54 }
  35 #define SH4_SCIF_IRQS { 40,  41,  43,  42 }
  36 #define STB1_SCIF1_IRQS {23, 24,  26,  25 }
  37 #define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
  38 #define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
  39 #define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
  40 #define SH7300_SCIF0_IRQS {80,  80,  80,  80 }
  41 #define H8300H_SCI_IRQS0 {52, 53, 54,   0 }
  42 #define H8300H_SCI_IRQS1 {56, 57, 58,   0 }
  43 #define H8300H_SCI_IRQS2 {60, 61, 62,   0 }
  44 #define H8S_SCI_IRQS0 {88, 89, 90,   0 }
  45 #define H8S_SCI_IRQS1 {92, 93, 94,   0 }
  46 #define H8S_SCI_IRQS2 {96, 97, 98,   0 }
  47 #define SH5_SCIF_IRQS {39, 40, 42,   0 }
  48
  49 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
  50 # define SCI_NPORTS 1
  51 # define SCSPTR 0xffffff7c /* 8 bit */
  52 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  53 # define SCI_ONLY
  54 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
  55 # define SCI_NPORTS 3
  56 # define SCPCR  0xA4000116 /* 16 bit SCI and SCIF */
  57 # define SCPDR  0xA4000136 /* 8  bit SCI and SCIF */
  58 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
  59 # define SCI_AND_SCIF
  60 #elif defined(CONFIG_SH_RTS7751R2D)
  61 # define SCI_NPORTS 1
  62 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  63 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  64 # define SCIF_ORER 0x0001   /* overrun error bit */
  65 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  66 # define SCIF_ONLY
  67 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
  68 # define SCI_NPORTS 2
  69 # define SCSPTR1 0xffe0001c /* 8  bit SCI */
  70 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
  71 # define SCIF_ORER 0x0001   /* overrun error bit */
  72 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
  73         0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
  74         0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
  75 # define SCI_AND_SCIF
  76 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
  77 # define SCI_NPORTS 3
  78 # define SCSPTR0 0xfe600000 /* 16 bit SCIF */
  79 # define SCSPTR1 0xfe610000 /* 16 bit SCIF */
  80 # define SCSPTR2 0xfe620000 /* 16 bit SCIF */
  81 # define SCIF_ORER 0x0001  /* overrun error bit */
  82 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  83 # define SCIF_ONLY
  84 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
  85 # define SCI_NPORTS 1
  86 # define SCPCR  0xA4050116        /* 16 bit SCIF */
  87 # define SCPDR  0xA4050136        /* 16 bit SCIF */
  88 # define SCSCR_INIT(port)  0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
  89 # define SCIF_ONLY
  90 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
  91 # define SCI_NPORTS 2
  92 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
  93 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
  94 # define SCIF_ORER 0x0001   /* overrun error bit */
  95 # define SCSCR_INIT(port)          0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
  96 # define SCIF_ONLY
  97 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
  98 # include <asm/hardware.h>
  99 # define SCIF_BASE_ADDR    0x01030000
 100 # define SCIF_ADDR_SH5     PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
 101 # define SCIF_PTR2_OFFS    0x0000020
 102 # define SCIF_LSR2_OFFS    0x0000024
 103 # define SCI_NPORTS 1
 104 # define SCI_INIT { \
 105   { {}, PORT_SCIF, 0, \
 106      SH5_SCIF_IRQS, sci_init_pins_scif }  \
 107 }
 108 # define SCSPTR2           ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
 109 # define SCLSR2            ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
 110 # define SCSCR_INIT(port)  0x38                           /* TIE=0,RIE=0,
 111                                                              TE=1,RE=1,REIE=1 */
 112 # define SCIF_ONLY
 113 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
 114 # define SCI_NPORTS 3
 115 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 116 # define SCI_ONLY
 117 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 118 #elif defined(CONFIG_H8S2678)
 119 # define SCI_NPORTS 3
 120 # define SCSCR_INIT(port)          0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
 121 # define SCI_ONLY
 122 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
 123 #else
 124 # error CPU subtype not defined
 125 #endif
 126
 127 /* SCSCR */
 128 #define SCI_CTRL_FLAGS_TIE  0x80 /* all */
 129 #define SCI_CTRL_FLAGS_RIE  0x40 /* all */
 130 #define SCI_CTRL_FLAGS_TE   0x20 /* all */
 131 #define SCI_CTRL_FLAGS_RE   0x10 /* all */
 132 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
 133 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 134 #else
 135 #define SCI_CTRL_FLAGS_REIE 0
 136 #endif
 137 /*      SCI_CTRL_FLAGS_MPIE 0x08  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 138 /*      SCI_CTRL_FLAGS_TEIE 0x04  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 139 /*      SCI_CTRL_FLAGS_CKE1 0x02  * all */
 140 /*      SCI_CTRL_FLAGS_CKE0 0x01  * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
 141
 142 /* SCxSR SCI */
 143 #define SCI_TDRE  0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 144 #define SCI_RDRF  0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 145 #define SCI_ORER  0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 146 #define SCI_FER   0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 147 #define SCI_PER   0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 148 #define SCI_TEND  0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 149 /*      SCI_MPB   0x02  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 150 /*      SCI_MPBT  0x01  * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
 151
 152 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
 153
 154 /* SCxSR SCIF */
 155 #define SCIF_ER    0x0080 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 156 #define SCIF_TEND  0x0040 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 157 #define SCIF_TDFE  0x0020 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 158 #define SCIF_BRK   0x0010 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 159 #define SCIF_FER   0x0008 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 160 #define SCIF_PER   0x0004 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 161 #define SCIF_RDF   0x0002 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 162 #define SCIF_DR    0x0001 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
 163
 164 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 165 #define SCIF_ORER    0x0200
 166 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
 167 #define SCIF_RFDC_MASK 0x007f
 168 #define SCIF_TXROOM_MAX 64
 169 #else
 170 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
 171 #define SCIF_RFDC_MASK 0x001f
 172 #define SCIF_TXROOM_MAX 16
 173 #endif
 174
 175 #if defined(SCI_ONLY)
 176 # define SCxSR_TEND(port)               SCI_TEND
 177 # define SCxSR_ERRORS(port)             SCI_ERRORS
 178 # define SCxSR_RDxF(port)               SCI_RDRF
 179 # define SCxSR_TDxE(port)               SCI_TDRE
 180 # define SCxSR_ORER(port)               SCI_ORER
 181 # define SCxSR_FER(port)                SCI_FER
 182 # define SCxSR_PER(port)                SCI_PER
 183 # define SCxSR_BRK(port)                0x00
 184 # define SCxSR_RDxF_CLEAR(port)         0xbc
 185 # define SCxSR_ERROR_CLEAR(port)        0xc4
 186 # define SCxSR_TDxE_CLEAR(port)         0x78
 187 # define SCxSR_BREAK_CLEAR(port)        0xc4
 188 #elif defined(SCIF_ONLY)
 189 # define SCxSR_TEND(port)               SCIF_TEND
 190 # define SCxSR_ERRORS(port)             SCIF_ERRORS
 191 # define SCxSR_RDxF(port)               SCIF_RDF
 192 # define SCxSR_TDxE(port)               SCIF_TDFE
 193 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 194 # define SCxSR_ORER(port)               SCIF_ORER
 195 #else
 196 # define SCxSR_ORER(port)               0x0000
 197 #endif
 198 # define SCxSR_FER(port)                SCIF_FER
 199 # define SCxSR_PER(port)                SCIF_PER
 200 # define SCxSR_BRK(port)                SCIF_BRK
 201 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 202 # define SCxSR_RDxF_CLEAR(port)         (sci_in(port,SCxSR)&0xfffc)
 203 # define SCxSR_ERROR_CLEAR(port)        (sci_in(port,SCxSR)&0xfd73)
 204 # define SCxSR_TDxE_CLEAR(port)         (sci_in(port,SCxSR)&0xffdf)
 205 # define SCxSR_BREAK_CLEAR(port)        (sci_in(port,SCxSR)&0xffe3)
 206 #else
 207 # define SCxSR_RDxF_CLEAR(port)         0x00fc
 208 # define SCxSR_ERROR_CLEAR(port)        0x0073
 209 # define SCxSR_TDxE_CLEAR(port)         0x00df
 210 # define SCxSR_BREAK_CLEAR(port)        0x00e3
 211 #endif
 212 #else
 213 # define SCxSR_TEND(port)        (((port)->type == PORT_SCI) ? SCI_TEND   : SCIF_TEND)
 214 # define SCxSR_ERRORS(port)      (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
 215 # define SCxSR_RDxF(port)        (((port)->type == PORT_SCI) ? SCI_RDRF   : SCIF_RDF)
 216 # define SCxSR_TDxE(port)        (((port)->type == PORT_SCI) ? SCI_TDRE   : SCIF_TDFE)
 217 # define SCxSR_ORER(port)        (((port)->type == PORT_SCI) ? SCI_ORER   : 0x0000)
 218 # define SCxSR_FER(port)         (((port)->type == PORT_SCI) ? SCI_FER    : SCIF_FER)
 219 # define SCxSR_PER(port)         (((port)->type == PORT_SCI) ? SCI_PER    : SCIF_PER)
 220 # define SCxSR_BRK(port)         (((port)->type == PORT_SCI) ? 0x00       : SCIF_BRK)
 221 # define SCxSR_RDxF_CLEAR(port)  (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
 222 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
 223 # define SCxSR_TDxE_CLEAR(port)  (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
 224 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
 225 #endif
 226
 227 /* SCFCR */
 228 #define SCFCR_RFRST 0x0002
 229 #define SCFCR_TFRST 0x0004
 230 #define SCFCR_TCRST 0x4000
 231 #define SCFCR_MCE   0x0008
 232
 233 #define SCI_MAJOR               204
 234 #define SCI_MINOR_START         8
 235
 236 /* Generic serial flags */
 237 #define SCI_RX_THROTTLE         0x0000001
 238
 239 #define SCI_MAGIC 0xbabeface
 240
 241 /*
 242  * Events are used to schedule things to happen at timer-interrupt
 243  * time, instead of at rs interrupt time.
 244  */
 245 #define SCI_EVENT_WRITE_WAKEUP  0
 246
 247 struct sci_port {
 248         struct uart_port port;
 249         int type;
 250         unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
 251         void (*init_pins)(struct uart_port *port, unsigned int cflag);
 252         int break_flag;
 253         struct timer_list break_timer;
 254 };
 255
 256 #define SCI_IN(size, offset)                                    \
 257   unsigned int addr = port->mapbase + (offset);                 \
 258   if ((size) == 8) {                                            \
 259     return ctrl_inb(addr);                                      \
 260   } else {                                                      \
 261     return ctrl_inw(addr);                                      \
 262   }
 263 #define SCI_OUT(size, offset, value)                            \
 264   unsigned int addr = port->mapbase + (offset);                 \
 265   if ((size) == 8) {                                            \
 266     ctrl_outb(value, addr);                                     \
 267   } else {                                                      \
 268     ctrl_outw(value, addr);                                     \
 269   }
 270
 271 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
 272   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 273   {                                                                     \
 274     if (port->type == PORT_SCI) {                                       \
 275       SCI_IN(sci_size, sci_offset)                                      \
 276     } else {                                                            \
 277       SCI_IN(scif_size, scif_offset);                                   \
 278     }                                                                   \
 279   }                                                                     \
 280   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 281   {                                                                     \
 282     if (port->type == PORT_SCI) {                                       \
 283       SCI_OUT(sci_size, sci_offset, value)                              \
 284     } else {                                                            \
 285       SCI_OUT(scif_size, scif_offset, value);                           \
 286     }                                                                   \
 287   }
 288
 289 #define CPU_SCIF_FNS(name, scif_offset, scif_size)                              \
 290   static inline unsigned int sci_##name##_in(struct uart_port *port)    \
 291   {                                                                     \
 292     SCI_IN(scif_size, scif_offset);                                     \
 293   }                                                                     \
 294   static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
 295   {                                                                     \
 296     SCI_OUT(scif_size, scif_offset, value);                             \
 297   }
 298
 299 #define CPU_SCI_FNS(name, sci_offset, sci_size)                         \
 300   static inline unsigned int sci_##name##_in(struct uart_port* port)    \
 301   {                                                                     \
 302     SCI_IN(sci_size, sci_offset);                                       \
 303   }                                                                     \
 304   static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
 305   {                                                                     \
 306     SCI_OUT(sci_size, sci_offset, value);                               \
 307   }
 308
 309 #ifdef CONFIG_CPU_SH3
 310 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 311 #define SCIF_FNS(name, scif_offset, scif_size) \
 312   CPU_SCIF_FNS(name, scif_offset, scif_size)
 313 #else
 314 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 315                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 316                  h8_sci_offset, h8_sci_size) \
 317   CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
 318 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 319   CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
 320 #endif
 321 #elif defined(__H8300H__) || defined(__H8300S__)
 322 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 323                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 324                  h8_sci_offset, h8_sci_size) \
 325   CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
 326 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
 327 #else
 328 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
 329                  sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
 330                  h8_sci_offset, h8_sci_size) \
 331   CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
 332 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
 333   CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
 334 #endif
 335
 336 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 337 SCIF_FNS(SCSMR,  0x00, 16)
 338 SCIF_FNS(SCBRR,  0x04,  8)
 339 SCIF_FNS(SCSCR,  0x08, 16)
 340 SCIF_FNS(SCTDSR, 0x0c,  8)
 341 SCIF_FNS(SCFER,  0x10, 16)
 342 SCIF_FNS(SCxSR,  0x14, 16)
 343 SCIF_FNS(SCFCR,  0x18, 16)
 344 SCIF_FNS(SCFDR,  0x1c, 16)
 345 SCIF_FNS(SCxTDR, 0x20,  8)
 346 SCIF_FNS(SCxRDR, 0x24,  8)
 347 SCIF_FNS(SCLSR,  0x24, 16)
 348 #else
 349 /*      reg      SCI/SH3   SCI/SH4  SCIF/SH3   SCIF/SH4  SCI/H8*/
 350 /*      name     off  sz   off  sz   off  sz   off  sz   off  sz*/
 351 SCIx_FNS(SCSMR,  0x00,  8, 0x00,  8, 0x00,  8, 0x00, 16, 0x00,  8)
 352 SCIx_FNS(SCBRR,  0x02,  8, 0x04,  8, 0x02,  8, 0x04,  8, 0x01,  8)
 353 SCIx_FNS(SCSCR,  0x04,  8, 0x08,  8, 0x04,  8, 0x08, 16, 0x02,  8)
 354 SCIx_FNS(SCxTDR, 0x06,  8, 0x0c,  8, 0x06,  8, 0x0C,  8, 0x03,  8)
 355 SCIx_FNS(SCxSR,  0x08,  8, 0x10,  8, 0x08, 16, 0x10, 16, 0x04,  8)
 356 SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 357 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 358 SCIF_FNS(SCFDR,                      0x0e, 16, 0x1C, 16)
 359 SCIF_FNS(SCSPTR,                        0,  0, 0x20, 16)
 360 SCIF_FNS(SCLSR,                         0,  0, 0x24, 16)
 361 #endif
 362 #define sci_in(port, reg) sci_##reg##_in(port)
 363 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
 364
 365 /* H8/300 series SCI pins assignment */
 366 #if defined(__H8300H__) || defined(__H8300S__)
 367 static const struct __attribute__((packed)) {
 368         int port;             /* GPIO port no */
 369         unsigned short rx,tx; /* GPIO bit no */
 370 } h8300_sci_pins[] = {
 371 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
 372         {    /* SCI0 */
 373                 .port = H8300_GPIO_P9,
 374                 .rx   = H8300_GPIO_B2,
 375                 .tx   = H8300_GPIO_B0,
 376         },
 377         {    /* SCI1 */
 378                 .port = H8300_GPIO_P9,
 379                 .rx   = H8300_GPIO_B3,
 380                 .tx   = H8300_GPIO_B1,
 381         },
 382         {    /* SCI2 */
 383                 .port = H8300_GPIO_PB,
 384                 .rx   = H8300_GPIO_B7,
 385                 .tx   = H8300_GPIO_B6,
 386         }
 387 #elif defined(CONFIG_H8S2678)
 388         {    /* SCI0 */
 389                 .port = H8300_GPIO_P3,
 390                 .rx   = H8300_GPIO_B2,
 391                 .tx   = H8300_GPIO_B0,
 392         },
 393         {    /* SCI1 */
 394                 .port = H8300_GPIO_P3,
 395                 .rx   = H8300_GPIO_B3,
 396                 .tx   = H8300_GPIO_B1,
 397         },
 398         {    /* SCI2 */
 399                 .port = H8300_GPIO_P5,
 400                 .rx   = H8300_GPIO_B1,
 401                 .tx   = H8300_GPIO_B0,
 402         }
 403 #endif
 404 };
 405 #endif
 406
 407 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
 408 static inline int sci_rxd_in(struct uart_port *port)
 409 {
 410         if (port->mapbase == 0xfffffe80)
 411                 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
 412         return 1;
 413 }
 414 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
 415 static inline int sci_rxd_in(struct uart_port *port)
 416 {
 417         if (port->mapbase == 0xfffffe80)
 418                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
 419         if (port->mapbase == 0xa4000150)
 420                 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
 421         if (port->mapbase == 0xa4000140)
 422                 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
 423         return 1;
 424 }
 425 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
 426 static inline int sci_rxd_in(struct uart_port *port)
 427 {
 428 #ifndef SCIF_ONLY
 429         if (port->mapbase == 0xffe00000)
 430                 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
 431 #endif
 432 #ifndef SCI_ONLY
 433         if (port->mapbase == 0xffe80000)
 434                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 435 #endif
 436         return 1;
 437 }
 438 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
 439 static inline int sci_rxd_in(struct uart_port *port)
 440 {
 441         if (port->mapbase == 0xfe600000)
 442                 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
 443         if (port->mapbase == 0xfe610000)
 444                 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 445         if (port->mapbase == 0xfe620000)
 446                 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
 447 }
 448 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
 449 static inline int sci_rxd_in(struct uart_port *port)
 450 {
 451         if (port->mapbase == 0xa4430000)
 452                 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
 453         return 1;
 454 }
 455 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
 456 static inline int sci_rxd_in(struct uart_port *port)
 457 {
 458         if (port->mapbase == 0xffe00000)
 459                 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
 460         else
 461                 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
 462
 463 }
 464 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
 465 static inline int sci_rxd_in(struct uart_port *port)
 466 {
 467          return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
 468 }
 469 #elif defined(__H8300H__) || defined(__H8300S__)
 470 static inline int sci_rxd_in(struct uart_port *port)
 471 {
 472         int ch = (port->mapbase - SMR0) >> 3;
 473         return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
 474 }
 475 #endif
 476
 477 /*
 478  * Values for the BitRate Register (SCBRR)
 479  *
 480  * The values are actually divisors for a frequency which can
 481  * be internal to the SH3 (14.7456MHz) or derived from an external
 482  * clock source.  This driver assumes the internal clock is used;
 483  * to support using an external clock source, config options or
 484  * possibly command-line options would need to be added.
 485  *
 486  * Also, to support speeds below 2400 (why?) the lower 2 bits of
 487  * the SCSMR register would also need to be set to non-zero values.
 488  *
 489  * -- Greg Banks 27Feb2000
 490  *
 491  * Answer: The SCBRR register is only eight bits, and the value in
 492  * it gets larger with lower baud rates. At around 2400 (depending on
 493  * the peripherial module clock) you run out of bits. However the
 494  * lower two bits of SCSMR allow the module clock to be divided down,
 495  * scaling the value which is needed in SCBRR.
 496  *
 497  * -- Stuart Menefy - 23 May 2000
 498  *
 499  * I meant, why would anyone bother with bitrates below 2400.
 500  *
 501  * -- Greg Banks - 7Jul2000
 502  *
 503  * You "speedist"!  How will I use my 110bps ASR-33 teletype with paper
 504  * tape reader as a console!
 505  *
 506  * -- Mitch Davis - 15 Jul 2000
 507  */
 508
 509 #define PCLK           (current_cpu_data.module_clock)
 510
 511 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
 512 #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(16*bps)-1)
 513 #elif !defined(__H8300H__) && !defined(__H8300S__)
 514 #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
 515 #else
 516 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
 517 #endif
 518 #define BPS_2400       SCBRR_VALUE(2400)
 519 #define BPS_4800       SCBRR_VALUE(4800)
 520 #define BPS_9600       SCBRR_VALUE(9600)
 521 #define BPS_19200      SCBRR_VALUE(19200)
 522 #define BPS_38400      SCBRR_VALUE(38400)
 523 #define BPS_57600      SCBRR_VALUE(57600)
 524 #define BPS_115200     SCBRR_VALUE(115200)
 525