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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / scsi / sym53c8xx_2 / sym_fw1.h
blobafb3309b935163dc824a4ba1f4f636fa88f84a04
1 /*
2 * Device driver for the SYMBIOS/LSILOGIC 53C8XX and 53C1010 family
3 * of PCI-SCSI IO processors.
4 *
5 * Copyright (C) 1999-2001 Gerard Roudier <groudier@free.fr>
6 *
7 * This driver is derived from the Linux sym53c8xx driver.
8 * Copyright (C) 1998-2000 Gerard Roudier
9 *
10 * The sym53c8xx driver is derived from the ncr53c8xx driver that had been
11 * a port of the FreeBSD ncr driver to Linux-1.2.13.
12 *
13 * The original ncr driver has been written for 386bsd and FreeBSD by
14 * Wolfgang Stanglmeier <wolf@cologne.de>
15 * Stefan Esser <se@mi.Uni-Koeln.de>
16 * Copyright (C) 1994 Wolfgang Stanglmeier
17 *
18 * Other major contributions:
19 *
20 * NVRAM detection and reading.
21 * Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
22 *
23 *-----------------------------------------------------------------------------
24 *
25 * Redistribution and use in source and binary forms, with or without
26 * modification, are permitted provided that the following conditions
27 * are met:
28 * 1. Redistributions of source code must retain the above copyright
29 * notice, this list of conditions and the following disclaimer.
30 * 2. The name of the author may not be used to endorse or promote products
31 * derived from this software without specific prior written permission.
32 *
33 * Where this Software is combined with software released under the terms of
34 * the GNU Public License ("GPL") and the terms of the GPL would require the
35 * combined work to also be released under the terms of the GPL, the terms
36 * and conditions of this License will apply in addition to those of the
37 * GPL with the exception of any terms or conditions of this License that
38 * conflict with, or are expressly prohibited by, the GPL.
39 *
40 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND
41 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
42 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
43 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
44 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
45 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
46 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
47 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
48 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
49 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
50 * SUCH DAMAGE.
51 */
52
53 /*
54 * Scripts for SYMBIOS-Processor
55 *
56 * We have to know the offsets of all labels before we reach
57 * them (for forward jumps). Therefore we declare a struct
58 * here. If you make changes inside the script,
59 *
60 * DONT FORGET TO CHANGE THE LENGTHS HERE!
61 */
62
63 /*
64 * Script fragments which are loaded into the on-chip RAM
65 * of 825A, 875, 876, 895, 895A, 896 and 1010 chips.
66 * Must not exceed 4K bytes.
67 */
68 struct SYM_FWA_SCR {
69 u32 start [ 11];
70 u32 getjob_begin [ 4];
71 u32 _sms_a10 [ 5];
72 u32 getjob_end [ 4];
73 u32 _sms_a20 [ 4];
74 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
75 u32 select [ 8];
76 #else
77 u32 select [ 6];
78 #endif
79 u32 _sms_a30 [ 5];
80 u32 wf_sel_done [ 2];
81 u32 send_ident [ 2];
82 #ifdef SYM_CONF_IARB_SUPPORT
83 u32 select2 [ 8];
84 #else
85 u32 select2 [ 2];
86 #endif
87 u32 command [ 2];
88 u32 dispatch [ 28];
89 u32 sel_no_cmd [ 10];
90 u32 init [ 6];
91 u32 clrack [ 4];
92 u32 datai_done [ 11];
93 u32 datai_done_wsr [ 20];
94 u32 datao_done [ 11];
95 u32 datao_done_wss [ 6];
96 u32 datai_phase [ 5];
97 u32 datao_phase [ 5];
98 u32 msg_in [ 2];
99 u32 msg_in2 [ 10];
100 #ifdef SYM_CONF_IARB_SUPPORT
101 u32 status [ 14];
102 #else
103 u32 status [ 10];
104 #endif
105 u32 complete [ 6];
106 u32 complete2 [ 8];
107 u32 _sms_a40 [ 12];
108 u32 done [ 5];
109 u32 _sms_a50 [ 5];
110 u32 _sms_a60 [ 2];
111 u32 done_end [ 4];
112 u32 complete_error [ 5];
113 u32 save_dp [ 11];
114 u32 restore_dp [ 7];
115 u32 disconnect [ 11];
116 u32 disconnect2 [ 5];
117 u32 _sms_a65 [ 3];
118 #ifdef SYM_CONF_IARB_SUPPORT
119 u32 idle [ 4];
120 #else
121 u32 idle [ 2];
122 #endif
123 #ifdef SYM_CONF_IARB_SUPPORT
124 u32 ungetjob [ 7];
125 #else
126 u32 ungetjob [ 5];
127 #endif
128 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
129 u32 reselect [ 4];
130 #else
131 u32 reselect [ 2];
132 #endif
133 u32 reselected [ 19];
134 u32 _sms_a70 [ 6];
135 u32 _sms_a80 [ 4];
136 u32 reselected1 [ 25];
137 u32 _sms_a90 [ 4];
138 u32 resel_lun0 [ 7];
139 u32 _sms_a100 [ 4];
140 u32 resel_tag [ 8];
141 #if SYM_CONF_MAX_TASK*4 > 512
142 u32 _sms_a110 [ 23];
143 #elif SYM_CONF_MAX_TASK*4 > 256
144 u32 _sms_a110 [ 17];
145 #else
146 u32 _sms_a110 [ 13];
147 #endif
148 u32 _sms_a120 [ 2];
149 u32 resel_go [ 4];
150 u32 _sms_a130 [ 7];
151 u32 resel_dsa [ 2];
152 u32 resel_dsa1 [ 4];
153 u32 _sms_a140 [ 7];
154 u32 resel_no_tag [ 4];
155 u32 _sms_a145 [ 7];
156 u32 data_in [SYM_CONF_MAX_SG * 2];
157 u32 data_in2 [ 4];
158 u32 data_out [SYM_CONF_MAX_SG * 2];
159 u32 data_out2 [ 4];
160 u32 pm0_data [ 12];
161 u32 pm0_data_out [ 6];
162 u32 pm0_data_end [ 7];
163 u32 pm_data_end [ 4];
164 u32 _sms_a150 [ 4];
165 u32 pm1_data [ 12];
166 u32 pm1_data_out [ 6];
167 u32 pm1_data_end [ 9];
168 };
169
170 /*
171 * Script fragments which stay in main memory for all chips
172 * except for chips that support 8K on-chip RAM.
173 */
174 struct SYM_FWB_SCR {
175 u32 no_data [ 2];
176 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
177 u32 sel_for_abort [ 18];
178 #else
179 u32 sel_for_abort [ 16];
180 #endif
181 u32 sel_for_abort_1 [ 2];
182 u32 msg_in_etc [ 12];
183 u32 msg_received [ 5];
184 u32 msg_weird_seen [ 5];
185 u32 msg_extended [ 17];
186 u32 _sms_b10 [ 4];
187 u32 msg_bad [ 6];
188 u32 msg_weird [ 4];
189 u32 msg_weird1 [ 8];
190 u32 wdtr_resp [ 6];
191 u32 send_wdtr [ 4];
192 u32 sdtr_resp [ 6];
193 u32 send_sdtr [ 4];
194 u32 ppr_resp [ 6];
195 u32 send_ppr [ 4];
196 u32 nego_bad_phase [ 4];
197 u32 msg_out [ 4];
198 u32 msg_out_done [ 4];
199 u32 data_ovrun [ 3];
200 u32 data_ovrun1 [ 22];
201 u32 data_ovrun2 [ 8];
202 u32 abort_resel [ 16];
203 u32 resend_ident [ 4];
204 u32 ident_break [ 4];
205 u32 ident_break_atn [ 4];
206 u32 sdata_in [ 6];
207 u32 resel_bad_lun [ 4];
208 u32 bad_i_t_l [ 4];
209 u32 bad_i_t_l_q [ 4];
210 u32 bad_status [ 7];
211 u32 wsr_ma_helper [ 4];
212
213 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN
214 /* Unknown direction handling */
215 u32 data_io [ 2];
216 u32 data_io_com [ 8];
217 u32 data_io_out [ 7];
218 #endif
219 /* Data area */
220 u32 zero [ 1];
221 u32 scratch [ 1];
222 u32 scratch1 [ 1];
223 u32 prev_done [ 1];
224 u32 done_pos [ 1];
225 u32 nextjob [ 1];
226 u32 startpos [ 1];
227 u32 targtbl [ 1];
228 };
229
230 /*
231 * Script fragments used at initialisations.
232 * Only runs out of main memory.
233 */
234 struct SYM_FWZ_SCR {
235 u32 snooptest [ 9];
236 u32 snoopend [ 2];
237 };
238
239 static struct SYM_FWA_SCR SYM_FWA_SCR = {
240 /*--------------------------< START >----------------------------*/ {
241 /*
242 * Switch the LED on.
243 * Will be patched with a NO_OP if LED
244 * not needed or not desired.
245 */
246 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
247 0,
248 /*
249 * Clear SIGP.
250 */
251 SCR_FROM_REG (ctest2),
252 0,
253 /*
254 * Stop here if the C code wants to perform
255 * some error recovery procedure manually.
256 * (Indicate this by setting SEM in ISTAT)
257 */
258 SCR_FROM_REG (istat),
259 0,
260 /*
261 * Report to the C code the next position in
262 * the start queue the SCRIPTS will schedule.
263 * The C code must not change SCRATCHA.
264 */
265 SCR_COPY (4),
266 PADDR_B (startpos),
267 RADDR_1 (scratcha),
268 SCR_INT ^ IFTRUE (MASK (SEM, SEM)),
269 SIR_SCRIPT_STOPPED,
270 /*
271 * Start the next job.
272 *
273 * @DSA = start point for this job.
274 * SCRATCHA = address of this job in the start queue.
275 *
276 * We will restore startpos with SCRATCHA if we fails the
277 * arbitration or if it is the idle job.
278 *
279 * The below GETJOB_BEGIN to GETJOB_END section of SCRIPTS
280 * is a critical path. If it is partially executed, it then
281 * may happen that the job address is not yet in the DSA
282 * and the next queue position points to the next JOB.
283 */
284 }/*-------------------------< GETJOB_BEGIN >---------------------*/,{
285 /*
286 * Copy to a fixed location both the next STARTPOS
287 * and the current JOB address, using self modifying
288 * SCRIPTS.
289 */
290 SCR_COPY (4),
291 RADDR_1 (scratcha),
292 PADDR_A (_sms_a10),
293 SCR_COPY (8),
294 }/*-------------------------< _SMS_A10 >-------------------------*/,{
295 0,
296 PADDR_B (nextjob),
297 /*
298 * Move the start address to TEMP using self-
299 * modifying SCRIPTS and jump indirectly to
300 * that address.
301 */
302 SCR_COPY (4),
303 PADDR_B (nextjob),
304 RADDR_1 (dsa),
305 }/*-------------------------< GETJOB_END >-----------------------*/,{
306 SCR_COPY (4),
307 RADDR_1 (dsa),
308 PADDR_A (_sms_a20),
309 SCR_COPY (4),
310 }/*-------------------------< _SMS_A20 >-------------------------*/,{
311 0,
312 RADDR_1 (temp),
313 SCR_RETURN,
314 0,
315 }/*-------------------------< SELECT >---------------------------*/,{
316 /*
317 * DSA contains the address of a scheduled
318 * data structure.
319 *
320 * SCRATCHA contains the address of the start queue
321 * entry which points to the next job.
322 *
323 * Set Initiator mode.
324 *
325 * (Target mode is left as an exercise for the reader)
326 */
327 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
328 SCR_CLR (SCR_TRG),
329 0,
330 #endif
331 /*
332 * And try to select this target.
333 */
334 SCR_SEL_TBL_ATN ^ offsetof (struct sym_dsb, select),
335 PADDR_A (ungetjob),
336 /*
337 * Now there are 4 possibilities:
338 *
339 * (1) The chip loses arbitration.
340 * This is ok, because it will try again,
341 * when the bus becomes idle.
342 * (But beware of the timeout function!)
343 *
344 * (2) The chip is reselected.
345 * Then the script processor takes the jump
346 * to the RESELECT label.
347 *
348 * (3) The chip wins arbitration.
349 * Then it will execute SCRIPTS instruction until
350 * the next instruction that checks SCSI phase.
351 * Then will stop and wait for selection to be
352 * complete or selection time-out to occur.
353 *
354 * After having won arbitration, the SCRIPTS
355 * processor is able to execute instructions while
356 * the SCSI core is performing SCSI selection.
357 */
358
359 /*
360 * Copy the CCB header to a fixed location
361 * in the HCB using self-modifying SCRIPTS.
362 */
363 SCR_COPY (4),
364 RADDR_1 (dsa),
365 PADDR_A (_sms_a30),
366 SCR_COPY (sizeof(struct sym_ccbh)),
367 }/*-------------------------< _SMS_A30 >-------------------------*/,{
368 0,
369 HADDR_1 (ccb_head),
370 /*
371 * Initialize the status register
372 */
373 SCR_COPY (4),
374 HADDR_1 (ccb_head.status),
375 RADDR_1 (scr0),
376 }/*-------------------------< WF_SEL_DONE >----------------------*/,{
377 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_OUT)),
378 SIR_SEL_ATN_NO_MSG_OUT,
379 }/*-------------------------< SEND_IDENT >-----------------------*/,{
380 /*
381 * Selection complete.
382 * Send the IDENTIFY and possibly the TAG message
383 * and negotiation message if present.
384 */
385 SCR_MOVE_TBL ^ SCR_MSG_OUT,
386 offsetof (struct sym_dsb, smsg),
387 }/*-------------------------< SELECT2 >--------------------------*/,{
388 #ifdef SYM_CONF_IARB_SUPPORT
389 /*
390 * Set IMMEDIATE ARBITRATION if we have been given
391 * a hint to do so. (Some job to do after this one).
392 */
393 SCR_FROM_REG (HF_REG),
394 0,
395 SCR_JUMPR ^ IFFALSE (MASK (HF_HINT_IARB, HF_HINT_IARB)),
396 8,
397 SCR_REG_REG (scntl1, SCR_OR, IARB),
398 0,
399 #endif
400 /*
401 * Anticipate the COMMAND phase.
402 * This is the PHASE we expect at this point.
403 */
404 SCR_JUMP ^ IFFALSE (WHEN (SCR_COMMAND)),
405 PADDR_A (sel_no_cmd),
406 }/*-------------------------< COMMAND >--------------------------*/,{
407 /*
408 * ... and send the command
409 */
410 SCR_MOVE_TBL ^ SCR_COMMAND,
411 offsetof (struct sym_dsb, cmd),
412 }/*-------------------------< DISPATCH >-------------------------*/,{
413 /*
414 * MSG_IN is the only phase that shall be
415 * entered at least once for each (re)selection.
416 * So we test it first.
417 */
418 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
419 PADDR_A (msg_in),
420 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_OUT)),
421 PADDR_A (datao_phase),
422 SCR_JUMP ^ IFTRUE (IF (SCR_DATA_IN)),
423 PADDR_A (datai_phase),
424 SCR_JUMP ^ IFTRUE (IF (SCR_STATUS)),
425 PADDR_A (status),
426 SCR_JUMP ^ IFTRUE (IF (SCR_COMMAND)),
427 PADDR_A (command),
428 SCR_JUMP ^ IFTRUE (IF (SCR_MSG_OUT)),
429 PADDR_B (msg_out),
430 /*
431 * Discard as many illegal phases as
432 * required and tell the C code about.
433 */
434 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_OUT)),
435 16,
436 SCR_MOVE_ABS (1) ^ SCR_ILG_OUT,
437 HADDR_1 (scratch),
438 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_OUT)),
439 -16,
440 SCR_JUMPR ^ IFFALSE (WHEN (SCR_ILG_IN)),
441 16,
442 SCR_MOVE_ABS (1) ^ SCR_ILG_IN,
443 HADDR_1 (scratch),
444 SCR_JUMPR ^ IFTRUE (WHEN (SCR_ILG_IN)),
445 -16,
446 SCR_INT,
447 SIR_BAD_PHASE,
448 SCR_JUMP,
449 PADDR_A (dispatch),
450 }/*-------------------------< SEL_NO_CMD >-----------------------*/,{
451 /*
452 * The target does not switch to command
453 * phase after IDENTIFY has been sent.
454 *
455 * If it stays in MSG OUT phase send it
456 * the IDENTIFY again.
457 */
458 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
459 PADDR_B (resend_ident),
460 /*
461 * If target does not switch to MSG IN phase
462 * and we sent a negotiation, assert the
463 * failure immediately.
464 */
465 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
466 PADDR_A (dispatch),
467 SCR_FROM_REG (HS_REG),
468 0,
469 SCR_INT ^ IFTRUE (DATA (HS_NEGOTIATE)),
470 SIR_NEGO_FAILED,
471 /*
472 * Jump to dispatcher.
473 */
474 SCR_JUMP,
475 PADDR_A (dispatch),
476 }/*-------------------------< INIT >-----------------------------*/,{
477 /*
478 * Wait for the SCSI RESET signal to be
479 * inactive before restarting operations,
480 * since the chip may hang on SEL_ATN
481 * if SCSI RESET is active.
482 */
483 SCR_FROM_REG (sstat0),
484 0,
485 SCR_JUMPR ^ IFTRUE (MASK (IRST, IRST)),
486 -16,
487 SCR_JUMP,
488 PADDR_A (start),
489 }/*-------------------------< CLRACK >---------------------------*/,{
490 /*
491 * Terminate possible pending message phase.
492 */
493 SCR_CLR (SCR_ACK),
494 0,
495 SCR_JUMP,
496 PADDR_A (dispatch),
497 }/*-------------------------< DATAI_DONE >-----------------------*/,{
498 /*
499 * Save current pointer to LASTP.
500 */
501 SCR_COPY (4),
502 RADDR_1 (temp),
503 HADDR_1 (ccb_head.lastp),
504 /*
505 * If the SWIDE is not full, jump to dispatcher.
506 * We anticipate a STATUS phase.
507 */
508 SCR_FROM_REG (scntl2),
509 0,
510 SCR_JUMP ^ IFTRUE (MASK (WSR, WSR)),
511 PADDR_A (datai_done_wsr),
512 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
513 PADDR_A (status),
514 SCR_JUMP,
515 PADDR_A (dispatch),
516 }/*-------------------------< DATAI_DONE_WSR >-------------------*/,{
517 /*
518 * The SWIDE is full.
519 * Clear this condition.
520 */
521 SCR_REG_REG (scntl2, SCR_OR, WSR),
522 0,
523 /*
524 * We are expecting an IGNORE RESIDUE message
525 * from the device, otherwise we are in data
526 * overrun condition. Check against MSG_IN phase.
527 */
528 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
529 SIR_SWIDE_OVERRUN,
530 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
531 PADDR_A (dispatch),
532 /*
533 * We are in MSG_IN phase,
534 * Read the first byte of the message.
535 * If it is not an IGNORE RESIDUE message,
536 * signal overrun and jump to message
537 * processing.
538 */
539 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
540 HADDR_1 (msgin[0]),
541 SCR_INT ^ IFFALSE (DATA (M_IGN_RESIDUE)),
542 SIR_SWIDE_OVERRUN,
543 SCR_JUMP ^ IFFALSE (DATA (M_IGN_RESIDUE)),
544 PADDR_A (msg_in2),
545 /*
546 * We got the message we expected.
547 * Read the 2nd byte, and jump to dispatcher.
548 */
549 SCR_CLR (SCR_ACK),
550 0,
551 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
552 HADDR_1 (msgin[1]),
553 SCR_CLR (SCR_ACK),
554 0,
555 SCR_JUMP,
556 PADDR_A (dispatch),
557 }/*-------------------------< DATAO_DONE >-----------------------*/,{
558 /*
559 * Save current pointer to LASTP.
560 */
561 SCR_COPY (4),
562 RADDR_1 (temp),
563 HADDR_1 (ccb_head.lastp),
564 /*
565 * If the SODL is not full jump to dispatcher.
566 * We anticipate a STATUS phase.
567 */
568 SCR_FROM_REG (scntl2),
569 0,
570 SCR_JUMP ^ IFTRUE (MASK (WSS, WSS)),
571 PADDR_A (datao_done_wss),
572 SCR_JUMP ^ IFTRUE (WHEN (SCR_STATUS)),
573 PADDR_A (status),
574 SCR_JUMP,
575 PADDR_A (dispatch),
576 }/*-------------------------< DATAO_DONE_WSS >-------------------*/,{
577 /*
578 * The SODL is full, clear this condition.
579 */
580 SCR_REG_REG (scntl2, SCR_OR, WSS),
581 0,
582 /*
583 * And signal a DATA UNDERRUN condition
584 * to the C code.
585 */
586 SCR_INT,
587 SIR_SODL_UNDERRUN,
588 SCR_JUMP,
589 PADDR_A (dispatch),
590 }/*-------------------------< DATAI_PHASE >----------------------*/,{
591 /*
592 * Jump to current pointer.
593 */
594 SCR_COPY (4),
595 HADDR_1 (ccb_head.lastp),
596 RADDR_1 (temp),
597 SCR_RETURN,
598 0,
599 }/*-------------------------< DATAO_PHASE >----------------------*/,{
600 /*
601 * Jump to current pointer.
602 */
603 SCR_COPY (4),
604 HADDR_1 (ccb_head.lastp),
605 RADDR_1 (temp),
606 SCR_RETURN,
607 0,
608 }/*-------------------------< MSG_IN >---------------------------*/,{
609 /*
610 * Get the first byte of the message.
611 *
612 * The script processor doesn't negate the
613 * ACK signal after this transfer.
614 */
615 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
616 HADDR_1 (msgin[0]),
617 }/*-------------------------< MSG_IN2 >--------------------------*/,{
618 /*
619 * Check first against 1 byte messages
620 * that we handle from SCRIPTS.
621 */
622 SCR_JUMP ^ IFTRUE (DATA (M_COMPLETE)),
623 PADDR_A (complete),
624 SCR_JUMP ^ IFTRUE (DATA (M_DISCONNECT)),
625 PADDR_A (disconnect),
626 SCR_JUMP ^ IFTRUE (DATA (M_SAVE_DP)),
627 PADDR_A (save_dp),
628 SCR_JUMP ^ IFTRUE (DATA (M_RESTORE_DP)),
629 PADDR_A (restore_dp),
630 /*
631 * We handle all other messages from the
632 * C code, so no need to waste on-chip RAM
633 * for those ones.
634 */
635 SCR_JUMP,
636 PADDR_B (msg_in_etc),
637 }/*-------------------------< STATUS >---------------------------*/,{
638 /*
639 * get the status
640 */
641 SCR_MOVE_ABS (1) ^ SCR_STATUS,
642 HADDR_1 (scratch),
643 #ifdef SYM_CONF_IARB_SUPPORT
644 /*
645 * If STATUS is not GOOD, clear IMMEDIATE ARBITRATION,
646 * since we may have to tamper the start queue from
647 * the C code.
648 */
649 SCR_JUMPR ^ IFTRUE (DATA (S_GOOD)),
650 8,
651 SCR_REG_REG (scntl1, SCR_AND, ~IARB),
652 0,
653 #endif
654 /*
655 * save status to scsi_status.
656 * mark as complete.
657 */
658 SCR_TO_REG (SS_REG),
659 0,
660 SCR_LOAD_REG (HS_REG, HS_COMPLETE),
661 0,
662 /*
663 * Anticipate the MESSAGE PHASE for
664 * the TASK COMPLETE message.
665 */
666 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
667 PADDR_A (msg_in),
668 SCR_JUMP,
669 PADDR_A (dispatch),
670 }/*-------------------------< COMPLETE >-------------------------*/,{
671 /*
672 * Complete message.
673 *
674 * When we terminate the cycle by clearing ACK,
675 * the target may disconnect immediately.
676 *
677 * We don't want to be told of an "unexpected disconnect",
678 * so we disable this feature.
679 */
680 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
681 0,
682 /*
683 * Terminate cycle ...
684 */
685 SCR_CLR (SCR_ACK|SCR_ATN),
686 0,
687 /*
688 * ... and wait for the disconnect.
689 */
690 SCR_WAIT_DISC,
691 0,
692 }/*-------------------------< COMPLETE2 >------------------------*/,{
693 /*
694 * Save host status.
695 */
696 SCR_COPY (4),
697 RADDR_1 (scr0),
698 HADDR_1 (ccb_head.status),
699 /*
700 * Move back the CCB header using self-modifying
701 * SCRIPTS.
702 */
703 SCR_COPY (4),
704 RADDR_1 (dsa),
705 PADDR_A (_sms_a40),
706 SCR_COPY (sizeof(struct sym_ccbh)),
707 HADDR_1 (ccb_head),
708 }/*-------------------------< _SMS_A40 >-------------------------*/,{
709 0,
710 /*
711 * Some bridges may reorder DMA writes to memory.
712 * We donnot want the CPU to deal with completions
713 * without all the posted write having been flushed
714 * to memory. This DUMMY READ should flush posted
715 * buffers prior to the CPU having to deal with
716 * completions.
717 */
718 SCR_COPY (4), /* DUMMY READ */
719 HADDR_1 (ccb_head.status),
720 RADDR_1 (scr0),
721 /*
722 * If command resulted in not GOOD status,
723 * call the C code if needed.
724 */
725 SCR_FROM_REG (SS_REG),
726 0,
727 SCR_CALL ^ IFFALSE (DATA (S_GOOD)),
728 PADDR_B (bad_status),
729 /*
730 * If we performed an auto-sense, call
731 * the C code to synchronyze task aborts
732 * with UNIT ATTENTION conditions.
733 */
734 SCR_FROM_REG (HF_REG),
735 0,
736 SCR_JUMP ^ IFFALSE (MASK (0 ,(HF_SENSE|HF_EXT_ERR))),
737 PADDR_A (complete_error),
738 }/*-------------------------< DONE >-----------------------------*/,{
739 /*
740 * Copy the DSA to the DONE QUEUE and
741 * signal completion to the host.
742 * If we are interrupted between DONE
743 * and DONE_END, we must reset, otherwise
744 * the completed CCB may be lost.
745 */
746 SCR_COPY (4),
747 PADDR_B (done_pos),
748 PADDR_A (_sms_a50),
749 SCR_COPY (4),
750 RADDR_1 (dsa),
751 }/*-------------------------< _SMS_A50 >-------------------------*/,{
752 0,
753 SCR_COPY (4),
754 PADDR_B (done_pos),
755 PADDR_A (_sms_a60),
756 /*
757 * The instruction below reads the DONE QUEUE next
758 * free position from memory.
759 * In addition it ensures that all PCI posted writes
760 * are flushed and so the DSA value of the done
761 * CCB is visible by the CPU before INTFLY is raised.
762 */
763 SCR_COPY (8),
764 }/*-------------------------< _SMS_A60 >-------------------------*/,{
765 0,
766 PADDR_B (prev_done),
767 }/*-------------------------< DONE_END >-------------------------*/,{
768 SCR_INT_FLY,
769 0,
770 SCR_JUMP,
771 PADDR_A (start),
772 }/*-------------------------< COMPLETE_ERROR >-------------------*/,{
773 SCR_COPY (4),
774 PADDR_B (startpos),
775 RADDR_1 (scratcha),
776 SCR_INT,
777 SIR_COMPLETE_ERROR,
778 }/*-------------------------< SAVE_DP >--------------------------*/,{
779 /*
780 * Clear ACK immediately.
781 * No need to delay it.
782 */
783 SCR_CLR (SCR_ACK),
784 0,
785 /*
786 * Keep track we received a SAVE DP, so
787 * we will switch to the other PM context
788 * on the next PM since the DP may point
789 * to the current PM context.
790 */
791 SCR_REG_REG (HF_REG, SCR_OR, HF_DP_SAVED),
792 0,
793 /*
794 * SAVE_DP message:
795 * Copy LASTP to SAVEP.
796 */
797 SCR_COPY (4),
798 HADDR_1 (ccb_head.lastp),
799 HADDR_1 (ccb_head.savep),
800 /*
801 * Anticipate the MESSAGE PHASE for
802 * the DISCONNECT message.
803 */
804 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_IN)),
805 PADDR_A (msg_in),
806 SCR_JUMP,
807 PADDR_A (dispatch),
808 }/*-------------------------< RESTORE_DP >-----------------------*/,{
809 /*
810 * Clear ACK immediately.
811 * No need to delay it.
812 */
813 SCR_CLR (SCR_ACK),
814 0,
815 /*
816 * Copy SAVEP to LASTP.
817 */
818 SCR_COPY (4),
819 HADDR_1 (ccb_head.savep),
820 HADDR_1 (ccb_head.lastp),
821 SCR_JUMP,
822 PADDR_A (dispatch),
823 }/*-------------------------< DISCONNECT >-----------------------*/,{
824 /*
825 * DISCONNECTing ...
826 *
827 * disable the "unexpected disconnect" feature,
828 * and remove the ACK signal.
829 */
830 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
831 0,
832 SCR_CLR (SCR_ACK|SCR_ATN),
833 0,
834 /*
835 * Wait for the disconnect.
836 */
837 SCR_WAIT_DISC,
838 0,
839 /*
840 * Status is: DISCONNECTED.
841 */
842 SCR_LOAD_REG (HS_REG, HS_DISCONNECT),
843 0,
844 /*
845 * Save host status.
846 */
847 SCR_COPY (4),
848 RADDR_1 (scr0),
849 HADDR_1 (ccb_head.status),
850 }/*-------------------------< DISCONNECT2 >----------------------*/,{
851 /*
852 * Move back the CCB header using self-modifying
853 * SCRIPTS.
854 */
855 SCR_COPY (4),
856 RADDR_1 (dsa),
857 PADDR_A (_sms_a65),
858 SCR_COPY (sizeof(struct sym_ccbh)),
859 HADDR_1 (ccb_head),
860 }/*-------------------------< _SMS_A65 >-------------------------*/,{
861 0,
862 SCR_JUMP,
863 PADDR_A (start),
864 }/*-------------------------< IDLE >-----------------------------*/,{
865 /*
866 * Nothing to do?
867 * Switch the LED off and wait for reselect.
868 * Will be patched with a NO_OP if LED
869 * not needed or not desired.
870 */
871 SCR_REG_REG (gpreg, SCR_OR, 0x01),
872 0,
873 #ifdef SYM_CONF_IARB_SUPPORT
874 SCR_JUMPR,
875 8,
876 #endif
877 }/*-------------------------< UNGETJOB >-------------------------*/,{
878 #ifdef SYM_CONF_IARB_SUPPORT
879 /*
880 * Set IMMEDIATE ARBITRATION, for the next time.
881 * This will give us better chance to win arbitration
882 * for the job we just wanted to do.
883 */
884 SCR_REG_REG (scntl1, SCR_OR, IARB),
885 0,
886 #endif
887 /*
888 * We are not able to restart the SCRIPTS if we are
889 * interrupted and these instruction haven't been
890 * all executed. BTW, this is very unlikely to
891 * happen, but we check that from the C code.
892 */
893 SCR_LOAD_REG (dsa, 0xff),
894 0,
895 SCR_COPY (4),
896 RADDR_1 (scratcha),
897 PADDR_B (startpos),
898 }/*-------------------------< RESELECT >-------------------------*/,{
899 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
900 /*
901 * Make sure we are in initiator mode.
902 */
903 SCR_CLR (SCR_TRG),
904 0,
905 #endif
906 /*
907 * Sleep waiting for a reselection.
908 */
909 SCR_WAIT_RESEL,
910 PADDR_A(start),
911 }/*-------------------------< RESELECTED >-----------------------*/,{
912 /*
913 * Switch the LED on.
914 * Will be patched with a NO_OP if LED
915 * not needed or not desired.
916 */
917 SCR_REG_REG (gpreg, SCR_AND, 0xfe),
918 0,
919 /*
920 * load the target id into the sdid
921 */
922 SCR_REG_SFBR (ssid, SCR_AND, 0x8F),
923 0,
924 SCR_TO_REG (sdid),
925 0,
926 /*
927 * Load the target control block address
928 */
929 SCR_COPY (4),
930 PADDR_B (targtbl),
931 RADDR_1 (dsa),
932 SCR_SFBR_REG (dsa, SCR_SHL, 0),
933 0,
934 SCR_REG_REG (dsa, SCR_SHL, 0),
935 0,
936 SCR_REG_REG (dsa, SCR_AND, 0x3c),
937 0,
938 SCR_COPY (4),
939 RADDR_1 (dsa),
940 PADDR_A (_sms_a70),
941 SCR_COPY (4),
942 }/*-------------------------< _SMS_A70 >-------------------------*/,{
943 0,
944 RADDR_1 (dsa),
945 /*
946 * Copy the TCB header to a fixed place in
947 * the HCB.
948 */
949 SCR_COPY (4),
950 RADDR_1 (dsa),
951 PADDR_A (_sms_a80),
952 SCR_COPY (sizeof(struct sym_tcbh)),
953 }/*-------------------------< _SMS_A80 >-------------------------*/,{
954 0,
955 HADDR_1 (tcb_head),
956 /*
957 * We expect MESSAGE IN phase.
958 * If not, get help from the C code.
959 */
960 SCR_INT ^ IFFALSE (WHEN (SCR_MSG_IN)),
961 SIR_RESEL_NO_MSG_IN,
962 }/*-------------------------< RESELECTED1 >----------------------*/,{
963 /*
964 * Load the synchronous transfer registers.
965 */
966 SCR_COPY (1),
967 HADDR_1 (tcb_head.wval),
968 RADDR_1 (scntl3),
969 SCR_COPY (1),
970 HADDR_1 (tcb_head.sval),
971 RADDR_1 (sxfer),
972 /*
973 * Get the IDENTIFY message.
974 */
975 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
976 HADDR_1 (msgin),
977 /*
978 * If IDENTIFY LUN #0, use a faster path
979 * to find the LCB structure.
980 */
981 SCR_JUMP ^ IFTRUE (MASK (0x80, 0xbf)),
982 PADDR_A (resel_lun0),
983 /*
984 * If message isn't an IDENTIFY,
985 * tell the C code about.
986 */
987 SCR_INT ^ IFFALSE (MASK (0x80, 0x80)),
988 SIR_RESEL_NO_IDENTIFY,
989 /*
990 * It is an IDENTIFY message,
991 * Load the LUN control block address.
992 */
993 SCR_COPY (4),
994 HADDR_1 (tcb_head.luntbl_sa),
995 RADDR_1 (dsa),
996 SCR_SFBR_REG (dsa, SCR_SHL, 0),
997 0,
998 SCR_REG_REG (dsa, SCR_SHL, 0),
999 0,
1000 SCR_REG_REG (dsa, SCR_AND, 0xfc),
1001 0,
1002 SCR_COPY (4),
1003 RADDR_1 (dsa),
1004 PADDR_A (_sms_a90),
1005 SCR_COPY (4),
1006 }/*-------------------------< _SMS_A90 >-------------------------*/,{
1007 0,
1008 RADDR_1 (dsa),
1009 SCR_JUMPR,
1010 12,
1011 }/*-------------------------< RESEL_LUN0 >-----------------------*/,{
1012 /*
1013 * LUN 0 special case (but usual one :))
1014 */
1015 SCR_COPY (4),
1016 HADDR_1 (tcb_head.lun0_sa),
1017 RADDR_1 (dsa),
1018 /*
1019 * Jump indirectly to the reselect action for this LUN.
1020 * (lcb.head.resel_sa assumed at offset zero of lcb).
1021 */
1022 SCR_COPY (4),
1023 RADDR_1 (dsa),
1024 PADDR_A (_sms_a100),
1025 SCR_COPY (4),
1026 }/*-------------------------< _SMS_A100 >------------------------*/,{
1027 0,
1028 RADDR_1 (temp),
1029 SCR_RETURN,
1030 0,
1031 /* In normal situations, we jump to RESEL_TAG or RESEL_NO_TAG */
1032 }/*-------------------------< RESEL_TAG >------------------------*/,{
1033 /*
1034 * ACK the IDENTIFY previously received.
1035 */
1036 SCR_CLR (SCR_ACK),
1037 0,
1038 /*
1039 * It shall be a tagged command.
1040 * Read SIMPLE+TAG.
1041 * The C code will deal with errors.
1042 * Agressive optimization, is'nt it? :)
1043 */
1044 SCR_MOVE_ABS (2) ^ SCR_MSG_IN,
1045 HADDR_1 (msgin),
1046 /*
1047 * Copy the LCB header to a fixed place in
1048 * the HCB using self-modifying SCRIPTS.
1049 */
1050 SCR_COPY (4),
1051 RADDR_1 (dsa),
1052 PADDR_A (_sms_a110),
1053 SCR_COPY (sizeof(struct sym_lcbh)),
1054 }/*-------------------------< _SMS_A110 >------------------------*/,{
1055 0,
1056 HADDR_1 (lcb_head),
1057 /*
1058 * Load the pointer to the tagged task
1059 * table for this LUN.
1060 */
1061 SCR_COPY (4),
1062 HADDR_1 (lcb_head.itlq_tbl_sa),
1063 RADDR_1 (dsa),
1064 /*
1065 * The SIDL still contains the TAG value.
1066 * Agressive optimization, isn't it? :):)
1067 */
1068 SCR_REG_SFBR (sidl, SCR_SHL, 0),
1069 0,
1070 #if SYM_CONF_MAX_TASK*4 > 512
1071 SCR_JUMPR ^ IFFALSE (CARRYSET),
1072 8,
1073 SCR_REG_REG (dsa1, SCR_OR, 2),
1074 0,
1075 SCR_REG_REG (sfbr, SCR_SHL, 0),
1076 0,
1077 SCR_JUMPR ^ IFFALSE (CARRYSET),
1078 8,
1079 SCR_REG_REG (dsa1, SCR_OR, 1),
1080 0,
1081 #elif SYM_CONF_MAX_TASK*4 > 256
1082 SCR_JUMPR ^ IFFALSE (CARRYSET),
1083 8,
1084 SCR_REG_REG (dsa1, SCR_OR, 1),
1085 0,
1086 #endif
1087 /*
1088 * Retrieve the DSA of this task.
1089 * JUMP indirectly to the restart point of the CCB.
1090 */
1091 SCR_SFBR_REG (dsa, SCR_AND, 0xfc),
1092 0,
1093 SCR_COPY (4),
1094 RADDR_1 (dsa),
1095 PADDR_A (_sms_a120),
1096 SCR_COPY (4),
1097 }/*-------------------------< _SMS_A120 >------------------------*/,{
1098 0,
1099 RADDR_1 (dsa),
1100 }/*-------------------------< RESEL_GO >-------------------------*/,{
1101 SCR_COPY (4),
1102 RADDR_1 (dsa),
1103 PADDR_A (_sms_a130),
1104 /*
1105 * Move 'ccb.phys.head.go' action to
1106 * scratch/scratch1. So scratch1 will
1107 * contain the 'restart' field of the
1108 * 'go' structure.
1109 */
1110 SCR_COPY (8),
1111 }/*-------------------------< _SMS_A130 >------------------------*/,{
1112 0,
1113 PADDR_B (scratch),
1114 SCR_COPY (4),
1115 PADDR_B (scratch1), /* phys.head.go.restart */
1116 RADDR_1 (temp),
1117 SCR_RETURN,
1118 0,
1119 /* In normal situations we branch to RESEL_DSA */
1120 }/*-------------------------< RESEL_DSA >------------------------*/,{
1121 /*
1122 * ACK the IDENTIFY or TAG previously received.
1123 */
1124 SCR_CLR (SCR_ACK),
1125 0,
1126 }/*-------------------------< RESEL_DSA1 >-----------------------*/,{
1127 /*
1128 * Copy the CCB header to a fixed location
1129 * in the HCB using self-modifying SCRIPTS.
1130 */
1131 SCR_COPY (4),
1132 RADDR_1 (dsa),
1133 PADDR_A (_sms_a140),
1134 SCR_COPY (sizeof(struct sym_ccbh)),
1135 }/*-------------------------< _SMS_A140 >------------------------*/,{
1136 0,
1137 HADDR_1 (ccb_head),
1138 /*
1139 * Initialize the status register
1140 */
1141 SCR_COPY (4),
1142 HADDR_1 (ccb_head.status),
1143 RADDR_1 (scr0),
1144 /*
1145 * Jump to dispatcher.
1146 */
1147 SCR_JUMP,
1148 PADDR_A (dispatch),
1149 }/*-------------------------< RESEL_NO_TAG >---------------------*/,{
1150 /*
1151 * Copy the LCB header to a fixed place in
1152 * the HCB using self-modifying SCRIPTS.
1153 */
1154 SCR_COPY (4),
1155 RADDR_1 (dsa),
1156 PADDR_A (_sms_a145),
1157 SCR_COPY (sizeof(struct sym_lcbh)),
1158 }/*-------------------------< _SMS_A145 >------------------------*/,{
1159 0,
1160 HADDR_1 (lcb_head),
1161 /*
1162 * Load the DSA with the unique ITL task.
1163 */
1164 SCR_COPY (4),
1165 HADDR_1 (lcb_head.itl_task_sa),
1166 RADDR_1 (dsa),
1167 SCR_JUMP,
1168 PADDR_A (resel_go),
1169 }/*-------------------------< DATA_IN >--------------------------*/,{
1170 /*
1171 * Because the size depends on the
1172 * #define SYM_CONF_MAX_SG parameter,
1173 * it is filled in at runtime.
1174 *
1175 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1176 * || SCR_CHMOV_TBL ^ SCR_DATA_IN,
1177 * || offsetof (struct sym_dsb, data[ i]),
1178 * ##==========================================
1179 */
1180 0
1181 }/*-------------------------< DATA_IN2 >-------------------------*/,{
1182 SCR_CALL,
1183 PADDR_A (datai_done),
1184 SCR_JUMP,
1185 PADDR_B (data_ovrun),
1186 }/*-------------------------< DATA_OUT >-------------------------*/,{
1187 /*
1188 * Because the size depends on the
1189 * #define SYM_CONF_MAX_SG parameter,
1190 * it is filled in at runtime.
1191 *
1192 * ##===========< i=0; i<SYM_CONF_MAX_SG >=========
1193 * || SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1194 * || offsetof (struct sym_dsb, data[ i]),
1195 * ##==========================================
1196 */
1197 0
1198 }/*-------------------------< DATA_OUT2 >------------------------*/,{
1199 SCR_CALL,
1200 PADDR_A (datao_done),
1201 SCR_JUMP,
1202 PADDR_B (data_ovrun),
1203 }/*-------------------------< PM0_DATA >-------------------------*/,{
1204 /*
1205 * Read our host flags to SFBR, so we will be able
1206 * to check against the data direction we expect.
1207 */
1208 SCR_FROM_REG (HF_REG),
1209 0,
1210 /*
1211 * Check against actual DATA PHASE.
1212 */
1213 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1214 PADDR_A (pm0_data_out),
1215 /*
1216 * Actual phase is DATA IN.
1217 * Check against expected direction.
1218 */
1219 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1220 PADDR_B (data_ovrun),
1221 /*
1222 * Keep track we are moving data from the
1223 * PM0 DATA mini-script.
1224 */
1225 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1226 0,
1227 /*
1228 * Move the data to memory.
1229 */
1230 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1231 offsetof (struct sym_ccb, phys.pm0.sg),
1232 SCR_JUMP,
1233 PADDR_A (pm0_data_end),
1234 }/*-------------------------< PM0_DATA_OUT >---------------------*/,{
1235 /*
1236 * Actual phase is DATA OUT.
1237 * Check against expected direction.
1238 */
1239 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1240 PADDR_B (data_ovrun),
1241 /*
1242 * Keep track we are moving data from the
1243 * PM0 DATA mini-script.
1244 */
1245 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM0),
1246 0,
1247 /*
1248 * Move the data from memory.
1249 */
1250 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1251 offsetof (struct sym_ccb, phys.pm0.sg),
1252 }/*-------------------------< PM0_DATA_END >---------------------*/,{
1253 /*
1254 * Clear the flag that told we were moving
1255 * data from the PM0 DATA mini-script.
1256 */
1257 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM0)),
1258 0,
1259 /*
1260 * Return to the previous DATA script which
1261 * is guaranteed by design (if no bug) to be
1262 * the main DATA script for this transfer.
1263 */
1264 SCR_COPY (4),
1265 RADDR_1 (dsa),
1266 RADDR_1 (scratcha),
1267 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm0.ret)),
1268 0,
1269 }/*-------------------------< PM_DATA_END >----------------------*/,{
1270 SCR_COPY (4),
1271 RADDR_1 (scratcha),
1272 PADDR_A (_sms_a150),
1273 SCR_COPY (4),
1274 }/*-------------------------< _SMS_A150 >------------------------*/,{
1275 0,
1276 RADDR_1 (temp),
1277 SCR_RETURN,
1278 0,
1279 }/*-------------------------< PM1_DATA >-------------------------*/,{
1280 /*
1281 * Read our host flags to SFBR, so we will be able
1282 * to check against the data direction we expect.
1283 */
1284 SCR_FROM_REG (HF_REG),
1285 0,
1286 /*
1287 * Check against actual DATA PHASE.
1288 */
1289 SCR_JUMP ^ IFFALSE (WHEN (SCR_DATA_IN)),
1290 PADDR_A (pm1_data_out),
1291 /*
1292 * Actual phase is DATA IN.
1293 * Check against expected direction.
1294 */
1295 SCR_JUMP ^ IFFALSE (MASK (HF_DATA_IN, HF_DATA_IN)),
1296 PADDR_B (data_ovrun),
1297 /*
1298 * Keep track we are moving data from the
1299 * PM1 DATA mini-script.
1300 */
1301 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1302 0,
1303 /*
1304 * Move the data to memory.
1305 */
1306 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1307 offsetof (struct sym_ccb, phys.pm1.sg),
1308 SCR_JUMP,
1309 PADDR_A (pm1_data_end),
1310 }/*-------------------------< PM1_DATA_OUT >---------------------*/,{
1311 /*
1312 * Actual phase is DATA OUT.
1313 * Check against expected direction.
1314 */
1315 SCR_JUMP ^ IFTRUE (MASK (HF_DATA_IN, HF_DATA_IN)),
1316 PADDR_B (data_ovrun),
1317 /*
1318 * Keep track we are moving data from the
1319 * PM1 DATA mini-script.
1320 */
1321 SCR_REG_REG (HF_REG, SCR_OR, HF_IN_PM1),
1322 0,
1323 /*
1324 * Move the data from memory.
1325 */
1326 SCR_CHMOV_TBL ^ SCR_DATA_OUT,
1327 offsetof (struct sym_ccb, phys.pm1.sg),
1328 }/*-------------------------< PM1_DATA_END >---------------------*/,{
1329 /*
1330 * Clear the flag that told we were moving
1331 * data from the PM1 DATA mini-script.
1332 */
1333 SCR_REG_REG (HF_REG, SCR_AND, (~HF_IN_PM1)),
1334 0,
1335 /*
1336 * Return to the previous DATA script which
1337 * is guaranteed by design (if no bug) to be
1338 * the main DATA script for this transfer.
1339 */
1340 SCR_COPY (4),
1341 RADDR_1 (dsa),
1342 RADDR_1 (scratcha),
1343 SCR_REG_REG (scratcha, SCR_ADD, offsetof (struct sym_ccb,phys.pm1.ret)),
1344 0,
1345 SCR_JUMP,
1346 PADDR_A (pm_data_end),
1347 }/*--------------------------<>----------------------------------*/
1348 };
1349
1350 static struct SYM_FWB_SCR SYM_FWB_SCR = {
1351 /*-------------------------< NO_DATA >--------------------------*/ {
1352 SCR_JUMP,
1353 PADDR_B (data_ovrun),
1354 }/*-------------------------< SEL_FOR_ABORT >--------------------*/,{
1355 /*
1356 * We are jumped here by the C code, if we have
1357 * some target to reset or some disconnected
1358 * job to abort. Since error recovery is a serious
1359 * busyness, we will really reset the SCSI BUS, if
1360 * case of a SCSI interrupt occurring in this path.
1361 */
1362
1363 #ifdef SYM_CONF_TARGET_ROLE_SUPPORT
1364 /*
1365 * Set initiator mode.
1366 */
1367 SCR_CLR (SCR_TRG),
1368 0,
1369 #endif
1370 /*
1371 * And try to select this target.
1372 */
1373 SCR_SEL_TBL_ATN ^ offsetof (struct sym_hcb, abrt_sel),
1374 PADDR_A (reselect),
1375 /*
1376 * Wait for the selection to complete or
1377 * the selection to time out.
1378 */
1379 SCR_JUMPR ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1380 -8,
1381 /*
1382 * Call the C code.
1383 */
1384 SCR_INT,
1385 SIR_TARGET_SELECTED,
1386 /*
1387 * The C code should let us continue here.
1388 * Send the 'kiss of death' message.
1389 * We expect an immediate disconnect once
1390 * the target has eaten the message.
1391 */
1392 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1393 0,
1394 SCR_MOVE_TBL ^ SCR_MSG_OUT,
1395 offsetof (struct sym_hcb, abrt_tbl),
1396 SCR_CLR (SCR_ACK|SCR_ATN),
1397 0,
1398 SCR_WAIT_DISC,
1399 0,
1400 /*
1401 * Tell the C code that we are done.
1402 */
1403 SCR_INT,
1404 SIR_ABORT_SENT,
1405 }/*-------------------------< SEL_FOR_ABORT_1 >------------------*/,{
1406 /*
1407 * Jump at scheduler.
1408 */
1409 SCR_JUMP,
1410 PADDR_A (start),
1411 }/*-------------------------< MSG_IN_ETC >-----------------------*/,{
1412 /*
1413 * If it is an EXTENDED (variable size message)
1414 * Handle it.
1415 */
1416 SCR_JUMP ^ IFTRUE (DATA (M_EXTENDED)),
1417 PADDR_B (msg_extended),
1418 /*
1419 * Let the C code handle any other
1420 * 1 byte message.
1421 */
1422 SCR_JUMP ^ IFTRUE (MASK (0x00, 0xf0)),
1423 PADDR_B (msg_received),
1424 SCR_JUMP ^ IFTRUE (MASK (0x10, 0xf0)),
1425 PADDR_B (msg_received),
1426 /*
1427 * We donnot handle 2 bytes messages from SCRIPTS.
1428 * So, let the C code deal with these ones too.
1429 */
1430 SCR_JUMP ^ IFFALSE (MASK (0x20, 0xf0)),
1431 PADDR_B (msg_weird_seen),
1432 SCR_CLR (SCR_ACK),
1433 0,
1434 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1435 HADDR_1 (msgin[1]),
1436 }/*-------------------------< MSG_RECEIVED >---------------------*/,{
1437 SCR_COPY (4), /* DUMMY READ */
1438 HADDR_1 (scratch),
1439 RADDR_1 (scratcha),
1440 SCR_INT,
1441 SIR_MSG_RECEIVED,
1442 }/*-------------------------< MSG_WEIRD_SEEN >-------------------*/,{
1443 SCR_COPY (4), /* DUMMY READ */
1444 HADDR_1 (scratch),
1445 RADDR_1 (scratcha),
1446 SCR_INT,
1447 SIR_MSG_WEIRD,
1448 }/*-------------------------< MSG_EXTENDED >---------------------*/,{
1449 /*
1450 * Clear ACK and get the next byte
1451 * assumed to be the message length.
1452 */
1453 SCR_CLR (SCR_ACK),
1454 0,
1455 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1456 HADDR_1 (msgin[1]),
1457 /*
1458 * Try to catch some unlikely situations as 0 length
1459 * or too large the length.
1460 */
1461 SCR_JUMP ^ IFTRUE (DATA (0)),
1462 PADDR_B (msg_weird_seen),
1463 SCR_TO_REG (scratcha),
1464 0,
1465 SCR_REG_REG (sfbr, SCR_ADD, (256-8)),
1466 0,
1467 SCR_JUMP ^ IFTRUE (CARRYSET),
1468 PADDR_B (msg_weird_seen),
1469 /*
1470 * We donnot handle extended messages from SCRIPTS.
1471 * Read the amount of data correponding to the
1472 * message length and call the C code.
1473 */
1474 SCR_COPY (1),
1475 RADDR_1 (scratcha),
1476 PADDR_B (_sms_b10),
1477 SCR_CLR (SCR_ACK),
1478 0,
1479 }/*-------------------------< _SMS_B10 >-------------------------*/,{
1480 SCR_MOVE_ABS (0) ^ SCR_MSG_IN,
1481 HADDR_1 (msgin[2]),
1482 SCR_JUMP,
1483 PADDR_B (msg_received),
1484 }/*-------------------------< MSG_BAD >--------------------------*/,{
1485 /*
1486 * unimplemented message - reject it.
1487 */
1488 SCR_INT,
1489 SIR_REJECT_TO_SEND,
1490 SCR_SET (SCR_ATN),
1491 0,
1492 SCR_JUMP,
1493 PADDR_A (clrack),
1494 }/*-------------------------< MSG_WEIRD >------------------------*/,{
1495 /*
1496 * weird message received
1497 * ignore all MSG IN phases and reject it.
1498 */
1499 SCR_INT,
1500 SIR_REJECT_TO_SEND,
1501 SCR_SET (SCR_ATN),
1502 0,
1503 }/*-------------------------< MSG_WEIRD1 >-----------------------*/,{
1504 SCR_CLR (SCR_ACK),
1505 0,
1506 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_IN)),
1507 PADDR_A (dispatch),
1508 SCR_MOVE_ABS (1) ^ SCR_MSG_IN,
1509 HADDR_1 (scratch),
1510 SCR_JUMP,
1511 PADDR_B (msg_weird1),
1512 }/*-------------------------< WDTR_RESP >------------------------*/,{
1513 /*
1514 * let the target fetch our answer.
1515 */
1516 SCR_SET (SCR_ATN),
1517 0,
1518 SCR_CLR (SCR_ACK),
1519 0,
1520 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1521 PADDR_B (nego_bad_phase),
1522 }/*-------------------------< SEND_WDTR >------------------------*/,{
1523 /*
1524 * Send the M_X_WIDE_REQ
1525 */
1526 SCR_MOVE_ABS (4) ^ SCR_MSG_OUT,
1527 HADDR_1 (msgout),
1528 SCR_JUMP,
1529 PADDR_B (msg_out_done),
1530 }/*-------------------------< SDTR_RESP >------------------------*/,{
1531 /*
1532 * let the target fetch our answer.
1533 */
1534 SCR_SET (SCR_ATN),
1535 0,
1536 SCR_CLR (SCR_ACK),
1537 0,
1538 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1539 PADDR_B (nego_bad_phase),
1540 }/*-------------------------< SEND_SDTR >------------------------*/,{
1541 /*
1542 * Send the M_X_SYNC_REQ
1543 */
1544 SCR_MOVE_ABS (5) ^ SCR_MSG_OUT,
1545 HADDR_1 (msgout),
1546 SCR_JUMP,
1547 PADDR_B (msg_out_done),
1548 }/*-------------------------< PPR_RESP >-------------------------*/,{
1549 /*
1550 * let the target fetch our answer.
1551 */
1552 SCR_SET (SCR_ATN),
1553 0,
1554 SCR_CLR (SCR_ACK),
1555 0,
1556 SCR_JUMP ^ IFFALSE (WHEN (SCR_MSG_OUT)),
1557 PADDR_B (nego_bad_phase),
1558 }/*-------------------------< SEND_PPR >-------------------------*/,{
1559 /*
1560 * Send the M_X_PPR_REQ
1561 */
1562 SCR_MOVE_ABS (8) ^ SCR_MSG_OUT,
1563 HADDR_1 (msgout),
1564 SCR_JUMP,
1565 PADDR_B (msg_out_done),
1566 }/*-------------------------< NEGO_BAD_PHASE >-------------------*/,{
1567 SCR_INT,
1568 SIR_NEGO_PROTO,
1569 SCR_JUMP,
1570 PADDR_A (dispatch),
1571 }/*-------------------------< MSG_OUT >--------------------------*/,{
1572 /*
1573 * The target requests a message.
1574 * We donnot send messages that may
1575 * require the device to go to bus free.
1576 */
1577 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1578 HADDR_1 (msgout),
1579 /*
1580 * ... wait for the next phase
1581 * if it's a message out, send it again, ...
1582 */
1583 SCR_JUMP ^ IFTRUE (WHEN (SCR_MSG_OUT)),
1584 PADDR_B (msg_out),
1585 }/*-------------------------< MSG_OUT_DONE >---------------------*/,{
1586 /*
1587 * Let the C code be aware of the
1588 * sent message and clear the message.
1589 */
1590 SCR_INT,
1591 SIR_MSG_OUT_DONE,
1592 /*
1593 * ... and process the next phase
1594 */
1595 SCR_JUMP,
1596 PADDR_A (dispatch),
1597 }/*-------------------------< DATA_OVRUN >-----------------------*/,{
1598 /*
1599 * Zero scratcha that will count the
1600 * extras bytes.
1601 */
1602 SCR_COPY (4),
1603 PADDR_B (zero),
1604 RADDR_1 (scratcha),
1605 }/*-------------------------< DATA_OVRUN1 >----------------------*/,{
1606 /*
1607 * The target may want to transfer too much data.
1608 *
1609 * If phase is DATA OUT write 1 byte and count it.
1610 */
1611 SCR_JUMPR ^ IFFALSE (WHEN (SCR_DATA_OUT)),
1612 16,
1613 SCR_CHMOV_ABS (1) ^ SCR_DATA_OUT,
1614 HADDR_1 (scratch),
1615 SCR_JUMP,
1616 PADDR_B (data_ovrun2),
1617 /*
1618 * If WSR is set, clear this condition, and
1619 * count this byte.
1620 */
1621 SCR_FROM_REG (scntl2),
1622 0,
1623 SCR_JUMPR ^ IFFALSE (MASK (WSR, WSR)),
1624 16,
1625 SCR_REG_REG (scntl2, SCR_OR, WSR),
1626 0,
1627 SCR_JUMP,
1628 PADDR_B (data_ovrun2),
1629 /*
1630 * Finally check against DATA IN phase.
1631 * Signal data overrun to the C code
1632 * and jump to dispatcher if not so.
1633 * Read 1 byte otherwise and count it.
1634 */
1635 SCR_JUMPR ^ IFTRUE (WHEN (SCR_DATA_IN)),
1636 16,
1637 SCR_INT,
1638 SIR_DATA_OVERRUN,
1639 SCR_JUMP,
1640 PADDR_A (dispatch),
1641 SCR_CHMOV_ABS (1) ^ SCR_DATA_IN,
1642 HADDR_1 (scratch),
1643 }/*-------------------------< DATA_OVRUN2 >----------------------*/,{
1644 /*
1645 * Count this byte.
1646 * This will allow to return a negative
1647 * residual to user.
1648 */
1649 SCR_REG_REG (scratcha, SCR_ADD, 0x01),
1650 0,
1651 SCR_REG_REG (scratcha1, SCR_ADDC, 0),
1652 0,
1653 SCR_REG_REG (scratcha2, SCR_ADDC, 0),
1654 0,
1655 /*
1656 * .. and repeat as required.
1657 */
1658 SCR_JUMP,
1659 PADDR_B (data_ovrun1),
1660 }/*-------------------------< ABORT_RESEL >----------------------*/,{
1661 SCR_SET (SCR_ATN),
1662 0,
1663 SCR_CLR (SCR_ACK),
1664 0,
1665 /*
1666 * send the abort/abortag/reset message
1667 * we expect an immediate disconnect
1668 */
1669 SCR_REG_REG (scntl2, SCR_AND, 0x7f),
1670 0,
1671 SCR_MOVE_ABS (1) ^ SCR_MSG_OUT,
1672 HADDR_1 (msgout),
1673 SCR_CLR (SCR_ACK|SCR_ATN),
1674 0,
1675 SCR_WAIT_DISC,
1676 0,
1677 SCR_INT,
1678 SIR_RESEL_ABORTED,
1679 SCR_JUMP,
1680 PADDR_A (start),
1681 }/*-------------------------< RESEND_IDENT >---------------------*/,{
1682 /*
1683 * The target stays in MSG OUT phase after having acked
1684 * Identify [+ Tag [+ Extended message ]]. Targets shall
1685 * behave this way on parity error.
1686 * We must send it again all the messages.
1687 */
1688 SCR_SET (SCR_ATN), /* Shall be asserted 2 deskew delays before the */
1689 0, /* 1rst ACK = 90 ns. Hope the chip isn't too fast */
1690 SCR_JUMP,
1691 PADDR_A (send_ident),
1692 }/*-------------------------< IDENT_BREAK >----------------------*/,{
1693 SCR_CLR (SCR_ATN),
1694 0,
1695 SCR_JUMP,
1696 PADDR_A (select2),
1697 }/*-------------------------< IDENT_BREAK_ATN >------------------*/,{
1698 SCR_SET (SCR_ATN),
1699 0,
1700 SCR_JUMP,
1701 PADDR_A (select2),
1702 }/*-------------------------< SDATA_IN >-------------------------*/,{
1703 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1704 offsetof (struct sym_dsb, sense),
1705 SCR_CALL,
1706 PADDR_A (datai_done),
1707 SCR_JUMP,
1708 PADDR_B (data_ovrun),
1709 }/*-------------------------< RESEL_BAD_LUN >--------------------*/,{
1710 /*
1711 * Message is an IDENTIFY, but lun is unknown.
1712 * Signal problem to C code for logging the event.
1713 * Send a M_ABORT to clear all pending tasks.
1714 */
1715 SCR_INT,
1716 SIR_RESEL_BAD_LUN,
1717 SCR_JUMP,
1718 PADDR_B (abort_resel),
1719 }/*-------------------------< BAD_I_T_L >------------------------*/,{
1720 /*
1721 * We donnot have a task for that I_T_L.
1722 * Signal problem to C code for logging the event.
1723 * Send a M_ABORT message.
1724 */
1725 SCR_INT,
1726 SIR_RESEL_BAD_I_T_L,
1727 SCR_JUMP,
1728 PADDR_B (abort_resel),
1729 }/*-------------------------< BAD_I_T_L_Q >----------------------*/,{
1730 /*
1731 * We donnot have a task that matches the tag.
1732 * Signal problem to C code for logging the event.
1733 * Send a M_ABORTTAG message.
1734 */
1735 SCR_INT,
1736 SIR_RESEL_BAD_I_T_L_Q,
1737 SCR_JUMP,
1738 PADDR_B (abort_resel),
1739 }/*-------------------------< BAD_STATUS >-----------------------*/,{
1740 /*
1741 * Anything different from INTERMEDIATE
1742 * CONDITION MET should be a bad SCSI status,
1743 * given that GOOD status has already been tested.
1744 * Call the C code.
1745 */
1746 SCR_COPY (4),
1747 PADDR_B (startpos),
1748 RADDR_1 (scratcha),
1749 SCR_INT ^ IFFALSE (DATA (S_COND_MET)),
1750 SIR_BAD_SCSI_STATUS,
1751 SCR_RETURN,
1752 0,
1753 }/*-------------------------< WSR_MA_HELPER >--------------------*/,{
1754 /*
1755 * Helper for the C code when WSR bit is set.
1756 * Perform the move of the residual byte.
1757 */
1758 SCR_CHMOV_TBL ^ SCR_DATA_IN,
1759 offsetof (struct sym_ccb, phys.wresid),
1760 SCR_JUMP,
1761 PADDR_A (dispatch),
1762
1763 #ifdef SYM_OPT_HANDLE_DIR_UNKNOWN
1764 }/*-------------------------< DATA_IO >--------------------------*/,{
1765 /*
1766 * We jump here if the data direction was unknown at the
1767 * time we had to queue the command to the scripts processor.
1768 * Pointers had been set as follow in this situation:
1769 * savep --> DATA_IO
1770 * lastp --> start pointer when DATA_IN
1771 * wlastp --> start pointer when DATA_OUT
1772 * This script sets savep and lastp according to the
1773 * direction chosen by the target.
1774 */
1775 SCR_JUMP ^ IFTRUE (WHEN (SCR_DATA_OUT)),
1776 PADDR_B (data_io_out),
1777 }/*-------------------------< DATA_IO_COM >----------------------*/,{
1778 /*
1779 * Direction is DATA IN.
1780 */
1781 SCR_COPY (4),
1782 HADDR_1 (ccb_head.lastp),
1783 HADDR_1 (ccb_head.savep),
1784 /*
1785 * Jump to the SCRIPTS according to actual direction.
1786 */
1787 SCR_COPY (4),
1788 HADDR_1 (ccb_head.savep),
1789 RADDR_1 (temp),
1790 SCR_RETURN,
1791 0,
1792 }/*-------------------------< DATA_IO_OUT >----------------------*/,{
1793 /*
1794 * Direction is DATA OUT.
1795 */
1796 SCR_REG_REG (HF_REG, SCR_AND, (~HF_DATA_IN)),
1797 0,
1798 SCR_COPY (4),
1799 HADDR_1 (ccb_head.wlastp),
1800 HADDR_1 (ccb_head.lastp),
1801 SCR_JUMP,
1802 PADDR_B(data_io_com),
1803 #endif /* SYM_OPT_HANDLE_DIR_UNKNOWN */
1804
1805 }/*-------------------------< ZERO >-----------------------------*/,{
1806 SCR_DATA_ZERO,
1807 }/*-------------------------< SCRATCH >--------------------------*/,{
1808 SCR_DATA_ZERO, /* MUST BE BEFORE SCRATCH1 */
1809 }/*-------------------------< SCRATCH1 >-------------------------*/,{
1810 SCR_DATA_ZERO,
1811 }/*-------------------------< PREV_DONE >------------------------*/,{
1812 SCR_DATA_ZERO, /* MUST BE BEFORE DONE_POS ! */
1813 }/*-------------------------< DONE_POS >-------------------------*/,{
1814 SCR_DATA_ZERO,
1815 }/*-------------------------< NEXTJOB >--------------------------*/,{
1816 SCR_DATA_ZERO, /* MUST BE BEFORE STARTPOS ! */
1817 }/*-------------------------< STARTPOS >-------------------------*/,{
1818 SCR_DATA_ZERO,
1819 }/*-------------------------< TARGTBL >--------------------------*/,{
1820 SCR_DATA_ZERO,
1821 }/*--------------------------<>----------------------------------*/
1822 };
1823
1824 static struct SYM_FWZ_SCR SYM_FWZ_SCR = {
1825 /*-------------------------< SNOOPTEST >------------------------*/{
1826 /*
1827 * Read the variable.
1828 */
1829 SCR_COPY (4),
1830 HADDR_1 (scratch),
1831 RADDR_1 (scratcha),
1832 /*
1833 * Write the variable.
1834 */
1835 SCR_COPY (4),
1836 RADDR_1 (temp),
1837 HADDR_1 (scratch),
1838 /*
1839 * Read back the variable.
1840 */
1841 SCR_COPY (4),
1842 HADDR_1 (scratch),
1843 RADDR_1 (temp),
1844 }/*-------------------------< SNOOPEND >-------------------------*/,{
1845 /*
1846 * And stop.
1847 */
1848 SCR_INT,
1849 99,
1850 }/*--------------------------<>----------------------------------*/
1851 };
MOXA 2.6.9 from sdlinux-moxaart.tgz