2 * sata_sx4.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
10 * The contents of this file are subject to the Open
11 * Software License version 1.1 that can be found at
12 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
15 * Alternatively, the contents of this file may be used under the terms
16 * of the GNU General Public License version 2 (the "GPL") as distributed
17 * in the kernel source COPYING file, in which case the provisions of
18 * the GPL are applicable instead of the above. If you wish to allow
19 * the use of your version of this file only under the terms of the
20 * GPL and not to allow others to use your version of this file under
21 * the OSL, indicate your decision by deleting the provisions above and
22 * replace them with the notice and other provisions required by the GPL.
23 * If you do not delete the provisions above, a recipient may use your
24 * version of this file under either the OSL or the GPL.
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/pci.h>
31 #include <linux/init.h>
32 #include <linux/blkdev.h>
33 #include <linux/delay.h>
34 #include <linux/interrupt.h>
35 #include <linux/sched.h>
37 #include <scsi/scsi_host.h>
38 #include <linux/libata.h>
40 #include "sata_promise.h"
42 #define DRV_NAME "sata_sx4"
43 #define DRV_VERSION "0.50"
47 PDC_PRD_TBL
= 0x44, /* Direct command DMA table addr */
49 PDC_PKT_SUBMIT
= 0x40, /* Command packet pointer addr */
50 PDC_HDMA_PKT_SUBMIT
= 0x100, /* Host DMA packet pointer addr */
51 PDC_INT_SEQMASK
= 0x40, /* Mask of asserted SEQ INTs */
52 PDC_HDMA_CTLSTAT
= 0x12C, /* Host DMA control / status */
54 PDC_20621_SEQCTL
= 0x400,
55 PDC_20621_SEQMASK
= 0x480,
56 PDC_20621_GENERAL_CTL
= 0x484,
57 PDC_20621_PAGE_SIZE
= (32 * 1024),
59 /* chosen, not constant, values; we design our own DIMM mem map */
60 PDC_20621_DIMM_WINDOW
= 0x0C, /* page# for 32K DIMM window */
61 PDC_20621_DIMM_BASE
= 0x00200000,
62 PDC_20621_DIMM_DATA
= (64 * 1024),
63 PDC_DIMM_DATA_STEP
= (256 * 1024),
64 PDC_DIMM_WINDOW_STEP
= (8 * 1024),
65 PDC_DIMM_HOST_PRD
= (6 * 1024),
66 PDC_DIMM_HOST_PKT
= (128 * 0),
67 PDC_DIMM_HPKT_PRD
= (128 * 1),
68 PDC_DIMM_ATA_PKT
= (128 * 2),
69 PDC_DIMM_APKT_PRD
= (128 * 3),
70 PDC_DIMM_HEADER_SZ
= PDC_DIMM_APKT_PRD
+ 128,
71 PDC_PAGE_WINDOW
= 0x40,
72 PDC_PAGE_DATA
= PDC_PAGE_WINDOW
+
73 (PDC_20621_DIMM_DATA
/ PDC_20621_PAGE_SIZE
),
74 PDC_PAGE_SET
= PDC_DIMM_DATA_STEP
/ PDC_20621_PAGE_SIZE
,
76 PDC_CHIP0_OFS
= 0xC0000, /* offset of chip #0 */
78 PDC_20621_ERR_MASK
= (1<<19) | (1<<20) | (1<<21) | (1<<22) |
81 board_20621
= 0, /* FastTrak S150 SX4 */
83 PDC_RESET
= (1 << 11), /* HDMA reset */
86 PDC_HDMA_Q_MASK
= (PDC_MAX_HDMA
- 1),
88 PDC_DIMM0_SPD_DEV_ADDRESS
= 0x50,
89 PDC_DIMM1_SPD_DEV_ADDRESS
= 0x51,
90 PDC_MAX_DIMM_MODULE
= 0x02,
91 PDC_I2C_CONTROL_OFFSET
= 0x48,
92 PDC_I2C_ADDR_DATA_OFFSET
= 0x4C,
93 PDC_DIMM0_CONTROL_OFFSET
= 0x80,
94 PDC_DIMM1_CONTROL_OFFSET
= 0x84,
95 PDC_SDRAM_CONTROL_OFFSET
= 0x88,
96 PDC_I2C_WRITE
= 0x00000000,
97 PDC_I2C_READ
= 0x00000040,
98 PDC_I2C_START
= 0x00000080,
99 PDC_I2C_MASK_INT
= 0x00000020,
100 PDC_I2C_COMPLETE
= 0x00010000,
101 PDC_I2C_NO_ACK
= 0x00100000,
102 PDC_DIMM_SPD_SUBADDRESS_START
= 0x00,
103 PDC_DIMM_SPD_SUBADDRESS_END
= 0x7F,
104 PDC_DIMM_SPD_ROW_NUM
= 3,
105 PDC_DIMM_SPD_COLUMN_NUM
= 4,
106 PDC_DIMM_SPD_MODULE_ROW
= 5,
107 PDC_DIMM_SPD_TYPE
= 11,
108 PDC_DIMM_SPD_FRESH_RATE
= 12,
109 PDC_DIMM_SPD_BANK_NUM
= 17,
110 PDC_DIMM_SPD_CAS_LATENCY
= 18,
111 PDC_DIMM_SPD_ATTRIBUTE
= 21,
112 PDC_DIMM_SPD_ROW_PRE_CHARGE
= 27,
113 PDC_DIMM_SPD_ROW_ACTIVE_DELAY
= 28,
114 PDC_DIMM_SPD_RAS_CAS_DELAY
= 29,
115 PDC_DIMM_SPD_ACTIVE_PRECHARGE
= 30,
116 PDC_DIMM_SPD_SYSTEM_FREQ
= 126,
117 PDC_CTL_STATUS
= 0x08,
118 PDC_DIMM_WINDOW_CTLR
= 0x0C,
119 PDC_TIME_CONTROL
= 0x3C,
120 PDC_TIME_PERIOD
= 0x40,
121 PDC_TIME_COUNTER
= 0x44,
122 PDC_GENERAL_CTLR
= 0x484,
123 PCI_PLL_INIT
= 0x8A531824,
124 PCI_X_TCOUNT
= 0xEE1E5CFF
128 struct pdc_port_priv
{
129 u8 dimm_buf
[(ATA_PRD_SZ
* ATA_MAX_PRD
) + 512];
134 struct pdc_host_priv
{
137 unsigned int doing_hdma
;
138 unsigned int hdma_prod
;
139 unsigned int hdma_cons
;
141 struct ata_queued_cmd
*qc
;
143 unsigned long pkt_ofs
;
148 static int pdc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
);
149 static irqreturn_t
pdc20621_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
);
150 static void pdc_eng_timeout(struct ata_port
*ap
);
151 static void pdc_20621_phy_reset (struct ata_port
*ap
);
152 static int pdc_port_start(struct ata_port
*ap
);
153 static void pdc_port_stop(struct ata_port
*ap
);
154 static void pdc20621_qc_prep(struct ata_queued_cmd
*qc
);
155 static void pdc_tf_load_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
);
156 static void pdc_exec_command_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
);
157 static void pdc20621_host_stop(struct ata_host_set
*host_set
);
158 static unsigned int pdc20621_dimm_init(struct ata_probe_ent
*pe
);
159 static int pdc20621_detect_dimm(struct ata_probe_ent
*pe
);
160 static unsigned int pdc20621_i2c_read(struct ata_probe_ent
*pe
,
161 u32 device
, u32 subaddr
, u32
*pdata
);
162 static int pdc20621_prog_dimm0(struct ata_probe_ent
*pe
);
163 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent
*pe
);
164 #ifdef ATA_VERBOSE_DEBUG
165 static void pdc20621_get_from_dimm(struct ata_probe_ent
*pe
,
166 void *psource
, u32 offset
, u32 size
);
168 static void pdc20621_put_to_dimm(struct ata_probe_ent
*pe
,
169 void *psource
, u32 offset
, u32 size
);
170 static void pdc20621_irq_clear(struct ata_port
*ap
);
171 static int pdc20621_qc_issue_prot(struct ata_queued_cmd
*qc
);
174 static Scsi_Host_Template pdc_sata_sht
= {
175 .module
= THIS_MODULE
,
177 .ioctl
= ata_scsi_ioctl
,
178 .queuecommand
= ata_scsi_queuecmd
,
179 .eh_strategy_handler
= ata_scsi_error
,
180 .can_queue
= ATA_DEF_QUEUE
,
181 .this_id
= ATA_SHT_THIS_ID
,
182 .sg_tablesize
= LIBATA_MAX_PRD
,
183 .max_sectors
= ATA_MAX_SECTORS
,
184 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
185 .emulated
= ATA_SHT_EMULATED
,
186 .use_clustering
= ATA_SHT_USE_CLUSTERING
,
187 .proc_name
= DRV_NAME
,
188 .dma_boundary
= ATA_DMA_BOUNDARY
,
189 .slave_configure
= ata_scsi_slave_config
,
190 .bios_param
= ata_std_bios_param
,
193 static struct ata_port_operations pdc_20621_ops
= {
194 .port_disable
= ata_port_disable
,
195 .tf_load
= pdc_tf_load_mmio
,
196 .tf_read
= ata_tf_read
,
197 .check_status
= ata_check_status
,
198 .exec_command
= pdc_exec_command_mmio
,
199 .dev_select
= ata_std_dev_select
,
200 .phy_reset
= pdc_20621_phy_reset
,
201 .qc_prep
= pdc20621_qc_prep
,
202 .qc_issue
= pdc20621_qc_issue_prot
,
203 .eng_timeout
= pdc_eng_timeout
,
204 .irq_handler
= pdc20621_interrupt
,
205 .irq_clear
= pdc20621_irq_clear
,
206 .port_start
= pdc_port_start
,
207 .port_stop
= pdc_port_stop
,
208 .host_stop
= pdc20621_host_stop
,
211 static struct ata_port_info pdc_port_info
[] = {
214 .sht
= &pdc_sata_sht
,
215 .host_flags
= ATA_FLAG_SATA
| ATA_FLAG_NO_LEGACY
|
216 ATA_FLAG_SRST
| ATA_FLAG_MMIO
,
217 .pio_mask
= 0x1f, /* pio0-4 */
218 .mwdma_mask
= 0x07, /* mwdma0-2 */
219 .udma_mask
= 0x7f, /* udma0-6 ; FIXME */
220 .port_ops
= &pdc_20621_ops
,
225 static struct pci_device_id pdc_sata_pci_tbl
[] = {
226 { PCI_VENDOR_ID_PROMISE
, 0x6622, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
228 { } /* terminate list */
232 static struct pci_driver pdc_sata_pci_driver
= {
234 .id_table
= pdc_sata_pci_tbl
,
235 .probe
= pdc_sata_init_one
,
236 .remove
= ata_pci_remove_one
,
240 static void pdc20621_host_stop(struct ata_host_set
*host_set
)
242 struct pdc_host_priv
*hpriv
= host_set
->private_data
;
243 void *dimm_mmio
= hpriv
->dimm_mmio
;
249 static int pdc_port_start(struct ata_port
*ap
)
251 struct pci_dev
*pdev
= ap
->host_set
->pdev
;
252 struct pdc_port_priv
*pp
;
255 rc
= ata_port_start(ap
);
259 pp
= kmalloc(sizeof(*pp
), GFP_KERNEL
);
264 memset(pp
, 0, sizeof(*pp
));
266 pp
->pkt
= pci_alloc_consistent(pdev
, 128, &pp
->pkt_dma
);
272 ap
->private_data
= pp
;
284 static void pdc_port_stop(struct ata_port
*ap
)
286 struct pci_dev
*pdev
= ap
->host_set
->pdev
;
287 struct pdc_port_priv
*pp
= ap
->private_data
;
289 ap
->private_data
= NULL
;
290 pci_free_consistent(pdev
, 128, pp
->pkt
, pp
->pkt_dma
);
296 static void pdc_20621_phy_reset (struct ata_port
*ap
)
299 ap
->cbl
= ATA_CBL_SATA
;
304 static inline void pdc20621_ata_sg(struct ata_taskfile
*tf
, u8
*buf
,
306 unsigned int total_len
)
309 unsigned int dw
= PDC_DIMM_APKT_PRD
>> 2;
310 u32
*buf32
= (u32
*) buf
;
312 /* output ATA packet S/G table */
313 addr
= PDC_20621_DIMM_BASE
+ PDC_20621_DIMM_DATA
+
314 (PDC_DIMM_DATA_STEP
* portno
);
315 VPRINTK("ATA sg addr 0x%x, %d\n", addr
, addr
);
316 buf32
[dw
] = cpu_to_le32(addr
);
317 buf32
[dw
+ 1] = cpu_to_le32(total_len
| ATA_PRD_EOT
);
319 VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
320 PDC_20621_DIMM_BASE
+
321 (PDC_DIMM_WINDOW_STEP
* portno
) +
323 buf32
[dw
], buf32
[dw
+ 1]);
326 static inline void pdc20621_host_sg(struct ata_taskfile
*tf
, u8
*buf
,
328 unsigned int total_len
)
331 unsigned int dw
= PDC_DIMM_HPKT_PRD
>> 2;
332 u32
*buf32
= (u32
*) buf
;
334 /* output Host DMA packet S/G table */
335 addr
= PDC_20621_DIMM_BASE
+ PDC_20621_DIMM_DATA
+
336 (PDC_DIMM_DATA_STEP
* portno
);
338 buf32
[dw
] = cpu_to_le32(addr
);
339 buf32
[dw
+ 1] = cpu_to_le32(total_len
| ATA_PRD_EOT
);
341 VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
342 PDC_20621_DIMM_BASE
+
343 (PDC_DIMM_WINDOW_STEP
* portno
) +
345 buf32
[dw
], buf32
[dw
+ 1]);
348 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile
*tf
,
349 unsigned int devno
, u8
*buf
,
353 u32
*buf32
= (u32
*) buf
;
356 unsigned int dimm_sg
= PDC_20621_DIMM_BASE
+
357 (PDC_DIMM_WINDOW_STEP
* portno
) +
359 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg
, dimm_sg
);
361 i
= PDC_DIMM_ATA_PKT
;
366 if ((tf
->protocol
== ATA_PROT_DMA
) && (!(tf
->flags
& ATA_TFLAG_WRITE
)))
367 buf
[i
++] = PDC_PKT_READ
;
368 else if (tf
->protocol
== ATA_PROT_NODATA
)
369 buf
[i
++] = PDC_PKT_NODATA
;
372 buf
[i
++] = 0; /* reserved */
373 buf
[i
++] = portno
+ 1; /* seq. id */
374 buf
[i
++] = 0xff; /* delay seq. id */
376 /* dimm dma S/G, and next-pkt */
378 if (tf
->protocol
== ATA_PROT_NODATA
)
381 buf32
[dw
] = cpu_to_le32(dimm_sg
);
386 dev_reg
= ATA_DEVICE_OBS
;
388 dev_reg
= ATA_DEVICE_OBS
| ATA_DEV1
;
391 buf
[i
++] = (1 << 5) | PDC_PKT_CLEAR_BSY
| ATA_REG_DEVICE
;
394 /* device control register */
395 buf
[i
++] = (1 << 5) | PDC_REG_DEVCTL
;
401 static inline void pdc20621_host_pkt(struct ata_taskfile
*tf
, u8
*buf
,
405 u32 tmp
, *buf32
= (u32
*) buf
;
407 unsigned int host_sg
= PDC_20621_DIMM_BASE
+
408 (PDC_DIMM_WINDOW_STEP
* portno
) +
410 unsigned int dimm_sg
= PDC_20621_DIMM_BASE
+
411 (PDC_DIMM_WINDOW_STEP
* portno
) +
413 VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg
, dimm_sg
);
414 VPRINTK("host_sg == 0x%x, %d\n", host_sg
, host_sg
);
416 dw
= PDC_DIMM_HOST_PKT
>> 2;
419 * Set up Host DMA packet
421 if ((tf
->protocol
== ATA_PROT_DMA
) && (!(tf
->flags
& ATA_TFLAG_WRITE
)))
425 tmp
|= ((portno
+ 1 + 4) << 16); /* seq. id */
426 tmp
|= (0xff << 24); /* delay seq. id */
427 buf32
[dw
+ 0] = cpu_to_le32(tmp
);
428 buf32
[dw
+ 1] = cpu_to_le32(host_sg
);
429 buf32
[dw
+ 2] = cpu_to_le32(dimm_sg
);
432 VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
433 PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* portno
) +
441 static void pdc20621_dma_prep(struct ata_queued_cmd
*qc
)
443 struct scatterlist
*sg
= qc
->sg
;
444 struct ata_port
*ap
= qc
->ap
;
445 struct pdc_port_priv
*pp
= ap
->private_data
;
446 void *mmio
= ap
->host_set
->mmio_base
;
447 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
448 void *dimm_mmio
= hpriv
->dimm_mmio
;
449 unsigned int portno
= ap
->port_no
;
450 unsigned int i
, last
, idx
, total_len
= 0, sgt_len
;
451 u32
*buf
= (u32
*) &pp
->dimm_buf
[PDC_DIMM_HEADER_SZ
];
453 assert(qc
->flags
& ATA_QCFLAG_DMAMAP
);
455 VPRINTK("ata%u: ENTER\n", ap
->id
);
457 /* hard-code chip #0 */
458 mmio
+= PDC_CHIP0_OFS
;
465 for (i
= 0; i
< last
; i
++) {
466 buf
[idx
++] = cpu_to_le32(sg_dma_address(&sg
[i
]));
467 buf
[idx
++] = cpu_to_le32(sg_dma_len(&sg
[i
]));
468 total_len
+= sg
[i
].length
;
470 buf
[idx
- 1] |= cpu_to_le32(ATA_PRD_EOT
);
474 * Build ATA, host DMA packets
476 pdc20621_host_sg(&qc
->tf
, &pp
->dimm_buf
[0], portno
, total_len
);
477 pdc20621_host_pkt(&qc
->tf
, &pp
->dimm_buf
[0], portno
);
479 pdc20621_ata_sg(&qc
->tf
, &pp
->dimm_buf
[0], portno
, total_len
);
480 i
= pdc20621_ata_pkt(&qc
->tf
, qc
->dev
->devno
, &pp
->dimm_buf
[0], portno
);
482 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
483 i
= pdc_prep_lba48(&qc
->tf
, &pp
->dimm_buf
[0], i
);
485 i
= pdc_prep_lba28(&qc
->tf
, &pp
->dimm_buf
[0], i
);
487 pdc_pkt_footer(&qc
->tf
, &pp
->dimm_buf
[0], i
);
489 /* copy three S/G tables and two packets to DIMM MMIO window */
490 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
),
491 &pp
->dimm_buf
, PDC_DIMM_HEADER_SZ
);
492 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
) +
494 &pp
->dimm_buf
[PDC_DIMM_HEADER_SZ
], sgt_len
);
496 /* force host FIFO dump */
497 writel(0x00000001, mmio
+ PDC_20621_GENERAL_CTL
);
499 readl(dimm_mmio
); /* MMIO PCI posting flush */
501 VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i
, sgt_len
);
504 static void pdc20621_nodata_prep(struct ata_queued_cmd
*qc
)
506 struct ata_port
*ap
= qc
->ap
;
507 struct pdc_port_priv
*pp
= ap
->private_data
;
508 void *mmio
= ap
->host_set
->mmio_base
;
509 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
510 void *dimm_mmio
= hpriv
->dimm_mmio
;
511 unsigned int portno
= ap
->port_no
;
514 VPRINTK("ata%u: ENTER\n", ap
->id
);
516 /* hard-code chip #0 */
517 mmio
+= PDC_CHIP0_OFS
;
519 i
= pdc20621_ata_pkt(&qc
->tf
, qc
->dev
->devno
, &pp
->dimm_buf
[0], portno
);
521 if (qc
->tf
.flags
& ATA_TFLAG_LBA48
)
522 i
= pdc_prep_lba48(&qc
->tf
, &pp
->dimm_buf
[0], i
);
524 i
= pdc_prep_lba28(&qc
->tf
, &pp
->dimm_buf
[0], i
);
526 pdc_pkt_footer(&qc
->tf
, &pp
->dimm_buf
[0], i
);
528 /* copy three S/G tables and two packets to DIMM MMIO window */
529 memcpy_toio(dimm_mmio
+ (portno
* PDC_DIMM_WINDOW_STEP
),
530 &pp
->dimm_buf
, PDC_DIMM_HEADER_SZ
);
532 /* force host FIFO dump */
533 writel(0x00000001, mmio
+ PDC_20621_GENERAL_CTL
);
535 readl(dimm_mmio
); /* MMIO PCI posting flush */
537 VPRINTK("ata pkt buf ofs %u, mmio copied\n", i
);
540 static void pdc20621_qc_prep(struct ata_queued_cmd
*qc
)
542 switch (qc
->tf
.protocol
) {
544 pdc20621_dma_prep(qc
);
546 case ATA_PROT_NODATA
:
547 pdc20621_nodata_prep(qc
);
554 static void __pdc20621_push_hdma(struct ata_queued_cmd
*qc
,
558 struct ata_port
*ap
= qc
->ap
;
559 struct ata_host_set
*host_set
= ap
->host_set
;
560 void *mmio
= host_set
->mmio_base
;
562 /* hard-code chip #0 */
563 mmio
+= PDC_CHIP0_OFS
;
565 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
566 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4)); /* flush */
568 writel(pkt_ofs
, mmio
+ PDC_HDMA_PKT_SUBMIT
);
569 readl(mmio
+ PDC_HDMA_PKT_SUBMIT
); /* flush */
572 static void pdc20621_push_hdma(struct ata_queued_cmd
*qc
,
576 struct ata_port
*ap
= qc
->ap
;
577 struct pdc_host_priv
*pp
= ap
->host_set
->private_data
;
578 unsigned int idx
= pp
->hdma_prod
& PDC_HDMA_Q_MASK
;
580 if (!pp
->doing_hdma
) {
581 __pdc20621_push_hdma(qc
, seq
, pkt_ofs
);
586 pp
->hdma
[idx
].qc
= qc
;
587 pp
->hdma
[idx
].seq
= seq
;
588 pp
->hdma
[idx
].pkt_ofs
= pkt_ofs
;
592 static void pdc20621_pop_hdma(struct ata_queued_cmd
*qc
)
594 struct ata_port
*ap
= qc
->ap
;
595 struct pdc_host_priv
*pp
= ap
->host_set
->private_data
;
596 unsigned int idx
= pp
->hdma_cons
& PDC_HDMA_Q_MASK
;
598 /* if nothing on queue, we're done */
599 if (pp
->hdma_prod
== pp
->hdma_cons
) {
604 __pdc20621_push_hdma(pp
->hdma
[idx
].qc
, pp
->hdma
[idx
].seq
,
605 pp
->hdma
[idx
].pkt_ofs
);
609 #ifdef ATA_VERBOSE_DEBUG
610 static void pdc20621_dump_hdma(struct ata_queued_cmd
*qc
)
612 struct ata_port
*ap
= qc
->ap
;
613 unsigned int port_no
= ap
->port_no
;
614 struct pdc_host_priv
*hpriv
= ap
->host_set
->private_data
;
615 void *dimm_mmio
= hpriv
->dimm_mmio
;
617 dimm_mmio
+= (port_no
* PDC_DIMM_WINDOW_STEP
);
618 dimm_mmio
+= PDC_DIMM_HOST_PKT
;
620 printk(KERN_ERR
"HDMA[0] == 0x%08X\n", readl(dimm_mmio
));
621 printk(KERN_ERR
"HDMA[1] == 0x%08X\n", readl(dimm_mmio
+ 4));
622 printk(KERN_ERR
"HDMA[2] == 0x%08X\n", readl(dimm_mmio
+ 8));
623 printk(KERN_ERR
"HDMA[3] == 0x%08X\n", readl(dimm_mmio
+ 12));
626 static inline void pdc20621_dump_hdma(struct ata_queued_cmd
*qc
) { }
627 #endif /* ATA_VERBOSE_DEBUG */
629 static void pdc20621_packet_start(struct ata_queued_cmd
*qc
)
631 struct ata_port
*ap
= qc
->ap
;
632 struct ata_host_set
*host_set
= ap
->host_set
;
633 unsigned int port_no
= ap
->port_no
;
634 void *mmio
= host_set
->mmio_base
;
635 unsigned int rw
= (qc
->tf
.flags
& ATA_TFLAG_WRITE
);
636 u8 seq
= (u8
) (port_no
+ 1);
637 unsigned int port_ofs
;
639 /* hard-code chip #0 */
640 mmio
+= PDC_CHIP0_OFS
;
642 VPRINTK("ata%u: ENTER\n", ap
->id
);
644 wmb(); /* flush PRD, pkt writes */
646 port_ofs
= PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* port_no
);
648 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
649 if (rw
&& qc
->tf
.protocol
== ATA_PROT_DMA
) {
652 pdc20621_dump_hdma(qc
);
653 pdc20621_push_hdma(qc
, seq
, port_ofs
+ PDC_DIMM_HOST_PKT
);
654 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
655 port_ofs
+ PDC_DIMM_HOST_PKT
,
656 port_ofs
+ PDC_DIMM_HOST_PKT
,
659 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
660 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4)); /* flush */
662 writel(port_ofs
+ PDC_DIMM_ATA_PKT
,
663 (void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
664 readl((void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
665 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
666 port_ofs
+ PDC_DIMM_ATA_PKT
,
667 port_ofs
+ PDC_DIMM_ATA_PKT
,
672 static int pdc20621_qc_issue_prot(struct ata_queued_cmd
*qc
)
674 switch (qc
->tf
.protocol
) {
676 case ATA_PROT_NODATA
:
677 pdc20621_packet_start(qc
);
680 case ATA_PROT_ATAPI_DMA
:
688 return ata_qc_issue_prot(qc
);
691 static inline unsigned int pdc20621_host_intr( struct ata_port
*ap
,
692 struct ata_queued_cmd
*qc
,
693 unsigned int doing_hdma
,
696 unsigned int port_no
= ap
->port_no
;
697 unsigned int port_ofs
=
698 PDC_20621_DIMM_BASE
+ (PDC_DIMM_WINDOW_STEP
* port_no
);
700 unsigned int handled
= 0;
704 if ((qc
->tf
.protocol
== ATA_PROT_DMA
) && /* read */
705 (!(qc
->tf
.flags
& ATA_TFLAG_WRITE
))) {
707 /* step two - DMA from DIMM to host */
709 VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap
->id
,
710 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
711 /* get drive status; clear intr; complete txn */
712 ata_qc_complete(qc
, ata_wait_idle(ap
));
713 pdc20621_pop_hdma(qc
);
716 /* step one - exec ATA command */
718 u8 seq
= (u8
) (port_no
+ 1 + 4);
719 VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap
->id
,
720 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
722 /* submit hdma pkt */
723 pdc20621_dump_hdma(qc
);
724 pdc20621_push_hdma(qc
, seq
,
725 port_ofs
+ PDC_DIMM_HOST_PKT
);
729 } else if (qc
->tf
.protocol
== ATA_PROT_DMA
) { /* write */
731 /* step one - DMA from host to DIMM */
733 u8 seq
= (u8
) (port_no
+ 1);
734 VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap
->id
,
735 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
738 writel(0x00000001, mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
739 readl(mmio
+ PDC_20621_SEQCTL
+ (seq
* 4));
740 writel(port_ofs
+ PDC_DIMM_ATA_PKT
,
741 (void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
742 readl((void *) ap
->ioaddr
.cmd_addr
+ PDC_PKT_SUBMIT
);
745 /* step two - execute ATA command */
747 VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap
->id
,
748 readl(mmio
+ 0x104), readl(mmio
+ PDC_HDMA_CTLSTAT
));
749 /* get drive status; clear intr; complete txn */
750 ata_qc_complete(qc
, ata_wait_idle(ap
));
751 pdc20621_pop_hdma(qc
);
755 /* command completion, but no data xfer */
756 } else if (qc
->tf
.protocol
== ATA_PROT_NODATA
) {
758 status
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
759 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status
);
760 ata_qc_complete(qc
, status
);
764 ap
->stats
.idle_irq
++;
770 static void pdc20621_irq_clear(struct ata_port
*ap
)
772 struct ata_host_set
*host_set
= ap
->host_set
;
773 void *mmio
= host_set
->mmio_base
;
775 mmio
+= PDC_CHIP0_OFS
;
777 readl(mmio
+ PDC_20621_SEQMASK
);
780 static irqreturn_t
pdc20621_interrupt (int irq
, void *dev_instance
, struct pt_regs
*regs
)
782 struct ata_host_set
*host_set
= dev_instance
;
785 unsigned int i
, tmp
, port_no
;
786 unsigned int handled
= 0;
791 if (!host_set
|| !host_set
->mmio_base
) {
792 VPRINTK("QUICK EXIT\n");
796 mmio_base
= host_set
->mmio_base
;
798 /* reading should also clear interrupts */
799 mmio_base
+= PDC_CHIP0_OFS
;
800 mask
= readl(mmio_base
+ PDC_20621_SEQMASK
);
801 VPRINTK("mask == 0x%x\n", mask
);
803 if (mask
== 0xffffffff) {
804 VPRINTK("QUICK EXIT 2\n");
807 mask
&= 0xffff; /* only 16 tags possible */
809 VPRINTK("QUICK EXIT 3\n");
813 spin_lock(&host_set
->lock
);
815 for (i
= 1; i
< 9; i
++) {
819 if (port_no
>= host_set
->n_ports
)
822 ap
= host_set
->ports
[port_no
];
823 tmp
= mask
& (1 << i
);
824 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i
, port_no
, ap
, tmp
);
825 if (tmp
&& ap
&& (!(ap
->flags
& ATA_FLAG_PORT_DISABLED
))) {
826 struct ata_queued_cmd
*qc
;
828 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
829 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
)))
830 handled
+= pdc20621_host_intr(ap
, qc
, (i
> 4),
835 spin_unlock(&host_set
->lock
);
837 VPRINTK("mask == 0x%x\n", mask
);
841 return IRQ_RETVAL(handled
);
844 static void pdc_eng_timeout(struct ata_port
*ap
)
847 struct ata_queued_cmd
*qc
;
851 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
853 printk(KERN_ERR
"ata%u: BUG: timeout without command\n",
858 /* hack alert! We cannot use the supplied completion
859 * function from inside the ->eh_strategy_handler() thread.
860 * libata is the only user of ->eh_strategy_handler() in
861 * any kernel, so the default scsi_done() assumes it is
862 * not being called from the SCSI EH.
864 qc
->scsidone
= scsi_finish_command
;
866 switch (qc
->tf
.protocol
) {
868 case ATA_PROT_NODATA
:
869 printk(KERN_ERR
"ata%u: command timeout\n", ap
->id
);
870 ata_qc_complete(qc
, ata_wait_idle(ap
) | ATA_ERR
);
874 drv_stat
= ata_busy_wait(ap
, ATA_BUSY
| ATA_DRQ
, 1000);
876 printk(KERN_ERR
"ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
877 ap
->id
, qc
->tf
.command
, drv_stat
);
879 ata_qc_complete(qc
, drv_stat
);
887 static void pdc_tf_load_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
)
889 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
890 tf
->protocol
== ATA_PROT_NODATA
);
895 static void pdc_exec_command_mmio(struct ata_port
*ap
, struct ata_taskfile
*tf
)
897 WARN_ON (tf
->protocol
== ATA_PROT_DMA
||
898 tf
->protocol
== ATA_PROT_NODATA
);
899 ata_exec_command(ap
, tf
);
903 static void pdc_sata_setup_port(struct ata_ioports
*port
, unsigned long base
)
905 port
->cmd_addr
= base
;
906 port
->data_addr
= base
;
908 port
->error_addr
= base
+ 0x4;
909 port
->nsect_addr
= base
+ 0x8;
910 port
->lbal_addr
= base
+ 0xc;
911 port
->lbam_addr
= base
+ 0x10;
912 port
->lbah_addr
= base
+ 0x14;
913 port
->device_addr
= base
+ 0x18;
915 port
->status_addr
= base
+ 0x1c;
916 port
->altstatus_addr
=
917 port
->ctl_addr
= base
+ 0x38;
921 #ifdef ATA_VERBOSE_DEBUG
922 static void pdc20621_get_from_dimm(struct ata_probe_ent
*pe
, void *psource
,
923 u32 offset
, u32 size
)
929 void *mmio
= pe
->mmio_base
;
930 struct pdc_host_priv
*hpriv
= pe
->private_data
;
931 void *dimm_mmio
= hpriv
->dimm_mmio
;
933 /* hard-code chip #0 */
934 mmio
+= PDC_CHIP0_OFS
;
937 window_size
= 0x2000 * 4; /* 32K byte uchar size */
938 idx
= (u16
) (offset
/ window_size
);
940 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
941 readl(mmio
+ PDC_GENERAL_CTLR
);
942 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
943 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
945 offset
-= (idx
* window_size
);
947 dist
= ((long) (window_size
- (offset
+ size
))) >= 0 ? size
:
948 (long) (window_size
- offset
);
949 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
+ offset
/ 4),
954 for (; (long) size
>= (long) window_size
;) {
955 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
956 readl(mmio
+ PDC_GENERAL_CTLR
);
957 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
958 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
959 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
),
961 psource
+= window_size
;
967 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
968 readl(mmio
+ PDC_GENERAL_CTLR
);
969 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
970 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
971 memcpy_fromio((char *) psource
, (char *) (dimm_mmio
),
978 static void pdc20621_put_to_dimm(struct ata_probe_ent
*pe
, void *psource
,
979 u32 offset
, u32 size
)
985 void *mmio
= pe
->mmio_base
;
986 struct pdc_host_priv
*hpriv
= pe
->private_data
;
987 void *dimm_mmio
= hpriv
->dimm_mmio
;
989 /* hard-code chip #0 */
990 mmio
+= PDC_CHIP0_OFS
;
993 window_size
= 0x2000 * 4; /* 32K byte uchar size */
994 idx
= (u16
) (offset
/ window_size
);
996 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
997 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
998 offset
-= (idx
* window_size
);
1000 dist
= ((long)(s32
)(window_size
- (offset
+ size
))) >= 0 ? size
:
1001 (long) (window_size
- offset
);
1002 memcpy_toio((char *) (dimm_mmio
+ offset
/ 4), (char *) psource
, dist
);
1003 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1004 readl(mmio
+ PDC_GENERAL_CTLR
);
1008 for (; (long) size
>= (long) window_size
;) {
1009 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1010 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1011 memcpy_toio((char *) (dimm_mmio
), (char *) psource
,
1013 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1014 readl(mmio
+ PDC_GENERAL_CTLR
);
1015 psource
+= window_size
;
1016 size
-= window_size
;
1021 writel(((idx
) << page_mask
), mmio
+ PDC_DIMM_WINDOW_CTLR
);
1022 readl(mmio
+ PDC_DIMM_WINDOW_CTLR
);
1023 memcpy_toio((char *) (dimm_mmio
), (char *) psource
, size
/ 4);
1024 writel(0x01, mmio
+ PDC_GENERAL_CTLR
);
1025 readl(mmio
+ PDC_GENERAL_CTLR
);
1030 static unsigned int pdc20621_i2c_read(struct ata_probe_ent
*pe
, u32 device
,
1031 u32 subaddr
, u32
*pdata
)
1033 void *mmio
= pe
->mmio_base
;
1038 /* hard-code chip #0 */
1039 mmio
+= PDC_CHIP0_OFS
;
1041 i2creg
|= device
<< 24;
1042 i2creg
|= subaddr
<< 16;
1044 /* Set the device and subaddress */
1045 writel(i2creg
, mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1046 readl(mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1048 /* Write Control to perform read operation, mask int */
1049 writel(PDC_I2C_READ
| PDC_I2C_START
| PDC_I2C_MASK_INT
,
1050 mmio
+ PDC_I2C_CONTROL_OFFSET
);
1052 for (count
= 0; count
<= 1000; count
++) {
1053 status
= readl(mmio
+ PDC_I2C_CONTROL_OFFSET
);
1054 if (status
& PDC_I2C_COMPLETE
) {
1055 status
= readl(mmio
+ PDC_I2C_ADDR_DATA_OFFSET
);
1057 } else if (count
== 1000)
1061 *pdata
= (status
>> 8) & 0x000000ff;
1066 static int pdc20621_detect_dimm(struct ata_probe_ent
*pe
)
1069 if (pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1070 PDC_DIMM_SPD_SYSTEM_FREQ
, &data
)) {
1076 if (pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
, 9, &data
)) {
1086 static int pdc20621_prog_dimm0(struct ata_probe_ent
*pe
)
1092 void *mmio
= pe
->mmio_base
;
1093 static const struct {
1096 } pdc_i2c_read_data
[] = {
1097 { PDC_DIMM_SPD_TYPE
, 11 },
1098 { PDC_DIMM_SPD_FRESH_RATE
, 12 },
1099 { PDC_DIMM_SPD_COLUMN_NUM
, 4 },
1100 { PDC_DIMM_SPD_ATTRIBUTE
, 21 },
1101 { PDC_DIMM_SPD_ROW_NUM
, 3 },
1102 { PDC_DIMM_SPD_BANK_NUM
, 17 },
1103 { PDC_DIMM_SPD_MODULE_ROW
, 5 },
1104 { PDC_DIMM_SPD_ROW_PRE_CHARGE
, 27 },
1105 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY
, 28 },
1106 { PDC_DIMM_SPD_RAS_CAS_DELAY
, 29 },
1107 { PDC_DIMM_SPD_ACTIVE_PRECHARGE
, 30 },
1108 { PDC_DIMM_SPD_CAS_LATENCY
, 18 },
1111 /* hard-code chip #0 */
1112 mmio
+= PDC_CHIP0_OFS
;
1114 for(i
=0; i
<ARRAY_SIZE(pdc_i2c_read_data
); i
++)
1115 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1116 pdc_i2c_read_data
[i
].reg
,
1117 &spd0
[pdc_i2c_read_data
[i
].ofs
]);
1119 data
|= (spd0
[4] - 8) | ((spd0
[21] != 0) << 3) | ((spd0
[3]-11) << 4);
1120 data
|= ((spd0
[17] / 4) << 6) | ((spd0
[5] / 2) << 7) |
1121 ((((spd0
[27] + 9) / 10) - 1) << 8) ;
1122 data
|= (((((spd0
[29] > spd0
[28])
1123 ? spd0
[29] : spd0
[28]) + 9) / 10) - 1) << 10;
1124 data
|= ((spd0
[30] - spd0
[29] + 9) / 10 - 2) << 12;
1126 if (spd0
[18] & 0x08)
1127 data
|= ((0x03) << 14);
1128 else if (spd0
[18] & 0x04)
1129 data
|= ((0x02) << 14);
1130 else if (spd0
[18] & 0x01)
1131 data
|= ((0x01) << 14);
1136 Calculate the size of bDIMMSize (power of 2) and
1137 merge the DIMM size by program start/end address.
1140 bdimmsize
= spd0
[4] + (spd0
[5] / 2) + spd0
[3] + (spd0
[17] / 2) + 3;
1141 size
= (1 << bdimmsize
) >> 20; /* size = xxx(MB) */
1142 data
|= (((size
/ 16) - 1) << 16);
1145 writel(data
, mmio
+ PDC_DIMM0_CONTROL_OFFSET
);
1146 readl(mmio
+ PDC_DIMM0_CONTROL_OFFSET
);
1151 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent
*pe
)
1155 void *mmio
= pe
->mmio_base
;
1157 /* hard-code chip #0 */
1158 mmio
+= PDC_CHIP0_OFS
;
1161 Set To Default : DIMM Module Global Control Register (0x022259F1)
1162 DIMM Arbitration Disable (bit 20)
1163 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1164 Refresh Enable (bit 17)
1168 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1169 readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1171 /* Turn on for ECC */
1172 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1173 PDC_DIMM_SPD_TYPE
, &spd0
);
1175 data
|= (0x01 << 16);
1176 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1177 readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1178 printk(KERN_ERR
"Local DIMM ECC Enabled\n");
1181 /* DIMM Initialization Select/Enable (bit 18/19) */
1184 writel(data
, mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1187 for (i
= 1; i
<= 10; i
++) { /* polling ~5 secs */
1188 data
= readl(mmio
+ PDC_SDRAM_CONTROL_OFFSET
);
1189 if (!(data
& (1<<19))) {
1193 set_current_state(TASK_UNINTERRUPTIBLE
);
1194 schedule_timeout((i
* 100) * HZ
/ 1000 + 1);
1200 static unsigned int pdc20621_dimm_init(struct ata_probe_ent
*pe
)
1202 int speed
, size
, length
;
1203 u32 addr
,spd0
,pci_status
;
1210 void *mmio
= pe
->mmio_base
;
1212 /* hard-code chip #0 */
1213 mmio
+= PDC_CHIP0_OFS
;
1215 /* Initialize PLL based upon PCI Bus Frequency */
1217 /* Initialize Time Period Register */
1218 writel(0xffffffff, mmio
+ PDC_TIME_PERIOD
);
1219 time_period
= readl(mmio
+ PDC_TIME_PERIOD
);
1220 VPRINTK("Time Period Register (0x40): 0x%x\n", time_period
);
1223 writel(0x00001a0, mmio
+ PDC_TIME_CONTROL
);
1224 readl(mmio
+ PDC_TIME_CONTROL
);
1226 /* Wait 3 seconds */
1227 set_current_state(TASK_UNINTERRUPTIBLE
);
1228 schedule_timeout(3 * HZ
);
1231 When timer is enabled, counter is decreased every internal
1235 tcount
= readl(mmio
+ PDC_TIME_COUNTER
);
1236 VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount
);
1239 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1240 register should be >= (0xffffffff - 3x10^8).
1242 if(tcount
>= PCI_X_TCOUNT
) {
1243 ticks
= (time_period
- tcount
);
1244 VPRINTK("Num counters 0x%x (%d)\n", ticks
, ticks
);
1246 clock
= (ticks
/ 300000);
1247 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock
, clock
);
1249 clock
= (clock
* 33);
1250 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock
, clock
);
1252 /* PLL F Param (bit 22:16) */
1253 fparam
= (1400000 / clock
) - 2;
1254 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam
, fparam
);
1256 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1257 pci_status
= (0x8a001824 | (fparam
<< 16));
1259 pci_status
= PCI_PLL_INIT
;
1261 /* Initialize PLL. */
1262 VPRINTK("pci_status: 0x%x\n", pci_status
);
1263 writel(pci_status
, mmio
+ PDC_CTL_STATUS
);
1264 readl(mmio
+ PDC_CTL_STATUS
);
1267 Read SPD of DIMM by I2C interface,
1268 and program the DIMM Module Controller.
1270 if (!(speed
= pdc20621_detect_dimm(pe
))) {
1271 printk(KERN_ERR
"Detect Local DIMM Fail\n");
1272 return 1; /* DIMM error */
1274 VPRINTK("Local DIMM Speed = %d\n", speed
);
1276 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1277 size
= pdc20621_prog_dimm0(pe
);
1278 VPRINTK("Local DIMM Size = %dMB\n",size
);
1280 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1281 if (pdc20621_prog_dimm_global(pe
)) {
1282 printk(KERN_ERR
"Programming DIMM Module Global Control Register Fail\n");
1286 #ifdef ATA_VERBOSE_DEBUG
1288 u8 test_parttern1
[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1289 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1291 '9','8','0','3','1','6','1','2',0,0};
1292 u8 test_parttern2
[40] = {0};
1294 pdc20621_put_to_dimm(pe
, (void *) test_parttern2
, 0x10040, 40);
1295 pdc20621_put_to_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1297 pdc20621_put_to_dimm(pe
, (void *) test_parttern1
, 0x10040, 40);
1298 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1299 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1300 test_parttern2
[1], &(test_parttern2
[2]));
1301 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x10040,
1303 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1304 test_parttern2
[1], &(test_parttern2
[2]));
1306 pdc20621_put_to_dimm(pe
, (void *) test_parttern1
, 0x40, 40);
1307 pdc20621_get_from_dimm(pe
, (void *) test_parttern2
, 0x40, 40);
1308 printk(KERN_ERR
"%x, %x, %s\n", test_parttern2
[0],
1309 test_parttern2
[1], &(test_parttern2
[2]));
1313 /* ECC initiliazation. */
1315 pdc20621_i2c_read(pe
, PDC_DIMM0_SPD_DEV_ADDRESS
,
1316 PDC_DIMM_SPD_TYPE
, &spd0
);
1318 VPRINTK("Start ECC initialization\n");
1320 length
= size
* 1024 * 1024;
1321 while (addr
< length
) {
1322 pdc20621_put_to_dimm(pe
, (void *) &tmp
, addr
,
1324 addr
+= sizeof(u32
);
1326 VPRINTK("Finish ECC initialization\n");
1332 static void pdc_20621_init(struct ata_probe_ent
*pe
)
1335 void *mmio
= pe
->mmio_base
;
1337 /* hard-code chip #0 */
1338 mmio
+= PDC_CHIP0_OFS
;
1341 * Select page 0x40 for our 32k DIMM window
1343 tmp
= readl(mmio
+ PDC_20621_DIMM_WINDOW
) & 0xffff0000;
1344 tmp
|= PDC_PAGE_WINDOW
; /* page 40h; arbitrarily selected */
1345 writel(tmp
, mmio
+ PDC_20621_DIMM_WINDOW
);
1350 tmp
= readl(mmio
+ PDC_HDMA_CTLSTAT
);
1352 writel(tmp
, mmio
+ PDC_HDMA_CTLSTAT
);
1353 readl(mmio
+ PDC_HDMA_CTLSTAT
); /* flush */
1357 tmp
= readl(mmio
+ PDC_HDMA_CTLSTAT
);
1359 writel(tmp
, mmio
+ PDC_HDMA_CTLSTAT
);
1360 readl(mmio
+ PDC_HDMA_CTLSTAT
); /* flush */
1363 static int pdc_sata_init_one (struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1365 static int printed_version
;
1366 struct ata_probe_ent
*probe_ent
= NULL
;
1368 void *mmio_base
, *dimm_mmio
= NULL
;
1369 struct pdc_host_priv
*hpriv
= NULL
;
1370 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
1373 if (!printed_version
++)
1374 printk(KERN_DEBUG DRV_NAME
" version " DRV_VERSION
"\n");
1377 * If this driver happens to only be useful on Apple's K2, then
1378 * we should check that here as it has a normal Serverworks ID
1380 rc
= pci_enable_device(pdev
);
1384 rc
= pci_request_regions(pdev
, DRV_NAME
);
1388 rc
= pci_set_dma_mask(pdev
, ATA_DMA_MASK
);
1390 goto err_out_regions
;
1391 rc
= pci_set_consistent_dma_mask(pdev
, ATA_DMA_MASK
);
1393 goto err_out_regions
;
1395 probe_ent
= kmalloc(sizeof(*probe_ent
), GFP_KERNEL
);
1396 if (probe_ent
== NULL
) {
1398 goto err_out_regions
;
1401 memset(probe_ent
, 0, sizeof(*probe_ent
));
1402 probe_ent
->pdev
= pdev
;
1403 INIT_LIST_HEAD(&probe_ent
->node
);
1405 mmio_base
= ioremap(pci_resource_start(pdev
, 3),
1406 pci_resource_len(pdev
, 3));
1407 if (mmio_base
== NULL
) {
1409 goto err_out_free_ent
;
1411 base
= (unsigned long) mmio_base
;
1413 hpriv
= kmalloc(sizeof(*hpriv
), GFP_KERNEL
);
1416 goto err_out_iounmap
;
1418 memset(hpriv
, 0, sizeof(*hpriv
));
1420 dimm_mmio
= ioremap(pci_resource_start(pdev
, 4),
1421 pci_resource_len(pdev
, 4));
1425 goto err_out_iounmap
;
1428 hpriv
->dimm_mmio
= dimm_mmio
;
1430 probe_ent
->sht
= pdc_port_info
[board_idx
].sht
;
1431 probe_ent
->host_flags
= pdc_port_info
[board_idx
].host_flags
;
1432 probe_ent
->pio_mask
= pdc_port_info
[board_idx
].pio_mask
;
1433 probe_ent
->mwdma_mask
= pdc_port_info
[board_idx
].mwdma_mask
;
1434 probe_ent
->udma_mask
= pdc_port_info
[board_idx
].udma_mask
;
1435 probe_ent
->port_ops
= pdc_port_info
[board_idx
].port_ops
;
1437 probe_ent
->irq
= pdev
->irq
;
1438 probe_ent
->irq_flags
= SA_SHIRQ
;
1439 probe_ent
->mmio_base
= mmio_base
;
1441 probe_ent
->private_data
= hpriv
;
1442 base
+= PDC_CHIP0_OFS
;
1444 probe_ent
->n_ports
= 4;
1445 pdc_sata_setup_port(&probe_ent
->port
[0], base
+ 0x200);
1446 pdc_sata_setup_port(&probe_ent
->port
[1], base
+ 0x280);
1447 pdc_sata_setup_port(&probe_ent
->port
[2], base
+ 0x300);
1448 pdc_sata_setup_port(&probe_ent
->port
[3], base
+ 0x380);
1450 pci_set_master(pdev
);
1452 /* initialize adapter */
1453 /* initialize local dimm */
1454 if (pdc20621_dimm_init(probe_ent
)) {
1456 goto err_out_iounmap_dimm
;
1458 pdc_20621_init(probe_ent
);
1460 /* FIXME: check ata_device_add return value */
1461 ata_device_add(probe_ent
);
1466 err_out_iounmap_dimm
: /* only get to this label if 20621 */
1474 pci_release_regions(pdev
);
1476 pci_disable_device(pdev
);
1481 static int __init
pdc_sata_init(void)
1483 return pci_module_init(&pdc_sata_pci_driver
);
1487 static void __exit
pdc_sata_exit(void)
1489 pci_unregister_driver(&pdc_sata_pci_driver
);
1493 MODULE_AUTHOR("Jeff Garzik");
1494 MODULE_DESCRIPTION("Promise SATA low-level driver");
1495 MODULE_LICENSE("GPL");
1496 MODULE_DEVICE_TABLE(pci
, pdc_sata_pci_tbl
);
1498 module_init(pdc_sata_init
);
1499 module_exit(pdc_sata_exit
);