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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / pci / probe.c
blobe88017d6fd38922c031fc5f6ad74cfba89c8aa02
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/init.h>
6 #include <linux/pci.h>
7 #include <linux/slab.h>
8 #include <linux/module.h>
9 #include <linux/cpumask.h>
10
11 #undef DEBUG
12
13 #ifdef DEBUG
14 #define DBG(x...) printk(x)
15 #else
16 #define DBG(x...)
17 #endif
18
19 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
20 #define CARDBUS_RESERVE_BUSNR 3
21 #define PCI_CFG_SPACE_SIZE 256
22 #define PCI_CFG_SPACE_EXP_SIZE 4096
23
24 /* Ugh. Need to stop exporting this to modules. */
25 LIST_HEAD(pci_root_buses);
26 EXPORT_SYMBOL(pci_root_buses);
27
28 LIST_HEAD(pci_devices);
29
30 /*
31 * PCI Bus Class
32 */
33 static void release_pcibus_dev(struct class_device *class_dev)
34 {
35 struct pci_bus *pci_bus = to_pci_bus(class_dev);
36 if (pci_bus->bridge)
37 put_device(pci_bus->bridge);
38 kfree(pci_bus);
39 }
40
41 static struct class pcibus_class = {
42 .name = "pci_bus",
43 .release = &release_pcibus_dev,
44 };
45
46 static int __init pcibus_class_init(void)
47 {
48 return class_register(&pcibus_class);
49 }
50 postcore_initcall(pcibus_class_init);
51
52 /*
53 * PCI Bus Class Devices
54 */
55 static ssize_t pci_bus_show_cpuaffinity(struct class_device *class_dev, char *buf)
56 {
57 cpumask_t cpumask = pcibus_to_cpumask((to_pci_bus(class_dev))->number);
58 int ret;
59
60 ret = cpumask_scnprintf(buf, PAGE_SIZE, cpumask);
61 if (ret < PAGE_SIZE)
62 buf[ret++] = '\n';
63 return ret;
64 }
65 static CLASS_DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpuaffinity, NULL);
66
67 /*
68 * Translate the low bits of the PCI base
69 * to the resource type
70 */
71 static inline unsigned int pci_calc_resource_flags(unsigned int flags)
72 {
73 if (flags & PCI_BASE_ADDRESS_SPACE_IO)
74 return IORESOURCE_IO;
75
76 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
77 return IORESOURCE_MEM | IORESOURCE_PREFETCH;
78
79 return IORESOURCE_MEM;
80 }
81
82 /*
83 * Find the extent of a PCI decode..
84 */
85 static u32 pci_size(u32 base, u32 maxbase, unsigned long mask)
86 {
87 u32 size = mask & maxbase; /* Find the significant bits */
88 if (!size)
89 return 0;
90
91 /* Get the lowest of them to find the decode size, and
92 from that the extent. */
93 size = (size & ~(size-1)) - 1;
94
95 /* base == maxbase can be valid only if the BAR has
96 already been programmed with all 1s. */
97 if (base == maxbase && ((base | size) & mask) != mask)
98 return 0;
99
100 return size;
101 }
102
103 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
104 {
105 unsigned int pos, reg, next;
106 u32 l, sz;
107 struct resource *res;
108
109 for(pos=0; pos<howmany; pos = next) {
110 next = pos+1;
111 res = &dev->resource[pos];
112 res->name = pci_name(dev);
113 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
114 pci_read_config_dword(dev, reg, &l);
115 pci_write_config_dword(dev, reg, ~0);
116 pci_read_config_dword(dev, reg, &sz);
117 pci_write_config_dword(dev, reg, l);
118 if (!sz || sz == 0xffffffff)
119 continue;
120 if (l == 0xffffffff)
121 l = 0;
122 if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) {
123 sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK);
124 if (!sz)
125 continue;
126 res->start = l & PCI_BASE_ADDRESS_MEM_MASK;
127 res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK;
128 } else {
129 sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff);
130 if (!sz)
131 continue;
132 res->start = l & PCI_BASE_ADDRESS_IO_MASK;
133 res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK;
134 }
135 res->end = res->start + (unsigned long) sz;
136 res->flags |= pci_calc_resource_flags(l);
137 if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK))
138 == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) {
139 pci_read_config_dword(dev, reg+4, &l);
140 next++;
141 #if BITS_PER_LONG == 64
142 res->start |= ((unsigned long) l) << 32;
143 res->end = res->start + sz;
144 pci_write_config_dword(dev, reg+4, ~0);
145 pci_read_config_dword(dev, reg+4, &sz);
146 pci_write_config_dword(dev, reg+4, l);
147 if (~sz)
148 res->end = res->start + 0xffffffff +
149 (((unsigned long) ~sz) << 32);
150 #else
151 if (l) {
152 printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev));
153 res->start = 0;
154 res->flags = 0;
155 continue;
156 }
157 #endif
158 }
159 }
160 if (rom) {
161 dev->rom_base_reg = rom;
162 res = &dev->resource[PCI_ROM_RESOURCE];
163 res->name = pci_name(dev);
164 pci_read_config_dword(dev, rom, &l);
165 pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE);
166 pci_read_config_dword(dev, rom, &sz);
167 pci_write_config_dword(dev, rom, l);
168 if (l == 0xffffffff)
169 l = 0;
170 if (sz && sz != 0xffffffff) {
171 sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK);
172 if (sz) {
173 res->flags = (l & PCI_ROM_ADDRESS_ENABLE) |
174 IORESOURCE_MEM | IORESOURCE_PREFETCH |
175 IORESOURCE_READONLY | IORESOURCE_CACHEABLE;
176 res->start = l & PCI_ROM_ADDRESS_MASK;
177 res->end = res->start + (unsigned long) sz;
178 }
179 }
180 }
181 }
182
183 void __devinit pci_read_bridge_bases(struct pci_bus *child)
184 {
185 struct pci_dev *dev = child->self;
186 u8 io_base_lo, io_limit_lo;
187 u16 mem_base_lo, mem_limit_lo;
188 unsigned long base, limit;
189 struct resource *res;
190 int i;
191
192 if (!dev) /* It's a host bus, nothing to read */
193 return;
194
195 if (dev->transparent) {
196 printk(KERN_INFO "PCI: Transparent bridge - %s\n", pci_name(dev));
197 for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++)
198 child->resource[i] = child->parent->resource[i];
199 return;
200 }
201
202 for(i=0; i<3; i++)
203 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
204
205 res = child->resource[0];
206 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
207 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
208 base = (io_base_lo & PCI_IO_RANGE_MASK) << 8;
209 limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8;
210
211 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
212 u16 io_base_hi, io_limit_hi;
213 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
214 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
215 base |= (io_base_hi << 16);
216 limit |= (io_limit_hi << 16);
217 }
218
219 if (base <= limit) {
220 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
221 res->start = base;
222 res->end = limit + 0xfff;
223 }
224
225 res = child->resource[1];
226 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
227 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
228 base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
229 limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
230 if (base <= limit) {
231 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
232 res->start = base;
233 res->end = limit + 0xfffff;
234 }
235
236 res = child->resource[2];
237 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
238 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
239 base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
240 limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
241
242 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
243 u32 mem_base_hi, mem_limit_hi;
244 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
245 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
246 #if BITS_PER_LONG == 64
247 base |= ((long) mem_base_hi) << 32;
248 limit |= ((long) mem_limit_hi) << 32;
249 #else
250 if (mem_base_hi || mem_limit_hi) {
251 printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name);
252 return;
253 }
254 #endif
255 }
256 if (base <= limit) {
257 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH;
258 res->start = base;
259 res->end = limit + 0xfffff;
260 }
261 }
262
263 static struct pci_bus * __devinit pci_alloc_bus(void)
264 {
265 struct pci_bus *b;
266
267 b = kmalloc(sizeof(*b), GFP_KERNEL);
268 if (b) {
269 memset(b, 0, sizeof(*b));
270 INIT_LIST_HEAD(&b->node);
271 INIT_LIST_HEAD(&b->children);
272 INIT_LIST_HEAD(&b->devices);
273 }
274 return b;
275 }
276
277 static struct pci_bus * __devinit
278 pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr)
279 {
280 struct pci_bus *child;
281 int i;
282
283 /*
284 * Allocate a new bus, and inherit stuff from the parent..
285 */
286 child = pci_alloc_bus();
287 if (!child)
288 return NULL;
289
290 child->self = bridge;
291 child->parent = parent;
292 child->ops = parent->ops;
293 child->sysdata = parent->sysdata;
294 child->bridge = get_device(&bridge->dev);
295
296 child->class_dev.class = &pcibus_class;
297 sprintf(child->class_dev.class_id, "%04x:%02x", pci_domain_nr(child), busnr);
298 class_device_register(&child->class_dev);
299 class_device_create_file(&child->class_dev, &class_device_attr_cpuaffinity);
300
301 /*
302 * Set up the primary, secondary and subordinate
303 * bus numbers.
304 */
305 child->number = child->secondary = busnr;
306 child->primary = parent->secondary;
307 child->subordinate = 0xff;
308
309 /* Set up default resource pointers and names.. */
310 for (i = 0; i < 4; i++) {
311 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
312 child->resource[i]->name = child->name;
313 }
314 bridge->subordinate = child;
315
316 return child;
317 }
318
319 struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
320 {
321 struct pci_bus *child;
322
323 child = pci_alloc_child_bus(parent, dev, busnr);
324 if (child)
325 list_add_tail(&child->node, &parent->children);
326 return child;
327 }
328
329 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus);
330
331 /*
332 * If it's a bridge, configure it and scan the bus behind it.
333 * For CardBus bridges, we don't scan behind as the devices will
334 * be handled by the bridge driver itself.
335 *
336 * We need to process bridges in two passes -- first we scan those
337 * already configured by the BIOS and after we are done with all of
338 * them, we proceed to assigning numbers to the remaining buses in
339 * order to avoid overlaps between old and new bus numbers.
340 */
341 int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass)
342 {
343 struct pci_bus *child;
344 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
345 u32 buses;
346 u16 bctl;
347
348 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
349
350 DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n",
351 pci_name(dev), buses & 0xffffff, pass);
352
353 /* Disable MasterAbortMode during probing to avoid reporting
354 of bus errors (in some architectures) */
355 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
356 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
357 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
358
359 if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) {
360 unsigned int cmax, busnr;
361 /*
362 * Bus already configured by firmware, process it in the first
363 * pass and just note the configuration.
364 */
365 if (pass)
366 return max;
367 busnr = (buses >> 8) & 0xFF;
368 child = pci_alloc_child_bus(bus, dev, busnr);
369 if (!child)
370 return max;
371 child->primary = buses & 0xFF;
372 child->subordinate = (buses >> 16) & 0xFF;
373 child->bridge_ctl = bctl;
374
375 cmax = pci_scan_child_bus(child);
376 if (cmax > max)
377 max = cmax;
378 if (child->subordinate > max)
379 max = child->subordinate;
380 } else {
381 /*
382 * We need to assign a number to this bus which we always
383 * do in the second pass.
384 */
385 if (!pass)
386 return max;
387
388 /* Clear errors */
389 pci_write_config_word(dev, PCI_STATUS, 0xffff);
390
391 child = pci_alloc_child_bus(bus, dev, ++max);
392 buses = (buses & 0xff000000)
393 | ((unsigned int)(child->primary) << 0)
394 | ((unsigned int)(child->secondary) << 8)
395 | ((unsigned int)(child->subordinate) << 16);
396
397 /*
398 * yenta.c forces a secondary latency timer of 176.
399 * Copy that behaviour here.
400 */
401 if (is_cardbus) {
402 buses &= ~0xff000000;
403 buses |= CARDBUS_LATENCY_TIMER << 24;
404 }
405
406 /*
407 * We need to blast all three values with a single write.
408 */
409 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
410
411 if (!is_cardbus) {
412 child->bridge_ctl = PCI_BRIDGE_CTL_NO_ISA;
413
414 /* Now we can scan all subordinate buses... */
415 max = pci_scan_child_bus(child);
416 } else {
417 /*
418 * For CardBus bridges, we leave 4 bus numbers
419 * as cards with a PCI-to-PCI bridge can be
420 * inserted later.
421 */
422 max += CARDBUS_RESERVE_BUSNR;
423 }
424 /*
425 * Set the subordinate bus number to its real value.
426 */
427 child->subordinate = max;
428 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
429 }
430
431 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
432
433 sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number);
434
435 return max;
436 }
437
438 /*
439 * Read interrupt line and base address registers.
440 * The architecture-dependent code can tweak these, of course.
441 */
442 static void pci_read_irq(struct pci_dev *dev)
443 {
444 unsigned char irq;
445
446 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
447 if (irq)
448 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
449 dev->irq = irq;
450 }
451
452 /**
453 * pci_setup_device - fill in class and map information of a device
454 * @dev: the device structure to fill
455 *
456 * Initialize the device structure with information about the device's
457 * vendor,class,memory and IO-space addresses,IRQ lines etc.
458 * Called at initialisation of the PCI subsystem and by CardBus services.
459 * Returns 0 on success and -1 if unknown type of device (not normal, bridge
460 * or CardBus).
461 */
462 static int pci_setup_device(struct pci_dev * dev)
463 {
464 u32 class;
465
466 dev->slot_name = dev->dev.bus_id;
467 sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
468 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
469
470 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
471 class >>= 8; /* upper 3 bytes */
472 dev->class = class;
473 class >>= 8;
474
475 DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number,
476 dev->devfn, dev->vendor, dev->device, class, dev->hdr_type);
477
478 /* "Unknown power state" */
479 dev->current_state = 4;
480
481 switch (dev->hdr_type) { /* header type */
482 case PCI_HEADER_TYPE_NORMAL: /* standard header */
483 if (class == PCI_CLASS_BRIDGE_PCI)
484 goto bad;
485 pci_read_irq(dev);
486 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
487 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
488 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
489 break;
490
491 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
492 if (class != PCI_CLASS_BRIDGE_PCI)
493 goto bad;
494 /* The PCI-to-PCI bridge spec requires that subtractive
495 decoding (i.e. transparent) bridge must have programming
496 interface code of 0x01. */
497 dev->transparent = ((dev->class & 0xff) == 1);
498 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
499 break;
500
501 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
502 if (class != PCI_CLASS_BRIDGE_CARDBUS)
503 goto bad;
504 pci_read_irq(dev);
505 pci_read_bases(dev, 1, 0);
506 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
507 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
508 break;
509
510 default: /* unknown header */
511 printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n",
512 pci_name(dev), dev->hdr_type);
513 return -1;
514
515 bad:
516 printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n",
517 pci_name(dev), class, dev->hdr_type);
518 dev->class = PCI_CLASS_NOT_DEFINED;
519 }
520
521 /* We found a fine healthy device, go go go... */
522 return 0;
523 }
524
525 /**
526 * pci_release_dev - free a pci device structure when all users of it are finished.
527 * @dev: device that's been disconnected
528 *
529 * Will be called only by the device core when all users of this pci device are
530 * done.
531 */
532 static void pci_release_dev(struct device *dev)
533 {
534 struct pci_dev *pci_dev;
535
536 pci_dev = to_pci_dev(dev);
537 kfree(pci_dev);
538 }
539
540 /**
541 * pci_cfg_space_size - get the configuration space size of the PCI device.
542 *
543 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
544 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
545 * access it. Maybe we don't have a way to generate extended config space
546 * accesses, or the device is behind a reverse Express bridge. So we try
547 * reading the dword at 0x100 which must either be 0 or a valid extended
548 * capability header.
549 */
550 static int pci_cfg_space_size(struct pci_dev *dev)
551 {
552 int pos;
553 u32 status;
554
555 pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
556 if (!pos) {
557 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
558 if (!pos)
559 goto fail;
560
561 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
562 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
563 goto fail;
564 }
565
566 if (pci_read_config_dword(dev, 256, &status) != PCIBIOS_SUCCESSFUL)
567 goto fail;
568 if (status == 0xffffffff)
569 goto fail;
570
571 return PCI_CFG_SPACE_EXP_SIZE;
572
573 fail:
574 return PCI_CFG_SPACE_SIZE;
575 }
576
577 static void pci_release_bus_bridge_dev(struct device *dev)
578 {
579 kfree(dev);
580 }
581
582 /*
583 * Read the config data for a PCI device, sanity-check it
584 * and fill in the dev structure...
585 */
586 static struct pci_dev * __devinit
587 pci_scan_device(struct pci_bus *bus, int devfn)
588 {
589 struct pci_dev *dev;
590 u32 l;
591 u8 hdr_type;
592
593 if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type))
594 return NULL;
595
596 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l))
597 return NULL;
598
599 /* some broken boards return 0 or ~0 if a slot is empty: */
600 if (l == 0xffffffff || l == 0x00000000 ||
601 l == 0x0000ffff || l == 0xffff0000)
602 return NULL;
603
604 dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL);
605 if (!dev)
606 return NULL;
607
608 memset(dev, 0, sizeof(struct pci_dev));
609 dev->bus = bus;
610 dev->sysdata = bus->sysdata;
611 dev->dev.parent = bus->bridge;
612 dev->dev.bus = &pci_bus_type;
613 dev->devfn = devfn;
614 dev->hdr_type = hdr_type & 0x7f;
615 dev->multifunction = !!(hdr_type & 0x80);
616 dev->vendor = l & 0xffff;
617 dev->device = (l >> 16) & 0xffff;
618 dev->cfg_size = pci_cfg_space_size(dev);
619
620 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
621 set this higher, assuming the system even supports it. */
622 dev->dma_mask = 0xffffffff;
623 if (pci_setup_device(dev) < 0) {
624 kfree(dev);
625 return NULL;
626 }
627 device_initialize(&dev->dev);
628 dev->dev.release = pci_release_dev;
629 pci_dev_get(dev);
630
631 pci_name_device(dev);
632
633 dev->dev.dma_mask = &dev->dma_mask;
634 dev->dev.coherent_dma_mask = 0xffffffffull;
635
636 return dev;
637 }
638
639 struct pci_dev * __devinit
640 pci_scan_single_device(struct pci_bus *bus, int devfn)
641 {
642 struct pci_dev *dev;
643
644 dev = pci_scan_device(bus, devfn);
645 pci_scan_msi_device(dev);
646
647 if (!dev)
648 return NULL;
649
650 /* Fix up broken headers */
651 pci_fixup_device(pci_fixup_header, dev);
652
653 /*
654 * Add the device to our list of discovered devices
655 * and the bus list for fixup functions, etc.
656 */
657 INIT_LIST_HEAD(&dev->global_list);
658 list_add_tail(&dev->bus_list, &bus->devices);
659
660 return dev;
661 }
662
663 /**
664 * pci_scan_slot - scan a PCI slot on a bus for devices.
665 * @bus: PCI bus to scan
666 * @devfn: slot number to scan (must have zero function.)
667 *
668 * Scan a PCI slot on the specified PCI bus for devices, adding
669 * discovered devices to the @bus->devices list. New devices
670 * will have an empty dev->global_list head.
671 */
672 int __devinit pci_scan_slot(struct pci_bus *bus, int devfn)
673 {
674 int func, nr = 0;
675 int scan_all_fns;
676
677 scan_all_fns = pcibios_scan_all_fns(bus, devfn);
678
679 for (func = 0; func < 8; func++, devfn++) {
680 struct pci_dev *dev;
681
682 dev = pci_scan_single_device(bus, devfn);
683 if (dev) {
684 nr++;
685
686 /*
687 * If this is a single function device,
688 * don't scan past the first function.
689 */
690 if (!dev->multifunction) {
691 if (func > 0) {
692 dev->multifunction = 1;
693 } else {
694 break;
695 }
696 }
697 } else {
698 if (func == 0 && !scan_all_fns)
699 break;
700 }
701 }
702 return nr;
703 }
704
705 unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus)
706 {
707 unsigned int devfn, pass, max = bus->secondary;
708 struct pci_dev *dev;
709
710 DBG("Scanning bus %02x\n", bus->number);
711
712 /* Go find them, Rover! */
713 for (devfn = 0; devfn < 0x100; devfn += 8)
714 pci_scan_slot(bus, devfn);
715
716 /*
717 * After performing arch-dependent fixup of the bus, look behind
718 * all PCI-to-PCI bridges on this bus.
719 */
720 DBG("Fixups for bus %02x\n", bus->number);
721 pcibios_fixup_bus(bus);
722 for (pass=0; pass < 2; pass++)
723 list_for_each_entry(dev, &bus->devices, bus_list) {
724 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
725 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
726 max = pci_scan_bridge(bus, dev, max, pass);
727 }
728
729 /*
730 * We've scanned the bus and so we know all about what's on
731 * the other side of any bridges that may be on this bus plus
732 * any devices.
733 *
734 * Return how far we've got finding sub-buses.
735 */
736 DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max);
737 return max;
738 }
739
740 unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus)
741 {
742 unsigned int max;
743
744 max = pci_scan_child_bus(bus);
745
746 /*
747 * Make the discovered devices available.
748 */
749 pci_bus_add_devices(bus);
750
751 return max;
752 }
753
754 struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata)
755 {
756 struct pci_bus *b;
757 struct device *dev;
758
759 b = pci_alloc_bus();
760 if (!b)
761 return NULL;
762
763 dev = kmalloc(sizeof(*dev), GFP_KERNEL);
764 if (!dev){
765 kfree(b);
766 return NULL;
767 }
768
769 b->sysdata = sysdata;
770 b->ops = ops;
771
772 if (pci_find_bus(pci_domain_nr(b), bus)) {
773 /* If we already got to this bus through a different bridge, ignore it */
774 DBG("PCI: Bus %02x already known\n", bus);
775 kfree(dev);
776 kfree(b);
777 return NULL;
778 }
779 list_add_tail(&b->node, &pci_root_buses);
780
781 memset(dev, 0, sizeof(*dev));
782 dev->parent = parent;
783 dev->release = pci_release_bus_bridge_dev;
784 sprintf(dev->bus_id, "pci%04x:%02x", pci_domain_nr(b), bus);
785 device_register(dev);
786 b->bridge = get_device(dev);
787
788 b->class_dev.class = &pcibus_class;
789 sprintf(b->class_dev.class_id, "%04x:%02x", pci_domain_nr(b), bus);
790 class_device_register(&b->class_dev);
791 class_device_create_file(&b->class_dev, &class_device_attr_cpuaffinity);
792
793 sysfs_create_link(&b->class_dev.kobj, &b->bridge->kobj, "bridge");
794
795 b->number = b->secondary = bus;
796 b->resource[0] = &ioport_resource;
797 b->resource[1] = &iomem_resource;
798
799 b->subordinate = pci_scan_child_bus(b);
800
801 pci_bus_add_devices(b);
802
803 return b;
804 }
805 EXPORT_SYMBOL(pci_scan_bus_parented);
806
807 #ifdef CONFIG_HOTPLUG
808 EXPORT_SYMBOL(pci_add_new_bus);
809 EXPORT_SYMBOL(pci_do_scan_bus);
810 EXPORT_SYMBOL(pci_scan_slot);
811 EXPORT_SYMBOL(pci_scan_bridge);
812 EXPORT_SYMBOL(pci_scan_single_device);
813 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
814 #endif
MOXA 2.6.9 from sdlinux-moxaart.tgz