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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / net / wan / wanxl.c
blob6370aa7c2760bab093274f6775615dac11cf207d
1 /*
2 * wanXL serial card driver for Linux
3 * host part
4 *
5 * Copyright (C) 2003 Krzysztof Halasa <khc@pm.waw.pl>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License
9 * as published by the Free Software Foundation.
10 *
11 * Status:
12 * - Only DTE (external clock) support with NRZ and NRZI encodings
13 * - wanXL100 will require minor driver modifications, no access to hw
14 */
15
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/slab.h>
19 #include <linux/sched.h>
20 #include <linux/types.h>
21 #include <linux/fcntl.h>
22 #include <linux/string.h>
23 #include <linux/errno.h>
24 #include <linux/init.h>
25 #include <linux/ioport.h>
26 #include <linux/netdevice.h>
27 #include <linux/hdlc.h>
28 #include <linux/pci.h>
29 #include <asm/io.h>
30 #include <asm/delay.h>
31
32 #include "wanxl.h"
33
34 static const char* version = "wanXL serial card driver version: 0.48";
35
36 #define PLX_CTL_RESET 0x40000000 /* adapter reset */
37
38 #undef DEBUG_PKT
39 #undef DEBUG_PCI
40
41 /* MAILBOX #1 - PUTS COMMANDS */
42 #define MBX1_CMD_ABORTJ 0x85000000 /* Abort and Jump */
43 #ifdef __LITTLE_ENDIAN
44 #define MBX1_CMD_BSWAP 0x8C000001 /* little-endian Byte Swap Mode */
45 #else
46 #define MBX1_CMD_BSWAP 0x8C000000 /* big-endian Byte Swap Mode */
47 #endif
48
49 /* MAILBOX #2 - DRAM SIZE */
50 #define MBX2_MEMSZ_MASK 0xFFFF0000 /* PUTS Memory Size Register mask */
51
52
53 typedef struct {
54 struct net_device *dev;
55 struct card_t *card;
56 spinlock_t lock; /* for wanxl_xmit */
57 int node; /* physical port #0 - 3 */
58 unsigned int clock_type;
59 int tx_in, tx_out;
60 struct sk_buff *tx_skbs[TX_BUFFERS];
61 }port_t;
62
63
64 typedef struct {
65 desc_t rx_descs[RX_QUEUE_LENGTH];
66 port_status_t port_status[4];
67 }card_status_t;
68
69
70 typedef struct card_t {
71 int n_ports; /* 1, 2 or 4 ports */
72 u8 irq;
73
74 u8 *plx; /* PLX PCI9060 virtual base address */
75 struct pci_dev *pdev; /* for pdev->slot_name */
76 int rx_in;
77 struct sk_buff *rx_skbs[RX_QUEUE_LENGTH];
78 card_status_t *status; /* shared between host and card */
79 dma_addr_t status_address;
80 port_t ports[0]; /* 1 - 4 port_t structures follow */
81 }card_t;
82
83
84
85 static inline port_t* dev_to_port(struct net_device *dev)
86 {
87 return (port_t *)dev_to_hdlc(dev)->priv;
88 }
89
90
91 static inline const char* card_name(struct pci_dev *pdev)
92 {
93 return pdev->slot_name;
94 }
95
96
97 static inline port_status_t* get_status(port_t *port)
98 {
99 return &port->card->status->port_status[port->node];
100 }
101
102
103 #ifdef DEBUG_PCI
104 static inline dma_addr_t pci_map_single_debug(struct pci_dev *pdev, void *ptr,
105 size_t size, int direction)
106 {
107 dma_addr_t addr = pci_map_single(pdev, ptr, size, direction);
108 if (addr + size > 0x100000000LL)
109 printk(KERN_CRIT "wanXL %s: pci_map_single() returned memory"
110 " at 0x%LX!\n", card_name(pdev),
111 (unsigned long long)addr);
112 return addr;
113 }
114
115 #undef pci_map_single
116 #define pci_map_single pci_map_single_debug
117 #endif
118
119
120 /* Cable and/or personality module change interrupt service */
121 static inline void wanxl_cable_intr(port_t *port)
122 {
123 u32 value = get_status(port)->cable;
124 int valid = 1;
125 const char *cable, *pm, *dte = "", *dsr = "", *dcd = "";
126
127 switch(value & 0x7) {
128 case STATUS_CABLE_V35: cable = "V.35"; break;
129 case STATUS_CABLE_X21: cable = "X.21"; break;
130 case STATUS_CABLE_V24: cable = "V.24"; break;
131 case STATUS_CABLE_EIA530: cable = "EIA530"; break;
132 case STATUS_CABLE_NONE: cable = "no"; break;
133 default: cable = "invalid";
134 }
135
136 switch((value >> STATUS_CABLE_PM_SHIFT) & 0x7) {
137 case STATUS_CABLE_V35: pm = "V.35"; break;
138 case STATUS_CABLE_X21: pm = "X.21"; break;
139 case STATUS_CABLE_V24: pm = "V.24"; break;
140 case STATUS_CABLE_EIA530: pm = "EIA530"; break;
141 case STATUS_CABLE_NONE: pm = "no personality"; valid = 0; break;
142 default: pm = "invalid personality"; valid = 0;
143 }
144
145 if (valid) {
146 if ((value & 7) == ((value >> STATUS_CABLE_PM_SHIFT) & 7)) {
147 dsr = (value & STATUS_CABLE_DSR) ? ", DSR ON" :
148 ", DSR off";
149 dcd = (value & STATUS_CABLE_DCD) ? ", carrier ON" :
150 ", carrier off";
151 }
152 dte = (value & STATUS_CABLE_DCE) ? " DCE" : " DTE";
153 }
154 printk(KERN_INFO "%s: %s%s module, %s cable%s%s\n",
155 port->dev->name, pm, dte, cable, dsr, dcd);
156
157 hdlc_set_carrier(value & STATUS_CABLE_DCD, port->dev);
158 }
159
160
161
162 /* Transmit complete interrupt service */
163 static inline void wanxl_tx_intr(port_t *port)
164 {
165 struct net_device *dev = port->dev;
166 struct net_device_stats *stats = hdlc_stats(dev);
167 while (1) {
168 desc_t *desc = &get_status(port)->tx_descs[port->tx_in];
169 struct sk_buff *skb = port->tx_skbs[port->tx_in];
170
171 switch (desc->stat) {
172 case PACKET_FULL:
173 case PACKET_EMPTY:
174 netif_wake_queue(dev);
175 return;
176
177 case PACKET_UNDERRUN:
178 stats->tx_errors++;
179 stats->tx_fifo_errors++;
180 break;
181
182 default:
183 stats->tx_packets++;
184 stats->tx_bytes += skb->len;
185 }
186 desc->stat = PACKET_EMPTY; /* Free descriptor */
187 pci_unmap_single(port->card->pdev, desc->address, skb->len,
188 PCI_DMA_TODEVICE);
189 dev_kfree_skb_irq(skb);
190 port->tx_in = (port->tx_in + 1) % TX_BUFFERS;
191 }
192 }
193
194
195
196 /* Receive complete interrupt service */
197 static inline void wanxl_rx_intr(card_t *card)
198 {
199 desc_t *desc;
200 while (desc = &card->status->rx_descs[card->rx_in],
201 desc->stat != PACKET_EMPTY) {
202 if ((desc->stat & PACKET_PORT_MASK) > card->n_ports)
203 printk(KERN_CRIT "wanXL %s: received packet for"
204 " nonexistent port\n", card_name(card->pdev));
205 else {
206 struct sk_buff *skb = card->rx_skbs[card->rx_in];
207 port_t *port = &card->ports[desc->stat &
208 PACKET_PORT_MASK];
209 struct net_device *dev = port->dev;
210 struct net_device_stats *stats = hdlc_stats(dev);
211
212 if (!skb)
213 stats->rx_dropped++;
214 else {
215 pci_unmap_single(card->pdev, desc->address,
216 BUFFER_LENGTH,
217 PCI_DMA_FROMDEVICE);
218 skb_put(skb, desc->length);
219
220 #ifdef DEBUG_PKT
221 printk(KERN_DEBUG "%s RX(%i):", dev->name,
222 skb->len);
223 debug_frame(skb);
224 #endif
225 stats->rx_packets++;
226 stats->rx_bytes += skb->len;
227 skb->mac.raw = skb->data;
228 skb->dev = dev;
229 dev->last_rx = jiffies;
230 skb->protocol = hdlc_type_trans(skb, dev);
231 netif_rx(skb);
232 skb = NULL;
233 }
234
235 if (!skb) {
236 skb = dev_alloc_skb(BUFFER_LENGTH);
237 desc->address = skb ?
238 pci_map_single(card->pdev, skb->data,
239 BUFFER_LENGTH,
240 PCI_DMA_FROMDEVICE) : 0;
241 card->rx_skbs[card->rx_in] = skb;
242 }
243 }
244 desc->stat = PACKET_EMPTY; /* Free descriptor */
245 card->rx_in = (card->rx_in + 1) % RX_QUEUE_LENGTH;
246 }
247 }
248
249
250
251 static irqreturn_t wanxl_intr(int irq, void* dev_id, struct pt_regs *regs)
252 {
253 card_t *card = dev_id;
254 int i;
255 u32 stat;
256 int handled = 0;
257
258
259 while((stat = readl(card->plx + PLX_DOORBELL_FROM_CARD)) != 0) {
260 handled = 1;
261 writel(stat, card->plx + PLX_DOORBELL_FROM_CARD);
262
263 for (i = 0; i < card->n_ports; i++) {
264 if (stat & (1 << (DOORBELL_FROM_CARD_TX_0 + i)))
265 wanxl_tx_intr(&card->ports[i]);
266 if (stat & (1 << (DOORBELL_FROM_CARD_CABLE_0 + i)))
267 wanxl_cable_intr(&card->ports[i]);
268 }
269 if (stat & (1 << DOORBELL_FROM_CARD_RX))
270 wanxl_rx_intr(card);
271 }
272
273 return IRQ_RETVAL(handled);
274 }
275
276
277
278 static int wanxl_xmit(struct sk_buff *skb, struct net_device *dev)
279 {
280 port_t *port = dev_to_port(dev);
281 desc_t *desc;
282
283 spin_lock(&port->lock);
284
285 desc = &get_status(port)->tx_descs[port->tx_out];
286 if (desc->stat != PACKET_EMPTY) {
287 /* should never happen - previous xmit should stop queue */
288 #ifdef DEBUG_PKT
289 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
290 #endif
291 netif_stop_queue(dev);
292 spin_unlock_irq(&port->lock);
293 return 1; /* request packet to be queued */
294 }
295
296 #ifdef DEBUG_PKT
297 printk(KERN_DEBUG "%s TX(%i):", dev->name, skb->len);
298 debug_frame(skb);
299 #endif
300
301 port->tx_skbs[port->tx_out] = skb;
302 desc->address = pci_map_single(port->card->pdev, skb->data, skb->len,
303 PCI_DMA_TODEVICE);
304 desc->length = skb->len;
305 desc->stat = PACKET_FULL;
306 writel(1 << (DOORBELL_TO_CARD_TX_0 + port->node),
307 port->card->plx + PLX_DOORBELL_TO_CARD);
308 dev->trans_start = jiffies;
309
310 port->tx_out = (port->tx_out + 1) % TX_BUFFERS;
311
312 if (get_status(port)->tx_descs[port->tx_out].stat != PACKET_EMPTY) {
313 netif_stop_queue(dev);
314 #ifdef DEBUG_PKT
315 printk(KERN_DEBUG "%s: transmitter buffer full\n", dev->name);
316 #endif
317 }
318
319 spin_unlock(&port->lock);
320 return 0;
321 }
322
323
324
325 static int wanxl_attach(struct net_device *dev, unsigned short encoding,
326 unsigned short parity)
327 {
328 port_t *port = dev_to_port(dev);
329
330 if (encoding != ENCODING_NRZ &&
331 encoding != ENCODING_NRZI)
332 return -EINVAL;
333
334 if (parity != PARITY_NONE &&
335 parity != PARITY_CRC32_PR1_CCITT &&
336 parity != PARITY_CRC16_PR1_CCITT &&
337 parity != PARITY_CRC32_PR0_CCITT &&
338 parity != PARITY_CRC16_PR0_CCITT)
339 return -EINVAL;
340
341 get_status(port)->encoding = encoding;
342 get_status(port)->parity = parity;
343 return 0;
344 }
345
346
347
348 static int wanxl_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
349 {
350 const size_t size = sizeof(sync_serial_settings);
351 sync_serial_settings line;
352 port_t *port = dev_to_port(dev);
353
354 if (cmd != SIOCWANDEV)
355 return hdlc_ioctl(dev, ifr, cmd);
356
357 switch (ifr->ifr_settings.type) {
358 case IF_GET_IFACE:
359 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
360 if (ifr->ifr_settings.size < size) {
361 ifr->ifr_settings.size = size; /* data size wanted */
362 return -ENOBUFS;
363 }
364 line.clock_type = get_status(port)->clocking;
365 line.clock_rate = 0;
366 line.loopback = 0;
367
368 if (copy_to_user(ifr->ifr_settings.ifs_ifsu.sync, &line, size))
369 return -EFAULT;
370 return 0;
371
372 case IF_IFACE_SYNC_SERIAL:
373 if (!capable(CAP_NET_ADMIN))
374 return -EPERM;
375 if (dev->flags & IFF_UP)
376 return -EBUSY;
377
378 if (copy_from_user(&line, ifr->ifr_settings.ifs_ifsu.sync,
379 size))
380 return -EFAULT;
381
382 if (line.clock_type != CLOCK_EXT &&
383 line.clock_type != CLOCK_TXFROMRX)
384 return -EINVAL; /* No such clock setting */
385
386 if (line.loopback != 0)
387 return -EINVAL;
388
389 get_status(port)->clocking = line.clock_type;
390 return 0;
391
392 default:
393 return hdlc_ioctl(dev, ifr, cmd);
394 }
395 }
396
397
398
399 static int wanxl_open(struct net_device *dev)
400 {
401 port_t *port = dev_to_port(dev);
402 u8 *dbr = port->card->plx + PLX_DOORBELL_TO_CARD;
403 unsigned long timeout;
404 int i;
405
406 if (get_status(port)->open) {
407 printk(KERN_ERR "%s: port already open\n", dev->name);
408 return -EIO;
409 }
410 if ((i = hdlc_open(dev)) != 0)
411 return i;
412
413 port->tx_in = port->tx_out = 0;
414 for (i = 0; i < TX_BUFFERS; i++)
415 get_status(port)->tx_descs[i].stat = PACKET_EMPTY;
416 /* signal the card */
417 writel(1 << (DOORBELL_TO_CARD_OPEN_0 + port->node), dbr);
418
419 timeout = jiffies + HZ;
420 do
421 if (get_status(port)->open) {
422 netif_start_queue(dev);
423 return 0;
424 }
425 while (time_after(timeout, jiffies));
426
427 printk(KERN_ERR "%s: unable to open port\n", dev->name);
428 /* ask the card to close the port, should it be still alive */
429 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node), dbr);
430 return -EFAULT;
431 }
432
433
434
435 static int wanxl_close(struct net_device *dev)
436 {
437 port_t *port = dev_to_port(dev);
438 unsigned long timeout;
439 int i;
440
441 hdlc_close(dev);
442 /* signal the card */
443 writel(1 << (DOORBELL_TO_CARD_CLOSE_0 + port->node),
444 port->card->plx + PLX_DOORBELL_TO_CARD);
445
446 timeout = jiffies + HZ;
447 do
448 if (!get_status(port)->open)
449 break;
450 while (time_after(timeout, jiffies));
451
452 if (get_status(port)->open)
453 printk(KERN_ERR "%s: unable to close port\n", dev->name);
454
455 netif_stop_queue(dev);
456
457 for (i = 0; i < TX_BUFFERS; i++) {
458 desc_t *desc = &get_status(port)->tx_descs[i];
459
460 if (desc->stat != PACKET_EMPTY) {
461 desc->stat = PACKET_EMPTY;
462 pci_unmap_single(port->card->pdev, desc->address,
463 port->tx_skbs[i]->len,
464 PCI_DMA_TODEVICE);
465 dev_kfree_skb(port->tx_skbs[i]);
466 }
467 }
468 return 0;
469 }
470
471
472
473 static struct net_device_stats *wanxl_get_stats(struct net_device *dev)
474 {
475 struct net_device_stats *stats = hdlc_stats(dev);
476 port_t *port = dev_to_port(dev);
477
478 stats->rx_over_errors = get_status(port)->rx_overruns;
479 stats->rx_frame_errors = get_status(port)->rx_frame_errors;
480 stats->rx_errors = stats->rx_over_errors + stats->rx_frame_errors;
481 return stats;
482 }
483
484
485
486 static int wanxl_puts_command(card_t *card, u32 cmd)
487 {
488 unsigned long timeout = jiffies + 5 * HZ;
489
490 writel(cmd, card->plx + PLX_MAILBOX_1);
491 do {
492 if (readl(card->plx + PLX_MAILBOX_1) == 0)
493 return 0;
494
495 schedule();
496 }while (time_after(timeout, jiffies));
497
498 return -1;
499 }
500
501
502
503 static void wanxl_reset(card_t *card)
504 {
505 u32 old_value = readl(card->plx + PLX_CONTROL) & ~PLX_CTL_RESET;
506
507 writel(0x80, card->plx + PLX_MAILBOX_0);
508 writel(old_value | PLX_CTL_RESET, card->plx + PLX_CONTROL);
509 readl(card->plx + PLX_CONTROL); /* wait for posted write */
510 udelay(1);
511 writel(old_value, card->plx + PLX_CONTROL);
512 readl(card->plx + PLX_CONTROL); /* wait for posted write */
513 }
514
515
516
517 static void wanxl_pci_remove_one(struct pci_dev *pdev)
518 {
519 card_t *card = pci_get_drvdata(pdev);
520 int i;
521
522 for (i = 0; i < card->n_ports; i++) {
523 unregister_hdlc_device(card->ports[i].dev);
524 free_netdev(card->ports[i].dev);
525 }
526
527 /* unregister and free all host resources */
528 if (card->irq)
529 free_irq(card->irq, card);
530
531 wanxl_reset(card);
532
533 for (i = 0; i < RX_QUEUE_LENGTH; i++)
534 if (card->rx_skbs[i]) {
535 pci_unmap_single(card->pdev,
536 card->status->rx_descs[i].address,
537 BUFFER_LENGTH, PCI_DMA_FROMDEVICE);
538 dev_kfree_skb(card->rx_skbs[i]);
539 }
540
541 if (card->plx)
542 iounmap(card->plx);
543
544 if (card->status)
545 pci_free_consistent(pdev, sizeof(card_status_t),
546 card->status, card->status_address);
547
548 pci_release_regions(pdev);
549 pci_disable_device(pdev);
550 pci_set_drvdata(pdev, NULL);
551 kfree(card);
552 }
553
554
555 #include "wanxlfw.inc"
556
557 static int __devinit wanxl_pci_init_one(struct pci_dev *pdev,
558 const struct pci_device_id *ent)
559 {
560 card_t *card;
561 u32 ramsize, stat;
562 unsigned long timeout;
563 u32 plx_phy; /* PLX PCI base address */
564 u32 mem_phy; /* memory PCI base addr */
565 u8 *mem; /* memory virtual base addr */
566 int i, ports, alloc_size;
567
568 #ifndef MODULE
569 static int printed_version;
570 if (!printed_version) {
571 printed_version++;
572 printk(KERN_INFO "%s\n", version);
573 }
574 #endif
575
576 i = pci_enable_device(pdev);
577 if (i)
578 return i;
579
580 /* QUICC can only access first 256 MB of host RAM directly,
581 but PLX9060 DMA does 32-bits for actual packet data transfers */
582
583 /* FIXME when PCI/DMA subsystems are fixed.
584 We set both dma_mask and consistent_dma_mask to 28 bits
585 and pray pci_alloc_consistent() will use this info. It should
586 work on most platforms */
587 if (pci_set_consistent_dma_mask(pdev, 0x0FFFFFFF) ||
588 pci_set_dma_mask(pdev, 0x0FFFFFFF)) {
589 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
590 return -EIO;
591 }
592
593 i = pci_request_regions(pdev, "wanXL");
594 if (i) {
595 pci_disable_device(pdev);
596 return i;
597 }
598
599 switch (pdev->device) {
600 case PCI_DEVICE_ID_SBE_WANXL100: ports = 1; break;
601 case PCI_DEVICE_ID_SBE_WANXL200: ports = 2; break;
602 default: ports = 4;
603 }
604
605 alloc_size = sizeof(card_t) + ports * sizeof(port_t);
606 card = kmalloc(alloc_size, GFP_KERNEL);
607 if (card == NULL) {
608 printk(KERN_ERR "wanXL %s: unable to allocate memory\n",
609 card_name(pdev));
610 pci_release_regions(pdev);
611 pci_disable_device(pdev);
612 return -ENOBUFS;
613 }
614 memset(card, 0, alloc_size);
615
616 pci_set_drvdata(pdev, card);
617 card->pdev = pdev;
618
619 card->status = pci_alloc_consistent(pdev, sizeof(card_status_t),
620 &card->status_address);
621 if (card->status == NULL) {
622 wanxl_pci_remove_one(pdev);
623 return -ENOBUFS;
624 }
625
626 #ifdef DEBUG_PCI
627 printk(KERN_DEBUG "wanXL %s: pci_alloc_consistent() returned memory"
628 " at 0x%LX\n", card_name(pdev),
629 (unsigned long long)card->status_address);
630 #endif
631
632 /* FIXME when PCI/DMA subsystems are fixed.
633 We set both dma_mask and consistent_dma_mask back to 32 bits
634 to indicate the card can do 32-bit DMA addressing */
635 if (pci_set_consistent_dma_mask(pdev, 0xFFFFFFFF) ||
636 pci_set_dma_mask(pdev, 0xFFFFFFFF)) {
637 printk(KERN_ERR "wanXL: No usable DMA configuration\n");
638 wanxl_pci_remove_one(pdev);
639 return -EIO;
640 }
641
642 /* set up PLX mapping */
643 plx_phy = pci_resource_start(pdev, 0);
644 card->plx = ioremap_nocache(plx_phy, 0x70);
645
646 #if RESET_WHILE_LOADING
647 wanxl_reset(card);
648 #endif
649
650 timeout = jiffies + 20 * HZ;
651 while ((stat = readl(card->plx + PLX_MAILBOX_0)) != 0) {
652 if (time_before(timeout, jiffies)) {
653 printk(KERN_WARNING "wanXL %s: timeout waiting for"
654 " PUTS to complete\n", card_name(pdev));
655 wanxl_pci_remove_one(pdev);
656 return -ENODEV;
657 }
658
659 switch(stat & 0xC0) {
660 case 0x00: /* hmm - PUTS completed with non-zero code? */
661 case 0x80: /* PUTS still testing the hardware */
662 break;
663
664 default:
665 printk(KERN_WARNING "wanXL %s: PUTS test 0x%X"
666 " failed\n", card_name(pdev), stat & 0x30);
667 wanxl_pci_remove_one(pdev);
668 return -ENODEV;
669 }
670
671 schedule();
672 }
673
674 /* get on-board memory size (PUTS detects no more than 4 MB) */
675 ramsize = readl(card->plx + PLX_MAILBOX_2) & MBX2_MEMSZ_MASK;
676
677 /* set up on-board RAM mapping */
678 mem_phy = pci_resource_start(pdev, 2);
679
680
681 /* sanity check the board's reported memory size */
682 if (ramsize < BUFFERS_ADDR +
683 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports) {
684 printk(KERN_WARNING "wanXL %s: no enough on-board RAM"
685 " (%u bytes detected, %u bytes required)\n",
686 card_name(pdev), ramsize, BUFFERS_ADDR +
687 (TX_BUFFERS + RX_BUFFERS) * BUFFER_LENGTH * ports);
688 wanxl_pci_remove_one(pdev);
689 return -ENODEV;
690 }
691
692 if (wanxl_puts_command(card, MBX1_CMD_BSWAP)) {
693 printk(KERN_WARNING "wanXL %s: unable to Set Byte Swap"
694 " Mode\n", card_name(pdev));
695 wanxl_pci_remove_one(pdev);
696 return -ENODEV;
697 }
698
699 for (i = 0; i < RX_QUEUE_LENGTH; i++) {
700 struct sk_buff *skb = dev_alloc_skb(BUFFER_LENGTH);
701 card->rx_skbs[i] = skb;
702 if (skb)
703 card->status->rx_descs[i].address =
704 pci_map_single(card->pdev, skb->data,
705 BUFFER_LENGTH,
706 PCI_DMA_FROMDEVICE);
707 }
708
709 mem = ioremap_nocache(mem_phy, PDM_OFFSET + sizeof(firmware));
710 for (i = 0; i < sizeof(firmware); i += 4)
711 writel(htonl(*(u32*)(firmware + i)), mem + PDM_OFFSET + i);
712
713 for (i = 0; i < ports; i++)
714 writel(card->status_address +
715 (void *)&card->status->port_status[i] -
716 (void *)card->status, mem + PDM_OFFSET + 4 + i * 4);
717 writel(card->status_address, mem + PDM_OFFSET + 20);
718 writel(PDM_OFFSET, mem);
719 iounmap(mem);
720
721 writel(0, card->plx + PLX_MAILBOX_5);
722
723 if (wanxl_puts_command(card, MBX1_CMD_ABORTJ)) {
724 printk(KERN_WARNING "wanXL %s: unable to Abort and Jump\n",
725 card_name(pdev));
726 wanxl_pci_remove_one(pdev);
727 return -ENODEV;
728 }
729
730 stat = 0;
731 timeout = jiffies + 5 * HZ;
732 do {
733 if ((stat = readl(card->plx + PLX_MAILBOX_5)) != 0)
734 break;
735 schedule();
736 }while (time_after(timeout, jiffies));
737
738 if (!stat) {
739 printk(KERN_WARNING "wanXL %s: timeout while initializing card"
740 "firmware\n", card_name(pdev));
741 wanxl_pci_remove_one(pdev);
742 return -ENODEV;
743 }
744
745 #if DETECT_RAM
746 ramsize = stat;
747 #endif
748
749 printk(KERN_INFO "wanXL %s: at 0x%X, %u KB of RAM at 0x%X, irq %u\n",
750 card_name(pdev), plx_phy, ramsize / 1024, mem_phy, pdev->irq);
751
752 /* Allocate IRQ */
753 if (request_irq(pdev->irq, wanxl_intr, SA_SHIRQ, "wanXL", card)) {
754 printk(KERN_WARNING "wanXL %s: could not allocate IRQ%i.\n",
755 card_name(pdev), pdev->irq);
756 wanxl_pci_remove_one(pdev);
757 return -EBUSY;
758 }
759 card->irq = pdev->irq;
760
761 for (i = 0; i < ports; i++) {
762 hdlc_device *hdlc;
763 port_t *port = &card->ports[i];
764 struct net_device *dev = alloc_hdlcdev(port);
765 if (!dev) {
766 printk(KERN_ERR "wanXL %s: unable to allocate"
767 " memory\n", card_name(pdev));
768 wanxl_pci_remove_one(pdev);
769 return -ENOMEM;
770 }
771
772 port->dev = dev;
773 hdlc = dev_to_hdlc(dev);
774 spin_lock_init(&port->lock);
775 SET_MODULE_OWNER(dev);
776 dev->tx_queue_len = 50;
777 dev->do_ioctl = wanxl_ioctl;
778 dev->open = wanxl_open;
779 dev->stop = wanxl_close;
780 hdlc->attach = wanxl_attach;
781 hdlc->xmit = wanxl_xmit;
782 dev->get_stats = wanxl_get_stats;
783 port->card = card;
784 port->node = i;
785 get_status(port)->clocking = CLOCK_EXT;
786 if (register_hdlc_device(dev)) {
787 printk(KERN_ERR "wanXL %s: unable to register hdlc"
788 " device\n", card_name(pdev));
789 free_netdev(dev);
790 wanxl_pci_remove_one(pdev);
791 return -ENOBUFS;
792 }
793 card->n_ports++;
794 }
795
796 printk(KERN_INFO "wanXL %s: port", card_name(pdev));
797 for (i = 0; i < ports; i++)
798 printk("%s #%i: %s", i ? "," : "", i,
799 card->ports[i].dev->name);
800 printk("\n");
801
802 for (i = 0; i < ports; i++)
803 wanxl_cable_intr(&card->ports[i]); /* get carrier status etc.*/
804
805 return 0;
806 }
807
808 static struct pci_device_id wanxl_pci_tbl[] __devinitdata = {
809 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL100, PCI_ANY_ID,
810 PCI_ANY_ID, 0, 0, 0 },
811 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL200, PCI_ANY_ID,
812 PCI_ANY_ID, 0, 0, 0 },
813 { PCI_VENDOR_ID_SBE, PCI_DEVICE_ID_SBE_WANXL400, PCI_ANY_ID,
814 PCI_ANY_ID, 0, 0, 0 },
815 { 0, }
816 };
817
818
819 static struct pci_driver wanxl_pci_driver = {
820 .name = "wanXL",
821 .id_table = wanxl_pci_tbl,
822 .probe = wanxl_pci_init_one,
823 .remove = wanxl_pci_remove_one,
824 };
825
826
827 static int __init wanxl_init_module(void)
828 {
829 #ifdef MODULE
830 printk(KERN_INFO "%s\n", version);
831 #endif
832 return pci_module_init(&wanxl_pci_driver);
833 }
834
835 static void __exit wanxl_cleanup_module(void)
836 {
837 pci_unregister_driver(&wanxl_pci_driver);
838 }
839
840
841 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
842 MODULE_DESCRIPTION("SBE Inc. wanXL serial port driver");
843 MODULE_LICENSE("GPL v2");
844 MODULE_DEVICE_TABLE(pci, wanxl_pci_tbl);
845
846 module_init(wanxl_init_module);
847 module_exit(wanxl_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz