drivers/net/wan/c101.c

   1 /*
   2  * Moxa C101 synchronous serial card driver for Linux
   3  *
   4  * Copyright (C) 2000-2003 Krzysztof Halasa <khc@pm.waw.pl>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of version 2 of the GNU General Public License
   8  * as published by the Free Software Foundation.
   9  *
  10  * For information see http://hq.pm.waw.pl/hdlc/
  11  *
  12  * Sources of information:
  13  *    Hitachi HD64570 SCA User's Manual
  14  *    Moxa C101 User's Manual
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/slab.h>
  20 #include <linux/types.h>
  21 #include <linux/string.h>
  22 #include <linux/errno.h>
  23 #include <linux/init.h>
  24 #include <linux/moduleparam.h>
  25 #include <linux/netdevice.h>
  26 #include <linux/hdlc.h>
  27 #include <linux/delay.h>
  28 #include <asm/io.h>
  29
  30 #include "hd64570.h"
  31
  32
  33 static const char* version = "Moxa C101 driver version: 1.15";
  34 static const char* devname = "C101";
  35
  36 #undef DEBUG_PKT
  37 #define DEBUG_RINGS
  38
  39 #define C101_PAGE 0x1D00
  40 #define C101_DTR 0x1E00
  41 #define C101_SCA 0x1F00
  42 #define C101_WINDOW_SIZE 0x2000
  43 #define C101_MAPPED_RAM_SIZE 0x4000
  44
  45 #define RAM_SIZE (256 * 1024)
  46 #define TX_RING_BUFFERS 10
  47 #define RX_RING_BUFFERS ((RAM_SIZE - C101_WINDOW_SIZE) /                \
  48                          (sizeof(pkt_desc) + HDLC_MAX_MRU) - TX_RING_BUFFERS)
  49
  50 #define CLOCK_BASE 9830400      /* 9.8304 MHz */
  51 #define PAGE0_ALWAYS_MAPPED
  52
  53 static char *hw;                /* pointer to hw=xxx command line string */
  54
  55
  56 typedef struct card_s {
  57         struct net_device *dev;
  58         spinlock_t lock;        /* TX lock */
  59         u8 *win0base;           /* ISA window base address */
  60         u32 phy_winbase;        /* ISA physical base address */
  61         sync_serial_settings settings;
  62         int rxpart;             /* partial frame received, next frame invalid*/
  63         unsigned short encoding;
  64         unsigned short parity;
  65         u16 rx_ring_buffers;    /* number of buffers in a ring */
  66         u16 tx_ring_buffers;
  67         u16 buff_offset;        /* offset of first buffer of first channel */
  68         u16 rxin;               /* rx ring buffer 'in' pointer */
  69         u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  70         u16 txlast;
  71         u8 rxs, txs, tmc;       /* SCA registers */
  72         u8 irq;                 /* IRQ (3-15) */
  73         u8 page;
  74
  75         struct card_s *next_card;
  76 }card_t;
  77
  78 typedef card_t port_t;
  79
  80 static card_t *first_card;
  81 static card_t **new_card = &first_card;
  82
  83
  84 #define sca_in(reg, card)          readb((card)->win0base + C101_SCA + (reg))
  85 #define sca_out(value, reg, card)  writeb(value, (card)->win0base + C101_SCA + (reg))
  86 #define sca_inw(reg, card)         readw((card)->win0base + C101_SCA + (reg))
  87
  88 /* EDA address register must be set in EDAL, EDAH order - 8 bit ISA bus */
  89 #define sca_outw(value, reg, card) do { \
  90         writeb(value & 0xFF, (card)->win0base + C101_SCA + (reg)); \
  91         writeb((value >> 8 ) & 0xFF, (card)->win0base + C101_SCA + (reg+1));\
  92 } while(0)
  93
  94 #define port_to_card(port)         (port)
  95 #define log_node(port)             (0)
  96 #define phy_node(port)             (0)
  97 #define winsize(card)              (C101_WINDOW_SIZE)
  98 #define win0base(card)             ((card)->win0base)
  99 #define winbase(card)              ((card)->win0base + 0x2000)
 100 #define get_port(card, port)       (card)
 101 static void sca_msci_intr(port_t *port);
 102
 103
 104 static inline u8 sca_get_page(card_t *card)
 105 {
 106         return card->page;
 107 }
 108
 109 static inline void openwin(card_t *card, u8 page)
 110 {
 111         card->page = page;
 112         writeb(page, card->win0base + C101_PAGE);
 113 }
 114
 115
 116 #define close_windows(card) {} /* no hardware support */
 117
 118
 119 #include "hd6457x.c"
 120
 121
 122 static void sca_msci_intr(port_t *port)
 123 {
 124         struct net_device *dev = port_to_dev(port);
 125         card_t* card = port_to_card(port);
 126         u8 stat = sca_in(MSCI1_OFFSET + ST1, card); /* read MSCI ST1 status */
 127
 128         /* Reset MSCI TX underrun status bit */
 129         sca_out(stat & ST1_UDRN, MSCI0_OFFSET + ST1, card);
 130
 131         if (stat & ST1_UDRN) {
 132                 struct net_device_stats *stats = hdlc_stats(dev);
 133                 stats->tx_errors++; /* TX Underrun error detected */
 134                 stats->tx_fifo_errors++;
 135         }
 136
 137         /* Reset MSCI CDCD status bit - uses ch#2 DCD input */
 138         sca_out(stat & ST1_CDCD, MSCI1_OFFSET + ST1, card);
 139
 140         if (stat & ST1_CDCD)
 141                 hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD),
 142                                  dev);
 143 }
 144
 145
 146 static void c101_set_iface(port_t *port)
 147 {
 148         u8 rxs = port->rxs & CLK_BRG_MASK;
 149         u8 txs = port->txs & CLK_BRG_MASK;
 150
 151         switch(port->settings.clock_type) {
 152         case CLOCK_INT:
 153                 rxs |= CLK_BRG_RX; /* TX clock */
 154                 txs |= CLK_RXCLK_TX; /* BRG output */
 155                 break;
 156
 157         case CLOCK_TXINT:
 158                 rxs |= CLK_LINE_RX; /* RXC input */
 159                 txs |= CLK_BRG_TX; /* BRG output */
 160                 break;
 161
 162         case CLOCK_TXFROMRX:
 163                 rxs |= CLK_LINE_RX; /* RXC input */
 164                 txs |= CLK_RXCLK_TX; /* RX clock */
 165                 break;
 166
 167         default:        /* EXTernal clock */
 168                 rxs |= CLK_LINE_RX; /* RXC input */
 169                 txs |= CLK_LINE_TX; /* TXC input */
 170         }
 171
 172         port->rxs = rxs;
 173         port->txs = txs;
 174         sca_out(rxs, MSCI1_OFFSET + RXS, port);
 175         sca_out(txs, MSCI1_OFFSET + TXS, port);
 176         sca_set_port(port);
 177 }
 178
 179
 180 static int c101_open(struct net_device *dev)
 181 {
 182         port_t *port = dev_to_port(dev);
 183         int result;
 184
 185         result = hdlc_open(dev);
 186         if (result)
 187                 return result;
 188
 189         writeb(1, port->win0base + C101_DTR);
 190         sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */
 191         sca_open(dev);
 192         /* DCD is connected to port 2 !@#$%^& - disable MSCI0 CDCD interrupt */
 193         sca_out(IE1_UDRN, MSCI0_OFFSET + IE1, port);
 194         sca_out(IE0_TXINT, MSCI0_OFFSET + IE0, port);
 195
 196         hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, port) & ST3_DCD), dev);
 197         printk(KERN_DEBUG "0x%X\n", sca_in(MSCI1_OFFSET + ST3, port));
 198
 199         /* enable MSCI1 CDCD interrupt */
 200         sca_out(IE1_CDCD, MSCI1_OFFSET + IE1, port);
 201         sca_out(IE0_RXINTA, MSCI1_OFFSET + IE0, port);
 202         sca_out(0x48, IER0, port); /* TXINT #0 and RXINT #1 */
 203         c101_set_iface(port);
 204         return 0;
 205 }
 206
 207
 208 static int c101_close(struct net_device *dev)
 209 {
 210         port_t *port = dev_to_port(dev);
 211
 212         sca_close(dev);
 213         writeb(0, port->win0base + C101_DTR);
 214         sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
 215         hdlc_close(dev);
 216         return 0;
 217 }
 218
 219
 220 static int c101_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 221 {
 222         const size_t size = sizeof(sync_serial_settings);
 223         sync_serial_settings new_line;
 224         sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 225         port_t *port = dev_to_port(dev);
 226
 227 #ifdef DEBUG_RINGS
 228         if (cmd == SIOCDEVPRIVATE) {
 229                 sca_dump_rings(dev);
 230                 printk(KERN_DEBUG "MSCI1: ST: %02x %02x %02x %02x\n",
 231                        sca_in(MSCI1_OFFSET + ST0, port),
 232                        sca_in(MSCI1_OFFSET + ST1, port),
 233                        sca_in(MSCI1_OFFSET + ST2, port),
 234                        sca_in(MSCI1_OFFSET + ST3, port));
 235                 return 0;
 236         }
 237 #endif
 238         if (cmd != SIOCWANDEV)
 239                 return hdlc_ioctl(dev, ifr, cmd);
 240
 241         switch(ifr->ifr_settings.type) {
 242         case IF_GET_IFACE:
 243                 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
 244                 if (ifr->ifr_settings.size < size) {
 245                         ifr->ifr_settings.size = size; /* data size wanted */
 246                         return -ENOBUFS;
 247                 }
 248                 if (copy_to_user(line, &port->settings, size))
 249                         return -EFAULT;
 250                 return 0;
 251
 252         case IF_IFACE_SYNC_SERIAL:
 253                 if(!capable(CAP_NET_ADMIN))
 254                         return -EPERM;
 255
 256                 if (copy_from_user(&new_line, line, size))
 257                         return -EFAULT;
 258
 259                 if (new_line.clock_type != CLOCK_EXT &&
 260                     new_line.clock_type != CLOCK_TXFROMRX &&
 261                     new_line.clock_type != CLOCK_INT &&
 262                     new_line.clock_type != CLOCK_TXINT)
 263                 return -EINVAL; /* No such clock setting */
 264
 265                 if (new_line.loopback != 0 && new_line.loopback != 1)
 266                         return -EINVAL;
 267
 268                 memcpy(&port->settings, &new_line, size); /* Update settings */
 269                 c101_set_iface(port);
 270                 return 0;
 271
 272         default:
 273                 return hdlc_ioctl(dev, ifr, cmd);
 274         }
 275 }
 276
 277
 278
 279 static void c101_destroy_card(card_t *card)
 280 {
 281         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 282
 283         if (card->irq)
 284                 free_irq(card->irq, card);
 285
 286         if (card->win0base) {
 287                 iounmap(card->win0base);
 288                 release_mem_region(card->phy_winbase, C101_MAPPED_RAM_SIZE);
 289         }
 290
 291         free_netdev(card->dev);
 292
 293         kfree(card);
 294 }
 295
 296
 297
 298 static int __init c101_run(unsigned long irq, unsigned long winbase)
 299 {
 300         struct net_device *dev;
 301         hdlc_device *hdlc;
 302         card_t *card;
 303         int result;
 304
 305         if (irq<3 || irq>15 || irq == 6) /* FIXME */ {
 306                 printk(KERN_ERR "c101: invalid IRQ value\n");
 307                 return -ENODEV;
 308         }
 309
 310         if (winbase < 0xC0000 || winbase > 0xDFFFF || (winbase & 0x3FFF) !=0) {
 311                 printk(KERN_ERR "c101: invalid RAM value\n");
 312                 return -ENODEV;
 313         }
 314
 315         card = kmalloc(sizeof(card_t), GFP_KERNEL);
 316         if (card == NULL) {
 317                 printk(KERN_ERR "c101: unable to allocate memory\n");
 318                 return -ENOBUFS;
 319         }
 320         memset(card, 0, sizeof(card_t));
 321
 322         card->dev = alloc_hdlcdev(card);
 323         if (!card->dev) {
 324                 printk(KERN_ERR "c101: unable to allocate memory\n");
 325                 kfree(card);
 326                 return -ENOBUFS;
 327         }
 328
 329         if (request_irq(irq, sca_intr, 0, devname, card)) {
 330                 printk(KERN_ERR "c101: could not allocate IRQ\n");
 331                 c101_destroy_card(card);
 332                 return(-EBUSY);
 333         }
 334         card->irq = irq;
 335
 336         if (!request_mem_region(winbase, C101_MAPPED_RAM_SIZE, devname)) {
 337                 printk(KERN_ERR "c101: could not request RAM window\n");
 338                 c101_destroy_card(card);
 339                 return(-EBUSY);
 340         }
 341         card->phy_winbase = winbase;
 342         card->win0base = ioremap(winbase, C101_MAPPED_RAM_SIZE);
 343         if (!card->win0base) {
 344                 printk(KERN_ERR "c101: could not map I/O address\n");
 345                 c101_destroy_card(card);
 346                 return -EBUSY;
 347         }
 348
 349         card->tx_ring_buffers = TX_RING_BUFFERS;
 350         card->rx_ring_buffers = RX_RING_BUFFERS;
 351         card->buff_offset = C101_WINDOW_SIZE; /* Bytes 1D00-1FFF reserved */
 352
 353         readb(card->win0base + C101_PAGE); /* Resets SCA? */
 354         udelay(100);
 355         writeb(0, card->win0base + C101_PAGE);
 356         writeb(0, card->win0base + C101_DTR); /* Power-up for RAM? */
 357
 358         sca_init(card, 0);
 359
 360         dev = port_to_dev(card);
 361         hdlc = dev_to_hdlc(dev);
 362
 363         spin_lock_init(&card->lock);
 364         SET_MODULE_OWNER(dev);
 365         dev->irq = irq;
 366         dev->mem_start = winbase;
 367         dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;
 368         dev->tx_queue_len = 50;
 369         dev->do_ioctl = c101_ioctl;
 370         dev->open = c101_open;
 371         dev->stop = c101_close;
 372         hdlc->attach = sca_attach;
 373         hdlc->xmit = sca_xmit;
 374         card->settings.clock_type = CLOCK_EXT;
 375
 376         result = register_hdlc_device(dev);
 377         if (result) {
 378                 printk(KERN_WARNING "c101: unable to register hdlc device\n");
 379                 c101_destroy_card(card);
 380                 return result;
 381         }
 382
 383         sca_init_sync_port(card); /* Set up C101 memory */
 384         hdlc_set_carrier(!(sca_in(MSCI1_OFFSET + ST3, card) & ST3_DCD), dev);
 385
 386         printk(KERN_INFO "%s: Moxa C101 on IRQ%u,"
 387                " using %u TX + %u RX packets rings\n",
 388                dev->name, card->irq,
 389                card->tx_ring_buffers, card->rx_ring_buffers);
 390
 391         *new_card = card;
 392         new_card = &card->next_card;
 393         return 0;
 394 }
 395
 396
 397
 398 static int __init c101_init(void)
 399 {
 400         if (hw == NULL) {
 401 #ifdef MODULE
 402                 printk(KERN_INFO "c101: no card initialized\n");
 403 #endif
 404                 return -ENOSYS; /* no parameters specified, abort */
 405         }
 406
 407         printk(KERN_INFO "%s\n", version);
 408
 409         do {
 410                 unsigned long irq, ram;
 411
 412                 irq = simple_strtoul(hw, &hw, 0);
 413
 414                 if (*hw++ != ',')
 415                         break;
 416                 ram = simple_strtoul(hw, &hw, 0);
 417
 418                 if (*hw == ':' || *hw == '\x0')
 419                         c101_run(irq, ram);
 420
 421                 if (*hw == '\x0')
 422                         return first_card ? 0 : -ENOSYS;
 423         }while(*hw++ == ':');
 424
 425         printk(KERN_ERR "c101: invalid hardware parameters\n");
 426         return first_card ? 0 : -ENOSYS;
 427 }
 428
 429
 430 static void __exit c101_cleanup(void)
 431 {
 432         card_t *card = first_card;
 433
 434         while (card) {
 435                 card_t *ptr = card;
 436                 card = card->next_card;
 437                 unregister_hdlc_device(port_to_dev(ptr));
 438                 c101_destroy_card(ptr);
 439         }
 440 }
 441
 442
 443 module_init(c101_init);
 444 module_exit(c101_cleanup);
 445
 446 MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 447 MODULE_DESCRIPTION("Moxa C101 serial port driver");
 448 MODULE_LICENSE("GPL v2");
 449 module_param(hw, charp, 0444);  /* hw=irq,ram:irq,... */