drivers/net/pcmcia/nmclan_cs.c

   1 /* ----------------------------------------------------------------------------
   2 Linux PCMCIA ethernet adapter driver for the New Media Ethernet LAN.
   3   nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao
   4
   5   The Ethernet LAN uses the Advanced Micro Devices (AMD) Am79C940 Media
   6   Access Controller for Ethernet (MACE).  It is essentially the Am2150
   7   PCMCIA Ethernet card contained in the Am2150 Demo Kit.
   8
   9 Written by Roger C. Pao <rpao@paonet.org>
  10   Copyright 1995 Roger C. Pao
  11   Linux 2.5 cleanups Copyright Red Hat 2003
  12
  13   This software may be used and distributed according to the terms of
  14   the GNU General Public License.
  15
  16 Ported to Linux 1.3.* network driver environment by
  17   Matti Aarnio <mea@utu.fi>
  18
  19 References
  20
  21   Am2150 Technical Reference Manual, Revision 1.0, August 17, 1993
  22   Am79C940 (MACE) Data Sheet, 1994
  23   Am79C90 (C-LANCE) Data Sheet, 1994
  24   Linux PCMCIA Programmer's Guide v1.17
  25   /usr/src/linux/net/inet/dev.c, Linux kernel 1.2.8
  26
  27   Eric Mears, New Media Corporation
  28   Tom Pollard, New Media Corporation
  29   Dean Siasoyco, New Media Corporation
  30   Ken Lesniak, Silicon Graphics, Inc. <lesniak@boston.sgi.com>
  31   Donald Becker <becker@scyld.com>
  32   David Hinds <dahinds@users.sourceforge.net>
  33
  34   The Linux client driver is based on the 3c589_cs.c client driver by
  35   David Hinds.
  36
  37   The Linux network driver outline is based on the 3c589_cs.c driver,
  38   the 8390.c driver, and the example skeleton.c kernel code, which are
  39   by Donald Becker.
  40
  41   The Am2150 network driver hardware interface code is based on the
  42   OS/9000 driver for the New Media Ethernet LAN by Eric Mears.
  43
  44   Special thanks for testing and help in debugging this driver goes
  45   to Ken Lesniak.
  46
  47 -------------------------------------------------------------------------------
  48 Driver Notes and Issues
  49 -------------------------------------------------------------------------------
  50
  51 1. Developed on a Dell 320SLi
  52    PCMCIA Card Services 2.6.2
  53    Linux dell 1.2.10 #1 Thu Jun 29 20:23:41 PDT 1995 i386
  54
  55 2. rc.pcmcia may require loading pcmcia_core with io_speed=300:
  56    'insmod pcmcia_core.o io_speed=300'.
  57    This will avoid problems with fast systems which causes rx_framecnt
  58    to return random values.
  59
  60 3. If hot extraction does not work for you, use 'ifconfig eth0 down'
  61    before extraction.
  62
  63 4. There is a bad slow-down problem in this driver.
  64
  65 5. Future: Multicast processing.  In the meantime, do _not_ compile your
  66    kernel with multicast ip enabled.
  67
  68 -------------------------------------------------------------------------------
  69 History
  70 -------------------------------------------------------------------------------
  71 Log: nmclan_cs.c,v
  72  * 2.5.75-ac1 2003/07/11 Alan Cox <alan@redhat.com>
  73  * Fixed hang on card eject as we probe it
  74  * Cleaned up to use new style locking.
  75  *
  76  * Revision 0.16  1995/07/01  06:42:17  rpao
  77  * Bug fix: nmclan_reset() called CardServices incorrectly.
  78  *
  79  * Revision 0.15  1995/05/24  08:09:47  rpao
  80  * Re-implement MULTI_TX dev->tbusy handling.
  81  *
  82  * Revision 0.14  1995/05/23  03:19:30  rpao
  83  * Added, in nmclan_config(), "tuple.Attributes = 0;".
  84  * Modified MACE ID check to ignore chip revision level.
  85  * Avoid tx_free_frames race condition between _start_xmit and _interrupt.
  86  *
  87  * Revision 0.13  1995/05/18  05:56:34  rpao
  88  * Statistics changes.
  89  * Bug fix: nmclan_reset did not enable TX and RX: call restore_multicast_list.
  90  * Bug fix: mace_interrupt checks ~MACE_IMR_DEFAULT.  Fixes driver lockup.
  91  *
  92  * Revision 0.12  1995/05/14  00:12:23  rpao
  93  * Statistics overhaul.
  94  *
  95
  96 95/05/13 rpao   V0.10a
  97                 Bug fix: MACE statistics counters used wrong I/O ports.
  98                 Bug fix: mace_interrupt() needed to allow statistics to be
  99                 processed without RX or TX interrupts pending.
 100 95/05/11 rpao   V0.10
 101                 Multiple transmit request processing.
 102                 Modified statistics to use MACE counters where possible.
 103 95/05/10 rpao   V0.09 Bug fix: Must use IO_DATA_PATH_WIDTH_AUTO.
 104                 *Released
 105 95/05/10 rpao   V0.08
 106                 Bug fix: Make all non-exported functions private by using
 107                 static keyword.
 108                 Bug fix: Test IntrCnt _before_ reading MACE_IR.
 109 95/05/10 rpao   V0.07 Statistics.
 110 95/05/09 rpao   V0.06 Fix rx_framecnt problem by addition of PCIC wait states.
 111
 112 ---------------------------------------------------------------------------- */
 113
 114 #define DRV_NAME        "nmclan_cs"
 115 #define DRV_VERSION     "0.16"
 116
 117
 118 /* ----------------------------------------------------------------------------
 119 Conditional Compilation Options
 120 ---------------------------------------------------------------------------- */
 121
 122 #define MULTI_TX                        0
 123 #define RESET_ON_TIMEOUT                1
 124 #define TX_INTERRUPTABLE                1
 125 #define RESET_XILINX                    0
 126
 127 /* ----------------------------------------------------------------------------
 128 Include Files
 129 ---------------------------------------------------------------------------- */
 130
 131 #include <linux/module.h>
 132 #include <linux/kernel.h>
 133 #include <linux/init.h>
 134 #include <linux/ptrace.h>
 135 #include <linux/slab.h>
 136 #include <linux/string.h>
 137 #include <linux/timer.h>
 138 #include <linux/interrupt.h>
 139 #include <linux/in.h>
 140 #include <linux/delay.h>
 141 #include <linux/ethtool.h>
 142 #include <linux/netdevice.h>
 143 #include <linux/etherdevice.h>
 144 #include <linux/skbuff.h>
 145 #include <linux/if_arp.h>
 146 #include <linux/ioport.h>
 147
 148 #include <pcmcia/version.h>
 149 #include <pcmcia/cs_types.h>
 150 #include <pcmcia/cs.h>
 151 #include <pcmcia/cisreg.h>
 152 #include <pcmcia/cistpl.h>
 153 #include <pcmcia/ds.h>
 154
 155 #include <asm/uaccess.h>
 156 #include <asm/io.h>
 157 #include <asm/system.h>
 158 #include <asm/bitops.h>
 159
 160 /* ----------------------------------------------------------------------------
 161 Defines
 162 ---------------------------------------------------------------------------- */
 163
 164 #define ETHER_ADDR_LEN                  ETH_ALEN
 165                                         /* 6 bytes in an Ethernet Address */
 166 #define MACE_LADRF_LEN                  8
 167                                         /* 8 bytes in Logical Address Filter */
 168
 169 /* Loop Control Defines */
 170 #define MACE_MAX_IR_ITERATIONS          10
 171 #define MACE_MAX_RX_ITERATIONS          12
 172         /*
 173         TBD: Dean brought this up, and I assumed the hardware would
 174         handle it:
 175
 176         If MACE_MAX_RX_ITERATIONS is > 1, rx_framecnt may still be
 177         non-zero when the isr exits.  We may not get another interrupt
 178         to process the remaining packets for some time.
 179         */
 180
 181 /*
 182 The Am2150 has a Xilinx XC3042 field programmable gate array (FPGA)
 183 which manages the interface between the MACE and the PCMCIA bus.  It
 184 also includes buffer management for the 32K x 8 SRAM to control up to
 185 four transmit and 12 receive frames at a time.
 186 */
 187 #define AM2150_MAX_TX_FRAMES            4
 188 #define AM2150_MAX_RX_FRAMES            12
 189
 190 /* Am2150 Ethernet Card I/O Mapping */
 191 #define AM2150_RCV                      0x00
 192 #define AM2150_XMT                      0x04
 193 #define AM2150_XMT_SKIP                 0x09
 194 #define AM2150_RCV_NEXT                 0x0A
 195 #define AM2150_RCV_FRAME_COUNT          0x0B
 196 #define AM2150_MACE_BANK                0x0C
 197 #define AM2150_MACE_BASE                0x10
 198
 199 /* MACE Registers */
 200 #define MACE_RCVFIFO                    0
 201 #define MACE_XMTFIFO                    1
 202 #define MACE_XMTFC                      2
 203 #define MACE_XMTFS                      3
 204 #define MACE_XMTRC                      4
 205 #define MACE_RCVFC                      5
 206 #define MACE_RCVFS                      6
 207 #define MACE_FIFOFC                     7
 208 #define MACE_IR                         8
 209 #define MACE_IMR                        9
 210 #define MACE_PR                         10
 211 #define MACE_BIUCC                      11
 212 #define MACE_FIFOCC                     12
 213 #define MACE_MACCC                      13
 214 #define MACE_PLSCC                      14
 215 #define MACE_PHYCC                      15
 216 #define MACE_CHIPIDL                    16
 217 #define MACE_CHIPIDH                    17
 218 #define MACE_IAC                        18
 219 /* Reserved */
 220 #define MACE_LADRF                      20
 221 #define MACE_PADR                       21
 222 /* Reserved */
 223 /* Reserved */
 224 #define MACE_MPC                        24
 225 /* Reserved */
 226 #define MACE_RNTPC                      26
 227 #define MACE_RCVCC                      27
 228 /* Reserved */
 229 #define MACE_UTR                        29
 230 #define MACE_RTR1                       30
 231 #define MACE_RTR2                       31
 232
 233 /* MACE Bit Masks */
 234 #define MACE_XMTRC_EXDEF                0x80
 235 #define MACE_XMTRC_XMTRC                0x0F
 236
 237 #define MACE_XMTFS_XMTSV                0x80
 238 #define MACE_XMTFS_UFLO                 0x40
 239 #define MACE_XMTFS_LCOL                 0x20
 240 #define MACE_XMTFS_MORE                 0x10
 241 #define MACE_XMTFS_ONE                  0x08
 242 #define MACE_XMTFS_DEFER                0x04
 243 #define MACE_XMTFS_LCAR                 0x02
 244 #define MACE_XMTFS_RTRY                 0x01
 245
 246 #define MACE_RCVFS_RCVSTS               0xF000
 247 #define MACE_RCVFS_OFLO                 0x8000
 248 #define MACE_RCVFS_CLSN                 0x4000
 249 #define MACE_RCVFS_FRAM                 0x2000
 250 #define MACE_RCVFS_FCS                  0x1000
 251
 252 #define MACE_FIFOFC_RCVFC               0xF0
 253 #define MACE_FIFOFC_XMTFC               0x0F
 254
 255 #define MACE_IR_JAB                     0x80
 256 #define MACE_IR_BABL                    0x40
 257 #define MACE_IR_CERR                    0x20
 258 #define MACE_IR_RCVCCO                  0x10
 259 #define MACE_IR_RNTPCO                  0x08
 260 #define MACE_IR_MPCO                    0x04
 261 #define MACE_IR_RCVINT                  0x02
 262 #define MACE_IR_XMTINT                  0x01
 263
 264 #define MACE_MACCC_PROM                 0x80
 265 #define MACE_MACCC_DXMT2PD              0x40
 266 #define MACE_MACCC_EMBA                 0x20
 267 #define MACE_MACCC_RESERVED             0x10
 268 #define MACE_MACCC_DRCVPA               0x08
 269 #define MACE_MACCC_DRCVBC               0x04
 270 #define MACE_MACCC_ENXMT                0x02
 271 #define MACE_MACCC_ENRCV                0x01
 272
 273 #define MACE_PHYCC_LNKFL                0x80
 274 #define MACE_PHYCC_DLNKTST              0x40
 275 #define MACE_PHYCC_REVPOL               0x20
 276 #define MACE_PHYCC_DAPC                 0x10
 277 #define MACE_PHYCC_LRT                  0x08
 278 #define MACE_PHYCC_ASEL                 0x04
 279 #define MACE_PHYCC_RWAKE                0x02
 280 #define MACE_PHYCC_AWAKE                0x01
 281
 282 #define MACE_IAC_ADDRCHG                0x80
 283 #define MACE_IAC_PHYADDR                0x04
 284 #define MACE_IAC_LOGADDR                0x02
 285
 286 #define MACE_UTR_RTRE                   0x80
 287 #define MACE_UTR_RTRD                   0x40
 288 #define MACE_UTR_RPA                    0x20
 289 #define MACE_UTR_FCOLL                  0x10
 290 #define MACE_UTR_RCVFCSE                0x08
 291 #define MACE_UTR_LOOP_INCL_MENDEC       0x06
 292 #define MACE_UTR_LOOP_NO_MENDEC         0x04
 293 #define MACE_UTR_LOOP_EXTERNAL          0x02
 294 #define MACE_UTR_LOOP_NONE              0x00
 295 #define MACE_UTR_RESERVED               0x01
 296
 297 /* Switch MACE register bank (only 0 and 1 are valid) */
 298 #define MACEBANK(win_num) outb((win_num), ioaddr + AM2150_MACE_BANK)
 299
 300 #define MACE_IMR_DEFAULT \
 301   (0xFF - \
 302     ( \
 303       MACE_IR_CERR | \
 304       MACE_IR_RCVCCO | \
 305       MACE_IR_RNTPCO | \
 306       MACE_IR_MPCO | \
 307       MACE_IR_RCVINT | \
 308       MACE_IR_XMTINT \
 309     ) \
 310   )
 311 #undef MACE_IMR_DEFAULT
 312 #define MACE_IMR_DEFAULT 0x00 /* New statistics handling: grab everything */
 313
 314 #define TX_TIMEOUT              ((400*HZ)/1000)
 315
 316 /* ----------------------------------------------------------------------------
 317 Type Definitions
 318 ---------------------------------------------------------------------------- */
 319
 320 typedef struct _mace_statistics {
 321     /* MACE_XMTFS */
 322     int xmtsv;
 323     int uflo;
 324     int lcol;
 325     int more;
 326     int one;
 327     int defer;
 328     int lcar;
 329     int rtry;
 330
 331     /* MACE_XMTRC */
 332     int exdef;
 333     int xmtrc;
 334
 335     /* RFS1--Receive Status (RCVSTS) */
 336     int oflo;
 337     int clsn;
 338     int fram;
 339     int fcs;
 340
 341     /* RFS2--Runt Packet Count (RNTPC) */
 342     int rfs_rntpc;
 343
 344     /* RFS3--Receive Collision Count (RCVCC) */
 345     int rfs_rcvcc;
 346
 347     /* MACE_IR */
 348     int jab;
 349     int babl;
 350     int cerr;
 351     int rcvcco;
 352     int rntpco;
 353     int mpco;
 354
 355     /* MACE_MPC */
 356     int mpc;
 357
 358     /* MACE_RNTPC */
 359     int rntpc;
 360
 361     /* MACE_RCVCC */
 362     int rcvcc;
 363 } mace_statistics;
 364
 365 typedef struct _mace_private {
 366     dev_link_t link;
 367     dev_node_t node;
 368     struct net_device_stats linux_stats; /* Linux statistics counters */
 369     mace_statistics mace_stats; /* MACE chip statistics counters */
 370
 371     /* restore_multicast_list() state variables */
 372     int multicast_ladrf[MACE_LADRF_LEN]; /* Logical address filter */
 373     int multicast_num_addrs;
 374
 375     char tx_free_frames; /* Number of free transmit frame buffers */
 376     char tx_irq_disabled; /* MACE TX interrupt disabled */
 377
 378     spinlock_t bank_lock; /* Must be held if you step off bank 0 */
 379 } mace_private;
 380
 381 /* ----------------------------------------------------------------------------
 382 Private Global Variables
 383 ---------------------------------------------------------------------------- */
 384
 385 #ifdef PCMCIA_DEBUG
 386 static char rcsid[] =
 387 "nmclan_cs.c,v 0.16 1995/07/01 06:42:17 rpao Exp rpao";
 388 static char *version =
 389 DRV_NAME " " DRV_VERSION " (Roger C. Pao)";
 390 #endif
 391
 392 static dev_info_t dev_info="nmclan_cs";
 393 static dev_link_t *dev_list;
 394
 395 static char *if_names[]={
 396     "Auto", "10baseT", "BNC",
 397 };
 398
 399 /* ----------------------------------------------------------------------------
 400 Parameters
 401         These are the parameters that can be set during loading with
 402         'insmod'.
 403 ---------------------------------------------------------------------------- */
 404
 405 MODULE_DESCRIPTION("New Media PCMCIA ethernet driver");
 406 MODULE_LICENSE("GPL");
 407
 408 #define INT_MODULE_PARM(n, v) static int n = v; MODULE_PARM(n, "i")
 409
 410 static int irq_list[4] = { -1 };
 411 MODULE_PARM(irq_list, "1-4i");
 412
 413 /* 0=auto, 1=10baseT, 2 = 10base2, default=auto */
 414 INT_MODULE_PARM(if_port, 0);
 415 /* Bit map of interrupts to choose from */
 416 INT_MODULE_PARM(irq_mask, 0xdeb8);
 417
 418 #ifdef PCMCIA_DEBUG
 419 INT_MODULE_PARM(pc_debug, PCMCIA_DEBUG);
 420 #define DEBUG(n, args...) if (pc_debug>(n)) printk(KERN_DEBUG args)
 421 #else
 422 #define DEBUG(n, args...)
 423 #endif
 424
 425 /* ----------------------------------------------------------------------------
 426 Function Prototypes
 427 ---------------------------------------------------------------------------- */
 428
 429 static void nmclan_config(dev_link_t *link);
 430 static void nmclan_release(dev_link_t *link);
 431 static int nmclan_event(event_t event, int priority,
 432                         event_callback_args_t *args);
 433
 434 static void nmclan_reset(struct net_device *dev);
 435 static int mace_config(struct net_device *dev, struct ifmap *map);
 436 static int mace_open(struct net_device *dev);
 437 static int mace_close(struct net_device *dev);
 438 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev);
 439 static void mace_tx_timeout(struct net_device *dev);
 440 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs);
 441 static struct net_device_stats *mace_get_stats(struct net_device *dev);
 442 static int mace_rx(struct net_device *dev, unsigned char RxCnt);
 443 static void restore_multicast_list(struct net_device *dev);
 444 static void set_multicast_list(struct net_device *dev);
 445 static struct ethtool_ops netdev_ethtool_ops;
 446
 447
 448 static dev_link_t *nmclan_attach(void);
 449 static void nmclan_detach(dev_link_t *);
 450
 451 /* ----------------------------------------------------------------------------
 452 nmclan_attach
 453         Creates an "instance" of the driver, allocating local data
 454         structures for one device.  The device is registered with Card
 455         Services.
 456 ---------------------------------------------------------------------------- */
 457
 458 static dev_link_t *nmclan_attach(void)
 459 {
 460     mace_private *lp;
 461     dev_link_t *link;
 462     struct net_device *dev;
 463     client_reg_t client_reg;
 464     int i, ret;
 465
 466     DEBUG(0, "nmclan_attach()\n");
 467     DEBUG(1, "%s\n", rcsid);
 468
 469     /* Create new ethernet device */
 470     dev = alloc_etherdev(sizeof(mace_private));
 471     if (!dev)
 472         return NULL;
 473     lp = netdev_priv(dev);
 474     link = &lp->link;
 475     link->priv = dev;
 476
 477     spin_lock_init(&lp->bank_lock);
 478     link->io.NumPorts1 = 32;
 479     link->io.Attributes1 = IO_DATA_PATH_WIDTH_AUTO;
 480     link->io.IOAddrLines = 5;
 481     link->irq.Attributes = IRQ_TYPE_EXCLUSIVE | IRQ_HANDLE_PRESENT;
 482     link->irq.IRQInfo1 = IRQ_INFO2_VALID|IRQ_LEVEL_ID;
 483     if (irq_list[0] == -1)
 484         link->irq.IRQInfo2 = irq_mask;
 485     else
 486         for (i = 0; i < 4; i++)
 487             link->irq.IRQInfo2 |= 1 << irq_list[i];
 488     link->irq.Handler = &mace_interrupt;
 489     link->irq.Instance = dev;
 490     link->conf.Attributes = CONF_ENABLE_IRQ;
 491     link->conf.Vcc = 50;
 492     link->conf.IntType = INT_MEMORY_AND_IO;
 493     link->conf.ConfigIndex = 1;
 494     link->conf.Present = PRESENT_OPTION;
 495
 496     lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 497
 498     SET_MODULE_OWNER(dev);
 499     dev->hard_start_xmit = &mace_start_xmit;
 500     dev->set_config = &mace_config;
 501     dev->get_stats = &mace_get_stats;
 502     dev->set_multicast_list = &set_multicast_list;
 503     SET_ETHTOOL_OPS(dev, &netdev_ethtool_ops);
 504     dev->open = &mace_open;
 505     dev->stop = &mace_close;
 506 #ifdef HAVE_TX_TIMEOUT
 507     dev->tx_timeout = mace_tx_timeout;
 508     dev->watchdog_timeo = TX_TIMEOUT;
 509 #endif
 510
 511     /* Register with Card Services */
 512     link->next = dev_list;
 513     dev_list = link;
 514     client_reg.dev_info = &dev_info;
 515     client_reg.Attributes = INFO_IO_CLIENT | INFO_CARD_SHARE;
 516     client_reg.EventMask =
 517         CS_EVENT_CARD_INSERTION | CS_EVENT_CARD_REMOVAL |
 518         CS_EVENT_RESET_PHYSICAL | CS_EVENT_CARD_RESET |
 519         CS_EVENT_PM_SUSPEND | CS_EVENT_PM_RESUME;
 520     client_reg.event_handler = &nmclan_event;
 521     client_reg.Version = 0x0210;
 522     client_reg.event_callback_args.client_data = link;
 523     ret = pcmcia_register_client(&link->handle, &client_reg);
 524     if (ret != 0) {
 525         cs_error(link->handle, RegisterClient, ret);
 526         nmclan_detach(link);
 527         return NULL;
 528     }
 529
 530     return link;
 531 } /* nmclan_attach */
 532
 533 /* ----------------------------------------------------------------------------
 534 nmclan_detach
 535         This deletes a driver "instance".  The device is de-registered
 536         with Card Services.  If it has been released, all local data
 537         structures are freed.  Otherwise, the structures will be freed
 538         when the device is released.
 539 ---------------------------------------------------------------------------- */
 540
 541 static void nmclan_detach(dev_link_t *link)
 542 {
 543     struct net_device *dev = link->priv;
 544     dev_link_t **linkp;
 545
 546     DEBUG(0, "nmclan_detach(0x%p)\n", link);
 547
 548     /* Locate device structure */
 549     for (linkp = &dev_list; *linkp; linkp = &(*linkp)->next)
 550         if (*linkp == link) break;
 551     if (*linkp == NULL)
 552         return;
 553
 554     if (link->dev)
 555         unregister_netdev(dev);
 556
 557     if (link->state & DEV_CONFIG)
 558         nmclan_release(link);
 559
 560     if (link->handle)
 561         pcmcia_deregister_client(link->handle);
 562
 563     /* Unlink device structure, free bits */
 564     *linkp = link->next;
 565     free_netdev(dev);
 566 } /* nmclan_detach */
 567
 568 /* ----------------------------------------------------------------------------
 569 mace_read
 570         Reads a MACE register.  This is bank independent; however, the
 571         caller must ensure that this call is not interruptable.  We are
 572         assuming that during normal operation, the MACE is always in
 573         bank 0.
 574 ---------------------------------------------------------------------------- */
 575 static int mace_read(mace_private *lp, ioaddr_t ioaddr, int reg)
 576 {
 577   int data = 0xFF;
 578   unsigned long flags;
 579
 580   switch (reg >> 4) {
 581     case 0: /* register 0-15 */
 582       data = inb(ioaddr + AM2150_MACE_BASE + reg);
 583       break;
 584     case 1: /* register 16-31 */
 585       spin_lock_irqsave(&lp->bank_lock, flags);
 586       MACEBANK(1);
 587       data = inb(ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 588       MACEBANK(0);
 589       spin_unlock_irqrestore(&lp->bank_lock, flags);
 590       break;
 591   }
 592   return (data & 0xFF);
 593 } /* mace_read */
 594
 595 /* ----------------------------------------------------------------------------
 596 mace_write
 597         Writes to a MACE register.  This is bank independent; however,
 598         the caller must ensure that this call is not interruptable.  We
 599         are assuming that during normal operation, the MACE is always in
 600         bank 0.
 601 ---------------------------------------------------------------------------- */
 602 static void mace_write(mace_private *lp, ioaddr_t ioaddr, int reg, int data)
 603 {
 604   unsigned long flags;
 605
 606   switch (reg >> 4) {
 607     case 0: /* register 0-15 */
 608       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + reg);
 609       break;
 610     case 1: /* register 16-31 */
 611       spin_lock_irqsave(&lp->bank_lock, flags);
 612       MACEBANK(1);
 613       outb(data & 0xFF, ioaddr + AM2150_MACE_BASE + (reg & 0x0F));
 614       MACEBANK(0);
 615       spin_unlock_irqrestore(&lp->bank_lock, flags);
 616       break;
 617   }
 618 } /* mace_write */
 619
 620 /* ----------------------------------------------------------------------------
 621 mace_init
 622         Resets the MACE chip.
 623 ---------------------------------------------------------------------------- */
 624 static int mace_init(mace_private *lp, ioaddr_t ioaddr, char *enet_addr)
 625 {
 626   int i;
 627   int ct = 0;
 628
 629   /* MACE Software reset */
 630   mace_write(lp, ioaddr, MACE_BIUCC, 1);
 631   while (mace_read(lp, ioaddr, MACE_BIUCC) & 0x01) {
 632     /* Wait for reset bit to be cleared automatically after <= 200ns */;
 633     if(++ct > 500)
 634     {
 635         printk(KERN_ERR "mace: reset failed, card removed ?\n");
 636         return -1;
 637     }
 638     udelay(1);
 639   }
 640   mace_write(lp, ioaddr, MACE_BIUCC, 0);
 641
 642   /* The Am2150 requires that the MACE FIFOs operate in burst mode. */
 643   mace_write(lp, ioaddr, MACE_FIFOCC, 0x0F);
 644
 645   mace_write(lp,ioaddr, MACE_RCVFC, 0); /* Disable Auto Strip Receive */
 646   mace_write(lp, ioaddr, MACE_IMR, 0xFF); /* Disable all interrupts until _open */
 647
 648   /*
 649    * Bit 2-1 PORTSEL[1-0] Port Select.
 650    * 00 AUI/10Base-2
 651    * 01 10Base-T
 652    * 10 DAI Port (reserved in Am2150)
 653    * 11 GPSI
 654    * For this card, only the first two are valid.
 655    * So, PLSCC should be set to
 656    * 0x00 for 10Base-2
 657    * 0x02 for 10Base-T
 658    * Or just set ASEL in PHYCC below!
 659    */
 660   switch (if_port) {
 661     case 1:
 662       mace_write(lp, ioaddr, MACE_PLSCC, 0x02);
 663       break;
 664     case 2:
 665       mace_write(lp, ioaddr, MACE_PLSCC, 0x00);
 666       break;
 667     default:
 668       mace_write(lp, ioaddr, MACE_PHYCC, /* ASEL */ 4);
 669       /* ASEL Auto Select.  When set, the PORTSEL[1-0] bits are overridden,
 670          and the MACE device will automatically select the operating media
 671          interface port. */
 672       break;
 673   }
 674
 675   mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_PHYADDR);
 676   /* Poll ADDRCHG bit */
 677   ct = 0;
 678   while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
 679   {
 680         if(++ ct > 500)
 681         {
 682                 printk(KERN_ERR "mace: ADDRCHG timeout, card removed ?\n");
 683                 return -1;
 684         }
 685   }
 686   /* Set PADR register */
 687   for (i = 0; i < ETHER_ADDR_LEN; i++)
 688     mace_write(lp, ioaddr, MACE_PADR, enet_addr[i]);
 689
 690   /* MAC Configuration Control Register should be written last */
 691   /* Let set_multicast_list set this. */
 692   /* mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV); */
 693   mace_write(lp, ioaddr, MACE_MACCC, 0x00);
 694   return 0;
 695 } /* mace_init */
 696
 697 /* ----------------------------------------------------------------------------
 698 nmclan_config
 699         This routine is scheduled to run after a CARD_INSERTION event
 700         is received, to configure the PCMCIA socket, and to make the
 701         ethernet device available to the system.
 702 ---------------------------------------------------------------------------- */
 703
 704 #define CS_CHECK(fn, ret) \
 705   do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
 706
 707 static void nmclan_config(dev_link_t *link)
 708 {
 709   client_handle_t handle = link->handle;
 710   struct net_device *dev = link->priv;
 711   mace_private *lp = netdev_priv(dev);
 712   tuple_t tuple;
 713   cisparse_t parse;
 714   u_char buf[64];
 715   int i, last_ret, last_fn;
 716   ioaddr_t ioaddr;
 717
 718   DEBUG(0, "nmclan_config(0x%p)\n", link);
 719
 720   tuple.Attributes = 0;
 721   tuple.TupleData = buf;
 722   tuple.TupleDataMax = 64;
 723   tuple.TupleOffset = 0;
 724   tuple.DesiredTuple = CISTPL_CONFIG;
 725   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
 726   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
 727   CS_CHECK(ParseTuple, pcmcia_parse_tuple(handle, &tuple, &parse));
 728   link->conf.ConfigBase = parse.config.base;
 729
 730   /* Configure card */
 731   link->state |= DEV_CONFIG;
 732
 733   CS_CHECK(RequestIO, pcmcia_request_io(handle, &link->io));
 734   CS_CHECK(RequestIRQ, pcmcia_request_irq(handle, &link->irq));
 735   CS_CHECK(RequestConfiguration, pcmcia_request_configuration(handle, &link->conf));
 736   dev->irq = link->irq.AssignedIRQ;
 737   dev->base_addr = link->io.BasePort1;
 738
 739   ioaddr = dev->base_addr;
 740
 741   /* Read the ethernet address from the CIS. */
 742   tuple.DesiredTuple = 0x80 /* CISTPL_CFTABLE_ENTRY_MISC */;
 743   tuple.TupleData = buf;
 744   tuple.TupleDataMax = 64;
 745   tuple.TupleOffset = 0;
 746   CS_CHECK(GetFirstTuple, pcmcia_get_first_tuple(handle, &tuple));
 747   CS_CHECK(GetTupleData, pcmcia_get_tuple_data(handle, &tuple));
 748   memcpy(dev->dev_addr, tuple.TupleData, ETHER_ADDR_LEN);
 749
 750   /* Verify configuration by reading the MACE ID. */
 751   {
 752     char sig[2];
 753
 754     sig[0] = mace_read(lp, ioaddr, MACE_CHIPIDL);
 755     sig[1] = mace_read(lp, ioaddr, MACE_CHIPIDH);
 756     if ((sig[0] == 0x40) && ((sig[1] & 0x0F) == 0x09)) {
 757       DEBUG(0, "nmclan_cs configured: mace id=%x %x\n",
 758             sig[0], sig[1]);
 759     } else {
 760       printk(KERN_NOTICE "nmclan_cs: mace id not found: %x %x should"
 761              " be 0x40 0x?9\n", sig[0], sig[1]);
 762       link->state &= ~DEV_CONFIG_PENDING;
 763       return;
 764     }
 765   }
 766
 767   if(mace_init(lp, ioaddr, dev->dev_addr) == -1)
 768         goto failed;
 769
 770   /* The if_port symbol can be set when the module is loaded */
 771   if (if_port <= 2)
 772     dev->if_port = if_port;
 773   else
 774     printk(KERN_NOTICE "nmclan_cs: invalid if_port requested\n");
 775
 776   link->dev = &lp->node;
 777   link->state &= ~DEV_CONFIG_PENDING;
 778
 779   i = register_netdev(dev);
 780   if (i != 0) {
 781     printk(KERN_NOTICE "nmclan_cs: register_netdev() failed\n");
 782     link->dev = NULL;
 783     goto failed;
 784   }
 785
 786   strcpy(lp->node.dev_name, dev->name);
 787
 788   printk(KERN_INFO "%s: nmclan: port %#3lx, irq %d, %s port, hw_addr ",
 789          dev->name, dev->base_addr, dev->irq, if_names[dev->if_port]);
 790   for (i = 0; i < 6; i++)
 791       printk("%02X%s", dev->dev_addr[i], ((i<5) ? ":" : "\n"));
 792   return;
 793
 794 cs_failed:
 795     cs_error(link->handle, last_fn, last_ret);
 796 failed:
 797     nmclan_release(link);
 798     return;
 799
 800 } /* nmclan_config */
 801
 802 /* ----------------------------------------------------------------------------
 803 nmclan_release
 804         After a card is removed, nmclan_release() will unregister the
 805         net device, and release the PCMCIA configuration.  If the device
 806         is still open, this will be postponed until it is closed.
 807 ---------------------------------------------------------------------------- */
 808 static void nmclan_release(dev_link_t *link)
 809 {
 810
 811   DEBUG(0, "nmclan_release(0x%p)\n", link);
 812
 813   pcmcia_release_configuration(link->handle);
 814   pcmcia_release_io(link->handle, &link->io);
 815   pcmcia_release_irq(link->handle, &link->irq);
 816
 817   link->state &= ~DEV_CONFIG;
 818 }
 819
 820 /* ----------------------------------------------------------------------------
 821 nmclan_event
 822         The card status event handler.  Mostly, this schedules other
 823         stuff to run after an event is received.  A CARD_REMOVAL event
 824         also sets some flags to discourage the net drivers from trying
 825         to talk to the card any more.
 826 ---------------------------------------------------------------------------- */
 827 static int nmclan_event(event_t event, int priority,
 828                        event_callback_args_t *args)
 829 {
 830   dev_link_t *link = args->client_data;
 831   struct net_device *dev = link->priv;
 832
 833   DEBUG(1, "nmclan_event(0x%06x)\n", event);
 834
 835   switch (event) {
 836     case CS_EVENT_CARD_REMOVAL:
 837       link->state &= ~DEV_PRESENT;
 838       if (link->state & DEV_CONFIG)
 839         netif_device_detach(dev);
 840       break;
 841     case CS_EVENT_CARD_INSERTION:
 842       link->state |= DEV_PRESENT | DEV_CONFIG_PENDING;
 843       nmclan_config(link);
 844       break;
 845     case CS_EVENT_PM_SUSPEND:
 846       link->state |= DEV_SUSPEND;
 847       /* Fall through... */
 848     case CS_EVENT_RESET_PHYSICAL:
 849       if (link->state & DEV_CONFIG) {
 850         if (link->open)
 851           netif_device_detach(dev);
 852         pcmcia_release_configuration(link->handle);
 853       }
 854       break;
 855     case CS_EVENT_PM_RESUME:
 856       link->state &= ~DEV_SUSPEND;
 857       /* Fall through... */
 858     case CS_EVENT_CARD_RESET:
 859       if (link->state & DEV_CONFIG) {
 860         pcmcia_request_configuration(link->handle, &link->conf);
 861         if (link->open) {
 862           nmclan_reset(dev);
 863           netif_device_attach(dev);
 864         }
 865       }
 866       break;
 867     case CS_EVENT_RESET_REQUEST:
 868       return 1;
 869       break;
 870   }
 871   return 0;
 872 } /* nmclan_event */
 873
 874 /* ----------------------------------------------------------------------------
 875 nmclan_reset
 876         Reset and restore all of the Xilinx and MACE registers.
 877 ---------------------------------------------------------------------------- */
 878 static void nmclan_reset(struct net_device *dev)
 879 {
 880   mace_private *lp = netdev_priv(dev);
 881
 882 #if RESET_XILINX
 883   dev_link_t *link = &lp->link;
 884   conf_reg_t reg;
 885   u_long OrigCorValue;
 886
 887   /* Save original COR value */
 888   reg.Function = 0;
 889   reg.Action = CS_READ;
 890   reg.Offset = CISREG_COR;
 891   reg.Value = 0;
 892   pcmcia_access_configuration_register(link->handle, &reg);
 893   OrigCorValue = reg.Value;
 894
 895   /* Reset Xilinx */
 896   reg.Action = CS_WRITE;
 897   reg.Offset = CISREG_COR;
 898   DEBUG(1, "nmclan_reset: OrigCorValue=0x%lX, resetting...\n",
 899         OrigCorValue);
 900   reg.Value = COR_SOFT_RESET;
 901   pcmcia_access_configuration_register(link->handle, &reg);
 902   /* Need to wait for 20 ms for PCMCIA to finish reset. */
 903
 904   /* Restore original COR configuration index */
 905   reg.Value = COR_LEVEL_REQ | (OrigCorValue & COR_CONFIG_MASK);
 906   pcmcia_access_configuration_register(link->handle, &reg);
 907   /* Xilinx is now completely reset along with the MACE chip. */
 908   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 909
 910 #endif /* #if RESET_XILINX */
 911
 912   /* Xilinx is now completely reset along with the MACE chip. */
 913   lp->tx_free_frames=AM2150_MAX_TX_FRAMES;
 914
 915   /* Reinitialize the MACE chip for operation. */
 916   mace_init(lp, dev->base_addr, dev->dev_addr);
 917   mace_write(lp, dev->base_addr, MACE_IMR, MACE_IMR_DEFAULT);
 918
 919   /* Restore the multicast list and enable TX and RX. */
 920   restore_multicast_list(dev);
 921 } /* nmclan_reset */
 922
 923 /* ----------------------------------------------------------------------------
 924 mace_config
 925         [Someone tell me what this is supposed to do?  Is if_port a defined
 926         standard?  If so, there should be defines to indicate 1=10Base-T,
 927         2=10Base-2, etc. including limited automatic detection.]
 928 ---------------------------------------------------------------------------- */
 929 static int mace_config(struct net_device *dev, struct ifmap *map)
 930 {
 931   if ((map->port != (u_char)(-1)) && (map->port != dev->if_port)) {
 932     if (map->port <= 2) {
 933       dev->if_port = map->port;
 934       printk(KERN_INFO "%s: switched to %s port\n", dev->name,
 935              if_names[dev->if_port]);
 936     } else
 937       return -EINVAL;
 938   }
 939   return 0;
 940 } /* mace_config */
 941
 942 /* ----------------------------------------------------------------------------
 943 mace_open
 944         Open device driver.
 945 ---------------------------------------------------------------------------- */
 946 static int mace_open(struct net_device *dev)
 947 {
 948   ioaddr_t ioaddr = dev->base_addr;
 949   mace_private *lp = netdev_priv(dev);
 950   dev_link_t *link = &lp->link;
 951
 952   if (!DEV_OK(link))
 953     return -ENODEV;
 954
 955   link->open++;
 956
 957   MACEBANK(0);
 958
 959   netif_start_queue(dev);
 960   nmclan_reset(dev);
 961
 962   return 0; /* Always succeed */
 963 } /* mace_open */
 964
 965 /* ----------------------------------------------------------------------------
 966 mace_close
 967         Closes device driver.
 968 ---------------------------------------------------------------------------- */
 969 static int mace_close(struct net_device *dev)
 970 {
 971   ioaddr_t ioaddr = dev->base_addr;
 972   mace_private *lp = netdev_priv(dev);
 973   dev_link_t *link = &lp->link;
 974
 975   DEBUG(2, "%s: shutting down ethercard.\n", dev->name);
 976
 977   /* Mask off all interrupts from the MACE chip. */
 978   outb(0xFF, ioaddr + AM2150_MACE_BASE + MACE_IMR);
 979
 980   link->open--;
 981   netif_stop_queue(dev);
 982
 983   return 0;
 984 } /* mace_close */
 985
 986 static void netdev_get_drvinfo(struct net_device *dev,
 987                                struct ethtool_drvinfo *info)
 988 {
 989         strcpy(info->driver, DRV_NAME);
 990         strcpy(info->version, DRV_VERSION);
 991         sprintf(info->bus_info, "PCMCIA 0x%lx", dev->base_addr);
 992 }
 993
 994 #ifdef PCMCIA_DEBUG
 995 static u32 netdev_get_msglevel(struct net_device *dev)
 996 {
 997         return pc_debug;
 998 }
 999
1000 static void netdev_set_msglevel(struct net_device *dev, u32 level)
1001 {
1002         pc_debug = level;
1003 }
1004 #endif /* PCMCIA_DEBUG */
1005
1006 static struct ethtool_ops netdev_ethtool_ops = {
1007         .get_drvinfo            = netdev_get_drvinfo,
1008 #ifdef PCMCIA_DEBUG
1009         .get_msglevel           = netdev_get_msglevel,
1010         .set_msglevel           = netdev_set_msglevel,
1011 #endif /* PCMCIA_DEBUG */
1012 };
1013
1014 /* ----------------------------------------------------------------------------
1015 mace_start_xmit
1016         This routine begins the packet transmit function.  When completed,
1017         it will generate a transmit interrupt.
1018
1019         According to /usr/src/linux/net/inet/dev.c, if _start_xmit
1020         returns 0, the "packet is now solely the responsibility of the
1021         driver."  If _start_xmit returns non-zero, the "transmission
1022         failed, put skb back into a list."
1023 ---------------------------------------------------------------------------- */
1024
1025 static void mace_tx_timeout(struct net_device *dev)
1026 {
1027   mace_private *lp = netdev_priv(dev);
1028   dev_link_t *link = &lp->link;
1029
1030   printk(KERN_NOTICE "%s: transmit timed out -- ", dev->name);
1031 #if RESET_ON_TIMEOUT
1032   printk("resetting card\n");
1033   pcmcia_reset_card(link->handle, NULL);
1034 #else /* #if RESET_ON_TIMEOUT */
1035   printk("NOT resetting card\n");
1036 #endif /* #if RESET_ON_TIMEOUT */
1037   dev->trans_start = jiffies;
1038   netif_wake_queue(dev);
1039 }
1040
1041 static int mace_start_xmit(struct sk_buff *skb, struct net_device *dev)
1042 {
1043   mace_private *lp = netdev_priv(dev);
1044   ioaddr_t ioaddr = dev->base_addr;
1045
1046   netif_stop_queue(dev);
1047
1048   DEBUG(3, "%s: mace_start_xmit(length = %ld) called.\n",
1049         dev->name, (long)skb->len);
1050
1051 #if (!TX_INTERRUPTABLE)
1052   /* Disable MACE TX interrupts. */
1053   outb(MACE_IMR_DEFAULT | MACE_IR_XMTINT,
1054     ioaddr + AM2150_MACE_BASE + MACE_IMR);
1055   lp->tx_irq_disabled=1;
1056 #endif /* #if (!TX_INTERRUPTABLE) */
1057
1058   {
1059     /* This block must not be interrupted by another transmit request!
1060        mace_tx_timeout will take care of timer-based retransmissions from
1061        the upper layers.  The interrupt handler is guaranteed never to
1062        service a transmit interrupt while we are in here.
1063     */
1064
1065     lp->linux_stats.tx_bytes += skb->len;
1066     lp->tx_free_frames--;
1067
1068     /* WARNING: Write the _exact_ number of bytes written in the header! */
1069     /* Put out the word header [must be an outw()] . . . */
1070     outw(skb->len, ioaddr + AM2150_XMT);
1071     /* . . . and the packet [may be any combination of outw() and outb()] */
1072     outsw(ioaddr + AM2150_XMT, skb->data, skb->len >> 1);
1073     if (skb->len & 1) {
1074       /* Odd byte transfer */
1075       outb(skb->data[skb->len-1], ioaddr + AM2150_XMT);
1076     }
1077
1078     dev->trans_start = jiffies;
1079
1080 #if MULTI_TX
1081     if (lp->tx_free_frames > 0)
1082       netif_start_queue(dev);
1083 #endif /* #if MULTI_TX */
1084   }
1085
1086 #if (!TX_INTERRUPTABLE)
1087   /* Re-enable MACE TX interrupts. */
1088   lp->tx_irq_disabled=0;
1089   outb(MACE_IMR_DEFAULT, ioaddr + AM2150_MACE_BASE + MACE_IMR);
1090 #endif /* #if (!TX_INTERRUPTABLE) */
1091
1092   dev_kfree_skb(skb);
1093
1094   return 0;
1095 } /* mace_start_xmit */
1096
1097 /* ----------------------------------------------------------------------------
1098 mace_interrupt
1099         The interrupt handler.
1100 ---------------------------------------------------------------------------- */
1101 static irqreturn_t mace_interrupt(int irq, void *dev_id, struct pt_regs *regs)
1102 {
1103   struct net_device *dev = (struct net_device *) dev_id;
1104   mace_private *lp = netdev_priv(dev);
1105   ioaddr_t ioaddr = dev->base_addr;
1106   int status;
1107   int IntrCnt = MACE_MAX_IR_ITERATIONS;
1108
1109   if (dev == NULL) {
1110     DEBUG(2, "mace_interrupt(): irq 0x%X for unknown device.\n",
1111           irq);
1112     return IRQ_NONE;
1113   }
1114
1115   if (lp->tx_irq_disabled) {
1116     printk(
1117       (lp->tx_irq_disabled?
1118        KERN_NOTICE "%s: Interrupt with tx_irq_disabled "
1119        "[isr=%02X, imr=%02X]\n":
1120        KERN_NOTICE "%s: Re-entering the interrupt handler "
1121        "[isr=%02X, imr=%02X]\n"),
1122       dev->name,
1123       inb(ioaddr + AM2150_MACE_BASE + MACE_IR),
1124       inb(ioaddr + AM2150_MACE_BASE + MACE_IMR)
1125     );
1126     /* WARNING: MACE_IR has been read! */
1127     return IRQ_NONE;
1128   }
1129
1130   if (!netif_device_present(dev)) {
1131     DEBUG(2, "%s: interrupt from dead card\n", dev->name);
1132     return IRQ_NONE;
1133   }
1134
1135   do {
1136     /* WARNING: MACE_IR is a READ/CLEAR port! */
1137     status = inb(ioaddr + AM2150_MACE_BASE + MACE_IR);
1138
1139     DEBUG(3, "mace_interrupt: irq 0x%X status 0x%X.\n", irq, status);
1140
1141     if (status & MACE_IR_RCVINT) {
1142       mace_rx(dev, MACE_MAX_RX_ITERATIONS);
1143     }
1144
1145     if (status & MACE_IR_XMTINT) {
1146       unsigned char fifofc;
1147       unsigned char xmtrc;
1148       unsigned char xmtfs;
1149
1150       fifofc = inb(ioaddr + AM2150_MACE_BASE + MACE_FIFOFC);
1151       if ((fifofc & MACE_FIFOFC_XMTFC)==0) {
1152         lp->linux_stats.tx_errors++;
1153         outb(0xFF, ioaddr + AM2150_XMT_SKIP);
1154       }
1155
1156       /* Transmit Retry Count (XMTRC, reg 4) */
1157       xmtrc = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTRC);
1158       if (xmtrc & MACE_XMTRC_EXDEF) lp->mace_stats.exdef++;
1159       lp->mace_stats.xmtrc += (xmtrc & MACE_XMTRC_XMTRC);
1160
1161       if (
1162         (xmtfs = inb(ioaddr + AM2150_MACE_BASE + MACE_XMTFS)) &
1163         MACE_XMTFS_XMTSV /* Transmit Status Valid */
1164       ) {
1165         lp->mace_stats.xmtsv++;
1166
1167         if (xmtfs & ~MACE_XMTFS_XMTSV) {
1168           if (xmtfs & MACE_XMTFS_UFLO) {
1169             /* Underflow.  Indicates that the Transmit FIFO emptied before
1170                the end of frame was reached. */
1171             lp->mace_stats.uflo++;
1172           }
1173           if (xmtfs & MACE_XMTFS_LCOL) {
1174             /* Late Collision */
1175             lp->mace_stats.lcol++;
1176           }
1177           if (xmtfs & MACE_XMTFS_MORE) {
1178             /* MORE than one retry was needed */
1179             lp->mace_stats.more++;
1180           }
1181           if (xmtfs & MACE_XMTFS_ONE) {
1182             /* Exactly ONE retry occurred */
1183             lp->mace_stats.one++;
1184           }
1185           if (xmtfs & MACE_XMTFS_DEFER) {
1186             /* Transmission was defered */
1187             lp->mace_stats.defer++;
1188           }
1189           if (xmtfs & MACE_XMTFS_LCAR) {
1190             /* Loss of carrier */
1191             lp->mace_stats.lcar++;
1192           }
1193           if (xmtfs & MACE_XMTFS_RTRY) {
1194             /* Retry error: transmit aborted after 16 attempts */
1195             lp->mace_stats.rtry++;
1196           }
1197         } /* if (xmtfs & ~MACE_XMTFS_XMTSV) */
1198
1199       } /* if (xmtfs & MACE_XMTFS_XMTSV) */
1200
1201       lp->linux_stats.tx_packets++;
1202       lp->tx_free_frames++;
1203       netif_wake_queue(dev);
1204     } /* if (status & MACE_IR_XMTINT) */
1205
1206     if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) {
1207       if (status & MACE_IR_JAB) {
1208         /* Jabber Error.  Excessive transmit duration (20-150ms). */
1209         lp->mace_stats.jab++;
1210       }
1211       if (status & MACE_IR_BABL) {
1212         /* Babble Error.  >1518 bytes transmitted. */
1213         lp->mace_stats.babl++;
1214       }
1215       if (status & MACE_IR_CERR) {
1216         /* Collision Error.  CERR indicates the absence of the
1217            Signal Quality Error Test message after a packet
1218            transmission. */
1219         lp->mace_stats.cerr++;
1220       }
1221       if (status & MACE_IR_RCVCCO) {
1222         /* Receive Collision Count Overflow; */
1223         lp->mace_stats.rcvcco++;
1224       }
1225       if (status & MACE_IR_RNTPCO) {
1226         /* Runt Packet Count Overflow */
1227         lp->mace_stats.rntpco++;
1228       }
1229       if (status & MACE_IR_MPCO) {
1230         /* Missed Packet Count Overflow */
1231         lp->mace_stats.mpco++;
1232       }
1233     } /* if (status & ~MACE_IMR_DEFAULT & ~MACE_IR_RCVINT & ~MACE_IR_XMTINT) */
1234
1235   } while ((status & ~MACE_IMR_DEFAULT) && (--IntrCnt));
1236
1237   return IRQ_HANDLED;
1238 } /* mace_interrupt */
1239
1240 /* ----------------------------------------------------------------------------
1241 mace_rx
1242         Receives packets.
1243 ---------------------------------------------------------------------------- */
1244 static int mace_rx(struct net_device *dev, unsigned char RxCnt)
1245 {
1246   mace_private *lp = netdev_priv(dev);
1247   ioaddr_t ioaddr = dev->base_addr;
1248   unsigned char rx_framecnt;
1249   unsigned short rx_status;
1250
1251   while (
1252     ((rx_framecnt = inb(ioaddr + AM2150_RCV_FRAME_COUNT)) > 0) &&
1253     (rx_framecnt <= 12) && /* rx_framecnt==0xFF if card is extracted. */
1254     (RxCnt--)
1255   ) {
1256     rx_status = inw(ioaddr + AM2150_RCV);
1257
1258     DEBUG(3, "%s: in mace_rx(), framecnt 0x%X, rx_status"
1259           " 0x%X.\n", dev->name, rx_framecnt, rx_status);
1260
1261     if (rx_status & MACE_RCVFS_RCVSTS) { /* Error, update stats. */
1262       lp->linux_stats.rx_errors++;
1263       if (rx_status & MACE_RCVFS_OFLO) {
1264         lp->mace_stats.oflo++;
1265       }
1266       if (rx_status & MACE_RCVFS_CLSN) {
1267         lp->mace_stats.clsn++;
1268       }
1269       if (rx_status & MACE_RCVFS_FRAM) {
1270         lp->mace_stats.fram++;
1271       }
1272       if (rx_status & MACE_RCVFS_FCS) {
1273         lp->mace_stats.fcs++;
1274       }
1275     } else {
1276       short pkt_len = (rx_status & ~MACE_RCVFS_RCVSTS) - 4;
1277         /* Auto Strip is off, always subtract 4 */
1278       struct sk_buff *skb;
1279
1280       lp->mace_stats.rfs_rntpc += inb(ioaddr + AM2150_RCV);
1281         /* runt packet count */
1282       lp->mace_stats.rfs_rcvcc += inb(ioaddr + AM2150_RCV);
1283         /* rcv collision count */
1284
1285       DEBUG(3, "    receiving packet size 0x%X rx_status"
1286             " 0x%X.\n", pkt_len, rx_status);
1287
1288       skb = dev_alloc_skb(pkt_len+2);
1289
1290       if (skb != NULL) {
1291         skb->dev = dev;
1292
1293         skb_reserve(skb, 2);
1294         insw(ioaddr + AM2150_RCV, skb_put(skb, pkt_len), pkt_len>>1);
1295         if (pkt_len & 1)
1296             *(skb->tail-1) = inb(ioaddr + AM2150_RCV);
1297         skb->protocol = eth_type_trans(skb, dev);
1298
1299         netif_rx(skb); /* Send the packet to the upper (protocol) layers. */
1300
1301         dev->last_rx = jiffies;
1302         lp->linux_stats.rx_packets++;
1303         lp->linux_stats.rx_bytes += skb->len;
1304         outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1305         continue;
1306       } else {
1307         DEBUG(1, "%s: couldn't allocate a sk_buff of size"
1308               " %d.\n", dev->name, pkt_len);
1309         lp->linux_stats.rx_dropped++;
1310       }
1311     }
1312     outb(0xFF, ioaddr + AM2150_RCV_NEXT); /* skip to next frame */
1313   } /* while */
1314
1315   return 0;
1316 } /* mace_rx */
1317
1318 /* ----------------------------------------------------------------------------
1319 pr_linux_stats
1320 ---------------------------------------------------------------------------- */
1321 static void pr_linux_stats(struct net_device_stats *pstats)
1322 {
1323   DEBUG(2, "pr_linux_stats\n");
1324   DEBUG(2, " rx_packets=%-7ld        tx_packets=%ld\n",
1325         (long)pstats->rx_packets, (long)pstats->tx_packets);
1326   DEBUG(2, " rx_errors=%-7ld         tx_errors=%ld\n",
1327         (long)pstats->rx_errors, (long)pstats->tx_errors);
1328   DEBUG(2, " rx_dropped=%-7ld        tx_dropped=%ld\n",
1329         (long)pstats->rx_dropped, (long)pstats->tx_dropped);
1330   DEBUG(2, " multicast=%-7ld         collisions=%ld\n",
1331         (long)pstats->multicast, (long)pstats->collisions);
1332
1333   DEBUG(2, " rx_length_errors=%-7ld  rx_over_errors=%ld\n",
1334         (long)pstats->rx_length_errors, (long)pstats->rx_over_errors);
1335   DEBUG(2, " rx_crc_errors=%-7ld     rx_frame_errors=%ld\n",
1336         (long)pstats->rx_crc_errors, (long)pstats->rx_frame_errors);
1337   DEBUG(2, " rx_fifo_errors=%-7ld    rx_missed_errors=%ld\n",
1338         (long)pstats->rx_fifo_errors, (long)pstats->rx_missed_errors);
1339
1340   DEBUG(2, " tx_aborted_errors=%-7ld tx_carrier_errors=%ld\n",
1341         (long)pstats->tx_aborted_errors, (long)pstats->tx_carrier_errors);
1342   DEBUG(2, " tx_fifo_errors=%-7ld    tx_heartbeat_errors=%ld\n",
1343         (long)pstats->tx_fifo_errors, (long)pstats->tx_heartbeat_errors);
1344   DEBUG(2, " tx_window_errors=%ld\n",
1345         (long)pstats->tx_window_errors);
1346 } /* pr_linux_stats */
1347
1348 /* ----------------------------------------------------------------------------
1349 pr_mace_stats
1350 ---------------------------------------------------------------------------- */
1351 static void pr_mace_stats(mace_statistics *pstats)
1352 {
1353   DEBUG(2, "pr_mace_stats\n");
1354
1355   DEBUG(2, " xmtsv=%-7d             uflo=%d\n",
1356         pstats->xmtsv, pstats->uflo);
1357   DEBUG(2, " lcol=%-7d              more=%d\n",
1358         pstats->lcol, pstats->more);
1359   DEBUG(2, " one=%-7d               defer=%d\n",
1360         pstats->one, pstats->defer);
1361   DEBUG(2, " lcar=%-7d              rtry=%d\n",
1362         pstats->lcar, pstats->rtry);
1363
1364   /* MACE_XMTRC */
1365   DEBUG(2, " exdef=%-7d             xmtrc=%d\n",
1366         pstats->exdef, pstats->xmtrc);
1367
1368   /* RFS1--Receive Status (RCVSTS) */
1369   DEBUG(2, " oflo=%-7d              clsn=%d\n",
1370         pstats->oflo, pstats->clsn);
1371   DEBUG(2, " fram=%-7d              fcs=%d\n",
1372         pstats->fram, pstats->fcs);
1373
1374   /* RFS2--Runt Packet Count (RNTPC) */
1375   /* RFS3--Receive Collision Count (RCVCC) */
1376   DEBUG(2, " rfs_rntpc=%-7d         rfs_rcvcc=%d\n",
1377         pstats->rfs_rntpc, pstats->rfs_rcvcc);
1378
1379   /* MACE_IR */
1380   DEBUG(2, " jab=%-7d               babl=%d\n",
1381         pstats->jab, pstats->babl);
1382   DEBUG(2, " cerr=%-7d              rcvcco=%d\n",
1383         pstats->cerr, pstats->rcvcco);
1384   DEBUG(2, " rntpco=%-7d            mpco=%d\n",
1385         pstats->rntpco, pstats->mpco);
1386
1387   /* MACE_MPC */
1388   DEBUG(2, " mpc=%d\n", pstats->mpc);
1389
1390   /* MACE_RNTPC */
1391   DEBUG(2, " rntpc=%d\n", pstats->rntpc);
1392
1393   /* MACE_RCVCC */
1394   DEBUG(2, " rcvcc=%d\n", pstats->rcvcc);
1395
1396 } /* pr_mace_stats */
1397
1398 /* ----------------------------------------------------------------------------
1399 update_stats
1400         Update statistics.  We change to register window 1, so this
1401         should be run single-threaded if the device is active. This is
1402         expected to be a rare operation, and it's simpler for the rest
1403         of the driver to assume that window 0 is always valid rather
1404         than use a special window-state variable.
1405
1406         oflo & uflo should _never_ occur since it would mean the Xilinx
1407         was not able to transfer data between the MACE FIFO and the
1408         card's SRAM fast enough.  If this happens, something is
1409         seriously wrong with the hardware.
1410 ---------------------------------------------------------------------------- */
1411 static void update_stats(ioaddr_t ioaddr, struct net_device *dev)
1412 {
1413   mace_private *lp = netdev_priv(dev);
1414
1415   lp->mace_stats.rcvcc += mace_read(lp, ioaddr, MACE_RCVCC);
1416   lp->mace_stats.rntpc += mace_read(lp, ioaddr, MACE_RNTPC);
1417   lp->mace_stats.mpc += mace_read(lp, ioaddr, MACE_MPC);
1418   /* At this point, mace_stats is fully updated for this call.
1419      We may now update the linux_stats. */
1420
1421   /* The MACE has no equivalent for linux_stats field which are commented
1422      out. */
1423
1424   /* lp->linux_stats.multicast; */
1425   lp->linux_stats.collisions =
1426     lp->mace_stats.rcvcco * 256 + lp->mace_stats.rcvcc;
1427     /* Collision: The MACE may retry sending a packet 15 times
1428        before giving up.  The retry count is in XMTRC.
1429        Does each retry constitute a collision?
1430        If so, why doesn't the RCVCC record these collisions? */
1431
1432   /* detailed rx_errors: */
1433   lp->linux_stats.rx_length_errors =
1434     lp->mace_stats.rntpco * 256 + lp->mace_stats.rntpc;
1435   /* lp->linux_stats.rx_over_errors */
1436   lp->linux_stats.rx_crc_errors = lp->mace_stats.fcs;
1437   lp->linux_stats.rx_frame_errors = lp->mace_stats.fram;
1438   lp->linux_stats.rx_fifo_errors = lp->mace_stats.oflo;
1439   lp->linux_stats.rx_missed_errors =
1440     lp->mace_stats.mpco * 256 + lp->mace_stats.mpc;
1441
1442   /* detailed tx_errors */
1443   lp->linux_stats.tx_aborted_errors = lp->mace_stats.rtry;
1444   lp->linux_stats.tx_carrier_errors = lp->mace_stats.lcar;
1445     /* LCAR usually results from bad cabling. */
1446   lp->linux_stats.tx_fifo_errors = lp->mace_stats.uflo;
1447   lp->linux_stats.tx_heartbeat_errors = lp->mace_stats.cerr;
1448   /* lp->linux_stats.tx_window_errors; */
1449
1450   return;
1451 } /* update_stats */
1452
1453 /* ----------------------------------------------------------------------------
1454 mace_get_stats
1455         Gathers ethernet statistics from the MACE chip.
1456 ---------------------------------------------------------------------------- */
1457 static struct net_device_stats *mace_get_stats(struct net_device *dev)
1458 {
1459   mace_private *lp = netdev_priv(dev);
1460
1461   update_stats(dev->base_addr, dev);
1462
1463   DEBUG(1, "%s: updating the statistics.\n", dev->name);
1464   pr_linux_stats(&lp->linux_stats);
1465   pr_mace_stats(&lp->mace_stats);
1466
1467   return &lp->linux_stats;
1468 } /* net_device_stats */
1469
1470 /* ----------------------------------------------------------------------------
1471 updateCRC
1472         Modified from Am79C90 data sheet.
1473 ---------------------------------------------------------------------------- */
1474
1475 #ifdef BROKEN_MULTICAST
1476
1477 static void updateCRC(int *CRC, int bit)
1478 {
1479   int poly[]={
1480     1,1,1,0, 1,1,0,1,
1481     1,0,1,1, 1,0,0,0,
1482     1,0,0,0, 0,0,1,1,
1483     0,0,1,0, 0,0,0,0
1484   }; /* CRC polynomial.  poly[n] = coefficient of the x**n term of the
1485         CRC generator polynomial. */
1486
1487   int j;
1488
1489   /* shift CRC and control bit (CRC[32]) */
1490   for (j = 32; j > 0; j--)
1491     CRC[j] = CRC[j-1];
1492   CRC[0] = 0;
1493
1494   /* If bit XOR(control bit) = 1, set CRC = CRC XOR polynomial. */
1495   if (bit ^ CRC[32])
1496     for (j = 0; j < 32; j++)
1497       CRC[j] ^= poly[j];
1498 } /* updateCRC */
1499
1500 /* ----------------------------------------------------------------------------
1501 BuildLAF
1502         Build logical address filter.
1503         Modified from Am79C90 data sheet.
1504
1505 Input
1506         ladrf: logical address filter (contents initialized to 0)
1507         adr: ethernet address
1508 ---------------------------------------------------------------------------- */
1509 static void BuildLAF(int *ladrf, int *adr)
1510 {
1511   int CRC[33]={1}; /* CRC register, 1 word/bit + extra control bit */
1512
1513   int i, byte; /* temporary array indices */
1514   int hashcode; /* the output object */
1515
1516   CRC[32]=0;
1517
1518   for (byte = 0; byte < 6; byte++)
1519     for (i = 0; i < 8; i++)
1520       updateCRC(CRC, (adr[byte] >> i) & 1);
1521
1522   hashcode = 0;
1523   for (i = 0; i < 6; i++)
1524     hashcode = (hashcode << 1) + CRC[i];
1525
1526   byte = hashcode >> 3;
1527   ladrf[byte] |= (1 << (hashcode & 7));
1528
1529 #ifdef PCMCIA_DEBUG
1530   if (pc_debug > 2) {
1531     printk(KERN_DEBUG "    adr =");
1532     for (i = 0; i < 6; i++)
1533       printk(" %02X", adr[i]);
1534     printk("\n" KERN_DEBUG "    hashcode = %d(decimal), ladrf[0:63]"
1535            " =", hashcode);
1536     for (i = 0; i < 8; i++)
1537       printk(" %02X", ladrf[i]);
1538     printk("\n");
1539   }
1540 #endif
1541 } /* BuildLAF */
1542
1543 /* ----------------------------------------------------------------------------
1544 restore_multicast_list
1545         Restores the multicast filter for MACE chip to the last
1546         set_multicast_list() call.
1547
1548 Input
1549         multicast_num_addrs
1550         multicast_ladrf[]
1551 ---------------------------------------------------------------------------- */
1552 static void restore_multicast_list(struct net_device *dev)
1553 {
1554   mace_private *lp = netdev_priv(dev);
1555   int num_addrs = lp->multicast_num_addrs;
1556   int *ladrf = lp->multicast_ladrf;
1557   ioaddr_t ioaddr = dev->base_addr;
1558   int i;
1559
1560   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n",
1561         dev->name, num_addrs);
1562
1563   if (num_addrs > 0) {
1564
1565     DEBUG(1, "Attempt to restore multicast list detected.\n");
1566
1567     mace_write(lp, ioaddr, MACE_IAC, MACE_IAC_ADDRCHG | MACE_IAC_LOGADDR);
1568     /* Poll ADDRCHG bit */
1569     while (mace_read(lp, ioaddr, MACE_IAC) & MACE_IAC_ADDRCHG)
1570       ;
1571     /* Set LADRF register */
1572     for (i = 0; i < MACE_LADRF_LEN; i++)
1573       mace_write(lp, ioaddr, MACE_LADRF, ladrf[i]);
1574
1575     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_RCVFCSE | MACE_UTR_LOOP_EXTERNAL);
1576     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1577
1578   } else if (num_addrs < 0) {
1579
1580     /* Promiscuous mode: receive all packets */
1581     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1582     mace_write(lp, ioaddr, MACE_MACCC,
1583       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1584     );
1585
1586   } else {
1587
1588     /* Normal mode */
1589     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1590     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1591
1592   }
1593 } /* restore_multicast_list */
1594
1595 /* ----------------------------------------------------------------------------
1596 set_multicast_list
1597         Set or clear the multicast filter for this adaptor.
1598
1599 Input
1600         num_addrs == -1 Promiscuous mode, receive all packets
1601         num_addrs == 0  Normal mode, clear multicast list
1602         num_addrs > 0   Multicast mode, receive normal and MC packets, and do
1603                         best-effort filtering.
1604 Output
1605         multicast_num_addrs
1606         multicast_ladrf[]
1607 ---------------------------------------------------------------------------- */
1608
1609 static void set_multicast_list(struct net_device *dev)
1610 {
1611   mace_private *lp = netdev_priv(dev);
1612   int adr[ETHER_ADDR_LEN] = {0}; /* Ethernet address */
1613   int i;
1614   struct dev_mc_list *dmi = dev->mc_list;
1615
1616 #ifdef PCMCIA_DEBUG
1617   if (pc_debug > 1) {
1618     static int old;
1619     if (dev->mc_count != old) {
1620       old = dev->mc_count;
1621       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1622             dev->name, old);
1623     }
1624   }
1625 #endif
1626
1627   /* Set multicast_num_addrs. */
1628   lp->multicast_num_addrs = dev->mc_count;
1629
1630   /* Set multicast_ladrf. */
1631   if (num_addrs > 0) {
1632     /* Calculate multicast logical address filter */
1633     memset(lp->multicast_ladrf, 0, MACE_LADRF_LEN);
1634     for (i = 0; i < dev->mc_count; i++) {
1635       memcpy(adr, dmi->dmi_addr, ETHER_ADDR_LEN);
1636       dmi = dmi->next;
1637       BuildLAF(lp->multicast_ladrf, adr);
1638     }
1639   }
1640
1641   restore_multicast_list(dev);
1642
1643 } /* set_multicast_list */
1644
1645 #endif /* BROKEN_MULTICAST */
1646
1647 static void restore_multicast_list(struct net_device *dev)
1648 {
1649   ioaddr_t ioaddr = dev->base_addr;
1650   mace_private *lp = netdev_priv(dev);
1651
1652   DEBUG(2, "%s: restoring Rx mode to %d addresses.\n", dev->name,
1653         lp->multicast_num_addrs);
1654
1655   if (dev->flags & IFF_PROMISC) {
1656     /* Promiscuous mode: receive all packets */
1657     mace_write(lp,ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1658     mace_write(lp, ioaddr, MACE_MACCC,
1659       MACE_MACCC_PROM | MACE_MACCC_ENXMT | MACE_MACCC_ENRCV
1660     );
1661   } else {
1662     /* Normal mode */
1663     mace_write(lp, ioaddr, MACE_UTR, MACE_UTR_LOOP_EXTERNAL);
1664     mace_write(lp, ioaddr, MACE_MACCC, MACE_MACCC_ENXMT | MACE_MACCC_ENRCV);
1665   }
1666 } /* restore_multicast_list */
1667
1668 static void set_multicast_list(struct net_device *dev)
1669 {
1670   mace_private *lp = netdev_priv(dev);
1671
1672 #ifdef PCMCIA_DEBUG
1673   if (pc_debug > 1) {
1674     static int old;
1675     if (dev->mc_count != old) {
1676       old = dev->mc_count;
1677       DEBUG(0, "%s: setting Rx mode to %d addresses.\n",
1678             dev->name, old);
1679     }
1680   }
1681 #endif
1682
1683   lp->multicast_num_addrs = dev->mc_count;
1684   restore_multicast_list(dev);
1685
1686 } /* set_multicast_list */
1687
1688 static struct pcmcia_driver nmclan_cs_driver = {
1689         .owner          = THIS_MODULE,
1690         .drv            = {
1691                 .name   = "nmclan_cs",
1692         },
1693         .attach         = nmclan_attach,
1694         .detach         = nmclan_detach,
1695 };
1696
1697 static int __init init_nmclan_cs(void)
1698 {
1699         return pcmcia_register_driver(&nmclan_cs_driver);
1700 }
1701
1702 static void __exit exit_nmclan_cs(void)
1703 {
1704         pcmcia_unregister_driver(&nmclan_cs_driver);
1705         while (dev_list != NULL)
1706                 nmclan_detach(dev_list);
1707 }
1708
1709 module_init(init_nmclan_cs);
1710 module_exit(exit_nmclan_cs);