1 /*******************************************************************************
4 Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms of the GNU General Public License as published by the Free
8 Software Foundation; either version 2 of the License, or (at your option)
11 This program is distributed in the hope that it will be useful, but WITHOUT
12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 You should have received a copy of the GNU General Public License along with
17 this program; if not, write to the Free Software Foundation, Inc., 59
18 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
20 The full GNU General Public License is included in this distribution in the
24 Linux NICS <linux.nics@intel.com>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
30 * Shared functions for accessing and configuring the adapter
36 /* Local function prototypes */
38 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw
*hw
, uint8_t * mc_addr
);
40 static void ixgb_mta_set(struct ixgb_hw
*hw
, uint32_t hash_value
);
42 static void ixgb_get_bus_info(struct ixgb_hw
*hw
);
44 static boolean_t
ixgb_link_reset(struct ixgb_hw
*hw
);
46 static void ixgb_optics_reset(struct ixgb_hw
*hw
);
48 static ixgb_phy_type
ixgb_identify_phy(struct ixgb_hw
*hw
);
50 uint32_t ixgb_mac_reset(struct ixgb_hw
*hw
);
52 uint32_t ixgb_mac_reset(struct ixgb_hw
*hw
)
56 ctrl_reg
= IXGB_CTRL0_RST
| IXGB_CTRL0_SDP3_DIR
| /* All pins are Output=1 */
57 IXGB_CTRL0_SDP2_DIR
| IXGB_CTRL0_SDP1_DIR
| IXGB_CTRL0_SDP0_DIR
| IXGB_CTRL0_SDP3
| /* Initial value 1101 */
58 IXGB_CTRL0_SDP2
| IXGB_CTRL0_SDP0
;
61 /* Workaround for 82597EX reset errata */
62 IXGB_WRITE_REG_IO(hw
, CTRL0
, ctrl_reg
);
64 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
67 /* Delay a few ms just to allow the reset to complete */
68 msec_delay(IXGB_DELAY_AFTER_RESET
);
69 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
71 /* Make sure the self-clearing global reset bit did self clear */
72 ASSERT(!(ctrl_reg
& IXGB_CTRL0_RST
));
75 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
76 ixgb_optics_reset(hw
);
82 /******************************************************************************
83 * Reset the transmit and receive units; mask and clear all interrupts.
85 * hw - Struct containing variables accessed by shared code
86 *****************************************************************************/
87 boolean_t
ixgb_adapter_stop(struct ixgb_hw
* hw
)
92 DEBUGFUNC("ixgb_adapter_stop");
94 /* If we are stopped or resetting exit gracefully and wait to be
95 * started again before accessing the hardware.
97 if (hw
->adapter_stopped
) {
98 DEBUGOUT("Exiting because the adapter is already stopped!!!\n");
102 /* Set the Adapter Stopped flag so other driver functions stop
103 * touching the Hardware.
105 hw
->adapter_stopped
= TRUE
;
107 /* Clear interrupt mask to stop board from generating interrupts */
108 DEBUGOUT("Masking off all interrupts\n");
109 IXGB_WRITE_REG(hw
, IMC
, 0xFFFFFFFF);
111 /* Disable the Transmit and Receive units. Then delay to allow
112 * any pending transactions to complete before we hit the MAC with
115 IXGB_WRITE_REG(hw
, RCTL
, IXGB_READ_REG(hw
, RCTL
) & ~IXGB_RCTL_RXEN
);
116 IXGB_WRITE_REG(hw
, TCTL
, IXGB_READ_REG(hw
, TCTL
) & ~IXGB_TCTL_TXEN
);
117 msec_delay(IXGB_DELAY_BEFORE_RESET
);
119 /* Issue a global reset to the MAC. This will reset the chip's
120 * transmit, receive, DMA, and link units. It will not effect
121 * the current PCI configuration. The global reset bit is self-
122 * clearing, and should clear within a microsecond.
124 DEBUGOUT("Issuing a global reset to MAC\n");
126 ctrl_reg
= ixgb_mac_reset(hw
);
128 /* Clear interrupt mask to stop board from generating interrupts */
129 DEBUGOUT("Masking off all interrupts\n");
130 IXGB_WRITE_REG(hw
, IMC
, 0xffffffff);
132 /* Clear any pending interrupt events. */
133 icr_reg
= IXGB_READ_REG(hw
, ICR
);
135 return (ctrl_reg
& IXGB_CTRL0_RST
);
138 /******************************************************************************
139 * Identifies the vendor of the optics module on the adapter. The SR adapters
140 * support two different types of XPAK optics, so it is necessary to determine
141 * which optics are present before applying any optics-specific workarounds.
143 * hw - Struct containing variables accessed by shared code.
145 * Returns: the vendor of the XPAK optics module.
146 *****************************************************************************/
147 static ixgb_xpak_vendor
ixgb_identify_xpak_vendor(struct ixgb_hw
*hw
)
150 uint16_t vendor_name
[5];
151 ixgb_xpak_vendor xpak_vendor
;
153 DEBUGFUNC("ixgb_identify_xpak_vendor");
155 /* Read the first few bytes of the vendor string from the XPAK NVR
156 * registers. These are standard XENPAK/XPAK registers, so all XPAK
157 * devices should implement them. */
158 for (i
= 0; i
< 5; i
++) {
159 vendor_name
[i
] = ixgb_read_phy_reg(hw
,
160 MDIO_PMA_PMD_XPAK_VENDOR_NAME
161 + i
, IXGB_PHY_ADDRESS
,
165 /* Determine the actual vendor */
166 if (vendor_name
[0] == 'I' &&
167 vendor_name
[1] == 'N' &&
168 vendor_name
[2] == 'T' &&
169 vendor_name
[3] == 'E' && vendor_name
[4] == 'L') {
170 xpak_vendor
= ixgb_xpak_vendor_intel
;
172 xpak_vendor
= ixgb_xpak_vendor_infineon
;
175 return (xpak_vendor
);
178 /******************************************************************************
179 * Determine the physical layer module on the adapter.
181 * hw - Struct containing variables accessed by shared code. The device_id
182 * field must be (correctly) populated before calling this routine.
184 * Returns: the phy type of the adapter.
185 *****************************************************************************/
186 static ixgb_phy_type
ixgb_identify_phy(struct ixgb_hw
*hw
)
188 ixgb_phy_type phy_type
;
189 ixgb_xpak_vendor xpak_vendor
;
191 DEBUGFUNC("ixgb_identify_phy");
193 /* Infer the transceiver/phy type from the device id */
194 switch (hw
->device_id
) {
195 case IXGB_DEVICE_ID_82597EX
:
196 DEBUGOUT("Identified TXN17401 optics\n");
197 phy_type
= ixgb_phy_type_txn17401
;
200 case IXGB_DEVICE_ID_82597EX_SR
:
201 /* The SR adapters carry two different types of XPAK optics
202 * modules; read the vendor identifier to determine the exact
204 xpak_vendor
= ixgb_identify_xpak_vendor(hw
);
205 if (xpak_vendor
== ixgb_xpak_vendor_intel
) {
206 DEBUGOUT("Identified TXN17201 optics\n");
207 phy_type
= ixgb_phy_type_txn17201
;
209 DEBUGOUT("Identified G6005 optics\n");
210 phy_type
= ixgb_phy_type_g6005
;
215 DEBUGOUT("Unknown physical layer module\n");
216 phy_type
= ixgb_phy_type_unknown
;
223 /******************************************************************************
224 * Performs basic configuration of the adapter.
226 * hw - Struct containing variables accessed by shared code
228 * Resets the controller.
229 * Reads and validates the EEPROM.
230 * Initializes the receive address registers.
231 * Initializes the multicast table.
232 * Clears all on-chip counters.
233 * Calls routine to setup flow control settings.
234 * Leaves the transmit and receive units disabled and uninitialized.
237 * TRUE if successful,
238 * FALSE if unrecoverable problems were encountered.
239 *****************************************************************************/
240 boolean_t
ixgb_init_hw(struct ixgb_hw
* hw
)
246 DEBUGFUNC("ixgb_init_hw");
248 /* Issue a global reset to the MAC. This will reset the chip's
249 * transmit, receive, DMA, and link units. It will not effect
250 * the current PCI configuration. The global reset bit is self-
251 * clearing, and should clear within a microsecond.
253 DEBUGOUT("Issuing a global reset to MAC\n");
255 ctrl_reg
= ixgb_mac_reset(hw
);
257 DEBUGOUT("Issuing an EE reset to MAC\n");
259 /* Workaround for 82597EX reset errata */
260 IXGB_WRITE_REG_IO(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
262 IXGB_WRITE_REG(hw
, CTRL1
, IXGB_CTRL1_EE_RST
);
265 /* Delay a few ms just to allow the reset to complete */
266 msec_delay(IXGB_DELAY_AFTER_EE_RESET
);
268 if (ixgb_get_eeprom_data(hw
) == FALSE
) {
272 /* Use the device id to determine the type of phy/transceiver. */
273 hw
->device_id
= ixgb_get_ee_device_id(hw
);
274 hw
->phy_type
= ixgb_identify_phy(hw
);
276 /* Setup the receive addresses.
277 * Receive Address Registers (RARs 0 - 15).
279 ixgb_init_rx_addrs(hw
);
282 * Check that a valid MAC address has been set.
283 * If it is not valid, we fail hardware init.
285 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
286 DEBUGOUT("MAC address invalid after ixgb_init_rx_addrs\n");
290 /* tell the routines in this file they can access hardware again */
291 hw
->adapter_stopped
= FALSE
;
293 /* Fill in the bus_info structure */
294 ixgb_get_bus_info(hw
);
296 /* Zero out the Multicast HASH table */
297 DEBUGOUT("Zeroing the MTA\n");
298 for (i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++)
299 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
301 /* Zero out the VLAN Filter Table Array */
304 /* Zero all of the hardware counters */
305 ixgb_clear_hw_cntrs(hw
);
307 /* Call a subroutine to setup flow control. */
308 status
= ixgb_setup_fc(hw
);
310 /* 82597EX errata: Call check-for-link in case lane deskew is locked */
311 ixgb_check_for_link(hw
);
316 /******************************************************************************
317 * Initializes receive address filters.
319 * hw - Struct containing variables accessed by shared code
321 * Places the MAC address in receive address register 0 and clears the rest
322 * of the receive addresss registers. Clears the multicast table. Assumes
323 * the receiver is in reset when the routine is called.
324 *****************************************************************************/
325 void ixgb_init_rx_addrs(struct ixgb_hw
*hw
)
329 DEBUGFUNC("ixgb_init_rx_addrs");
332 * If the current mac address is valid, assume it is a software override
333 * to the permanent address.
334 * Otherwise, use the permanent address from the eeprom.
336 if (!mac_addr_valid(hw
->curr_mac_addr
)) {
338 /* Get the MAC address from the eeprom for later reference */
339 ixgb_get_ee_mac_addr(hw
, hw
->curr_mac_addr
);
341 DEBUGOUT3(" Keeping Permanent MAC Addr =%.2X %.2X %.2X ",
342 hw
->curr_mac_addr
[0],
343 hw
->curr_mac_addr
[1], hw
->curr_mac_addr
[2]);
344 DEBUGOUT3("%.2X %.2X %.2X\n",
345 hw
->curr_mac_addr
[3],
346 hw
->curr_mac_addr
[4], hw
->curr_mac_addr
[5]);
349 /* Setup the receive address. */
350 DEBUGOUT("Overriding MAC Address in RAR[0]\n");
351 DEBUGOUT3(" New MAC Addr =%.2X %.2X %.2X ",
352 hw
->curr_mac_addr
[0],
353 hw
->curr_mac_addr
[1], hw
->curr_mac_addr
[2]);
354 DEBUGOUT3("%.2X %.2X %.2X\n",
355 hw
->curr_mac_addr
[3],
356 hw
->curr_mac_addr
[4], hw
->curr_mac_addr
[5]);
358 ixgb_rar_set(hw
, hw
->curr_mac_addr
, 0);
361 /* Zero out the other 15 receive addresses. */
362 DEBUGOUT("Clearing RAR[1-15]\n");
363 for (i
= 1; i
< IXGB_RAR_ENTRIES
; i
++) {
364 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
365 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
371 /******************************************************************************
372 * Updates the MAC's list of multicast addresses.
374 * hw - Struct containing variables accessed by shared code
375 * mc_addr_list - the list of new multicast addresses
376 * mc_addr_count - number of addresses
377 * pad - number of bytes between addresses in the list
379 * The given list replaces any existing list. Clears the last 15 receive
380 * address registers and the multicast table. Uses receive address registers
381 * for the first 15 multicast addresses, and hashes the rest into the
383 *****************************************************************************/
385 ixgb_mc_addr_list_update(struct ixgb_hw
*hw
,
386 uint8_t * mc_addr_list
,
387 uint32_t mc_addr_count
, uint32_t pad
)
391 uint32_t rar_used_count
= 1; /* RAR[0] is used for our MAC address */
393 DEBUGFUNC("ixgb_mc_addr_list_update");
395 /* Set the new number of MC addresses that we are being requested to use. */
396 hw
->num_mc_addrs
= mc_addr_count
;
398 /* Clear RAR[1-15] */
399 DEBUGOUT(" Clearing RAR[1-15]\n");
400 for (i
= rar_used_count
; i
< IXGB_RAR_ENTRIES
; i
++) {
401 IXGB_WRITE_REG_ARRAY(hw
, RA
, (i
<< 1), 0);
402 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((i
<< 1) + 1), 0);
406 DEBUGOUT(" Clearing MTA\n");
407 for (i
= 0; i
< IXGB_MC_TBL_SIZE
; i
++) {
408 IXGB_WRITE_REG_ARRAY(hw
, MTA
, i
, 0);
411 /* Add the new addresses */
412 for (i
= 0; i
< mc_addr_count
; i
++) {
413 DEBUGOUT(" Adding the multicast addresses:\n");
414 DEBUGOUT7(" MC Addr #%d =%.2X %.2X %.2X %.2X %.2X %.2X\n", i
,
415 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
)],
416 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
418 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
420 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
422 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
424 mc_addr_list
[i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
) +
427 /* Place this multicast address in the RAR if there is room, *
428 * else put it in the MTA
430 if (rar_used_count
< IXGB_RAR_ENTRIES
) {
433 (i
* (IXGB_ETH_LENGTH_OF_ADDRESS
+ pad
)),
435 DEBUGOUT1("Added a multicast address to RAR[%d]\n", i
);
438 hash_value
= ixgb_hash_mc_addr(hw
,
441 (IXGB_ETH_LENGTH_OF_ADDRESS
444 DEBUGOUT1(" Hash value = 0x%03X\n", hash_value
);
446 ixgb_mta_set(hw
, hash_value
);
450 DEBUGOUT("MC Update Complete\n");
454 /******************************************************************************
455 * Hashes an address to determine its location in the multicast table
457 * hw - Struct containing variables accessed by shared code
458 * mc_addr - the multicast address to hash
462 *****************************************************************************/
463 static uint32_t ixgb_hash_mc_addr(struct ixgb_hw
*hw
, uint8_t * mc_addr
)
465 uint32_t hash_value
= 0;
467 DEBUGFUNC("ixgb_hash_mc_addr");
469 /* The portion of the address that is used for the hash table is
470 * determined by the mc_filter_type setting.
472 switch (hw
->mc_filter_type
) {
473 /* [0] [1] [2] [3] [4] [5]
475 * LSB MSB - According to H/W docs */
477 /* [47:36] i.e. 0x563 for above example address */
479 ((mc_addr
[4] >> 4) | (((uint16_t) mc_addr
[5]) << 4));
481 case 1: /* [46:35] i.e. 0xAC6 for above example address */
483 ((mc_addr
[4] >> 3) | (((uint16_t) mc_addr
[5]) << 5));
485 case 2: /* [45:34] i.e. 0x5D8 for above example address */
487 ((mc_addr
[4] >> 2) | (((uint16_t) mc_addr
[5]) << 6));
489 case 3: /* [43:32] i.e. 0x634 for above example address */
490 hash_value
= ((mc_addr
[4]) | (((uint16_t) mc_addr
[5]) << 8));
493 /* Invalid mc_filter_type, what should we do? */
494 DEBUGOUT("MC filter type param set incorrectly\n");
503 /******************************************************************************
504 * Sets the bit in the multicast table corresponding to the hash value.
506 * hw - Struct containing variables accessed by shared code
507 * hash_value - Multicast address hash value
508 *****************************************************************************/
509 static void ixgb_mta_set(struct ixgb_hw
*hw
, uint32_t hash_value
)
511 uint32_t hash_bit
, hash_reg
;
514 /* The MTA is a register array of 128 32-bit registers.
515 * It is treated like an array of 4096 bits. We want to set
516 * bit BitArray[hash_value]. So we figure out what register
517 * the bit is in, read it, OR in the new bit, then write
518 * back the new value. The register is determined by the
519 * upper 7 bits of the hash value and the bit within that
520 * register are determined by the lower 5 bits of the value.
522 hash_reg
= (hash_value
>> 5) & 0x7F;
523 hash_bit
= hash_value
& 0x1F;
525 mta_reg
= IXGB_READ_REG_ARRAY(hw
, MTA
, hash_reg
);
527 mta_reg
|= (1 << hash_bit
);
529 IXGB_WRITE_REG_ARRAY(hw
, MTA
, hash_reg
, mta_reg
);
534 /******************************************************************************
535 * Puts an ethernet address into a receive address register.
537 * hw - Struct containing variables accessed by shared code
538 * addr - Address to put into receive address register
539 * index - Receive address register to write
540 *****************************************************************************/
541 void ixgb_rar_set(struct ixgb_hw
*hw
, uint8_t * addr
, uint32_t index
)
543 uint32_t rar_low
, rar_high
;
545 DEBUGFUNC("ixgb_rar_set");
547 /* HW expects these in little endian so we reverse the byte order
548 * from network order (big endian) to little endian
550 rar_low
= ((uint32_t) addr
[0] |
551 ((uint32_t) addr
[1] << 8) |
552 ((uint32_t) addr
[2] << 16) | ((uint32_t) addr
[3] << 24));
554 rar_high
= ((uint32_t) addr
[4] |
555 ((uint32_t) addr
[5] << 8) | IXGB_RAH_AV
);
557 IXGB_WRITE_REG_ARRAY(hw
, RA
, (index
<< 1), rar_low
);
558 IXGB_WRITE_REG_ARRAY(hw
, RA
, ((index
<< 1) + 1), rar_high
);
562 /******************************************************************************
563 * Writes a value to the specified offset in the VLAN filter table.
565 * hw - Struct containing variables accessed by shared code
566 * offset - Offset in VLAN filer table to write
567 * value - Value to write into VLAN filter table
568 *****************************************************************************/
569 void ixgb_write_vfta(struct ixgb_hw
*hw
, uint32_t offset
, uint32_t value
)
571 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, value
);
575 /******************************************************************************
576 * Clears the VLAN filer table
578 * hw - Struct containing variables accessed by shared code
579 *****************************************************************************/
580 void ixgb_clear_vfta(struct ixgb_hw
*hw
)
584 for (offset
= 0; offset
< IXGB_VLAN_FILTER_TBL_SIZE
; offset
++)
585 IXGB_WRITE_REG_ARRAY(hw
, VFTA
, offset
, 0);
589 /******************************************************************************
590 * Configures the flow control settings based on SW configuration.
592 * hw - Struct containing variables accessed by shared code
593 *****************************************************************************/
595 boolean_t
ixgb_setup_fc(struct ixgb_hw
* hw
)
598 uint32_t pap_reg
= 0; /* by default, assume no pause time */
599 boolean_t status
= TRUE
;
601 DEBUGFUNC("ixgb_setup_fc");
603 /* Get the current control reg 0 settings */
604 ctrl_reg
= IXGB_READ_REG(hw
, CTRL0
);
606 /* Clear the Receive Pause Enable and Transmit Pause Enable bits */
607 ctrl_reg
&= ~(IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
609 /* The possible values of the "flow_control" parameter are:
610 * 0: Flow control is completely disabled
611 * 1: Rx flow control is enabled (we can receive pause frames
612 * but not send pause frames).
613 * 2: Tx flow control is enabled (we can send pause frames
614 * but we do not support receiving pause frames).
615 * 3: Both Rx and TX flow control (symmetric) are enabled.
618 switch (hw
->fc
.type
) {
619 case ixgb_fc_none
: /* 0 */
620 /* Set CMDC bit to disable Rx Flow control */
621 ctrl_reg
|= (IXGB_CTRL0_CMDC
);
623 case ixgb_fc_rx_pause
: /* 1 */
624 /* RX Flow control is enabled, and TX Flow control is
627 ctrl_reg
|= (IXGB_CTRL0_RPE
);
629 case ixgb_fc_tx_pause
: /* 2 */
630 /* TX Flow control is enabled, and RX Flow control is
631 * disabled, by a software over-ride.
633 ctrl_reg
|= (IXGB_CTRL0_TPE
);
634 pap_reg
= hw
->fc
.pause_time
;
636 case ixgb_fc_full
: /* 3 */
637 /* Flow control (both RX and TX) is enabled by a software
640 ctrl_reg
|= (IXGB_CTRL0_RPE
| IXGB_CTRL0_TPE
);
641 pap_reg
= hw
->fc
.pause_time
;
644 /* We should never get here. The value should be 0-3. */
645 DEBUGOUT("Flow control param set incorrectly\n");
650 /* Write the new settings */
651 IXGB_WRITE_REG(hw
, CTRL0
, ctrl_reg
);
654 IXGB_WRITE_REG(hw
, PAP
, pap_reg
);
657 /* Set the flow control receive threshold registers. Normally,
658 * these registers will be set to a default threshold that may be
659 * adjusted later by the driver's runtime code. However, if the
660 * ability to transmit pause frames in not enabled, then these
661 * registers will be set to 0.
663 if (!(hw
->fc
.type
& ixgb_fc_tx_pause
)) {
664 IXGB_WRITE_REG(hw
, FCRTL
, 0);
665 IXGB_WRITE_REG(hw
, FCRTH
, 0);
667 /* We need to set up the Receive Threshold high and low water
668 * marks as well as (optionally) enabling the transmission of XON frames.
670 if (hw
->fc
.send_xon
) {
671 IXGB_WRITE_REG(hw
, FCRTL
,
672 (hw
->fc
.low_water
| IXGB_FCRTL_XONE
));
674 IXGB_WRITE_REG(hw
, FCRTL
, hw
->fc
.low_water
);
676 IXGB_WRITE_REG(hw
, FCRTH
, hw
->fc
.high_water
);
681 /******************************************************************************
682 * Reads a word from a device over the Management Data Interface (MDI) bus.
683 * This interface is used to manage Physical layer devices.
685 * hw - Struct containing variables accessed by hw code
686 * reg_address - Offset of device register being read.
687 * phy_address - Address of device on MDI.
689 * Returns: Data word (16 bits) from MDI device.
691 * The 82597EX has support for several MDI access methods. This routine
692 * uses the new protocol MDI Single Command and Address Operation.
693 * This requires that first an address cycle command is sent, followed by a
695 *****************************************************************************/
697 ixgb_read_phy_reg(struct ixgb_hw
* hw
,
698 uint32_t reg_address
,
699 uint32_t phy_address
, uint32_t device_type
)
703 uint32_t command
= 0;
705 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
706 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
707 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
709 /* Setup and write the address cycle command */
710 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
711 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
712 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
713 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
715 IXGB_WRITE_REG(hw
, MSCA
, command
);
717 /**************************************************************
718 ** Check every 10 usec to see if the address cycle completed
719 ** The COMMAND bit will clear when the operation is complete.
720 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
721 ** from the CPU Write to the Ready bit assertion.
722 **************************************************************/
724 for (i
= 0; i
< 10; i
++) {
727 command
= IXGB_READ_REG(hw
, MSCA
);
729 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
733 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
735 /* Address cycle complete, setup and write the read command */
736 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
737 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
738 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
739 (IXGB_MSCA_READ
| IXGB_MSCA_MDI_COMMAND
));
741 IXGB_WRITE_REG(hw
, MSCA
, command
);
743 /**************************************************************
744 ** Check every 10 usec to see if the read command completed
745 ** The COMMAND bit will clear when the operation is complete.
746 ** The read may take as long as 64 usecs (we'll wait 100 usecs max)
747 ** from the CPU Write to the Ready bit assertion.
748 **************************************************************/
750 for (i
= 0; i
< 10; i
++) {
753 command
= IXGB_READ_REG(hw
, MSCA
);
755 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
759 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
761 /* Operation is complete, get the data from the MDIO Read/Write Data
762 * register and return.
764 data
= IXGB_READ_REG(hw
, MSRWD
);
765 data
>>= IXGB_MSRWD_READ_DATA_SHIFT
;
766 return ((uint16_t) data
);
769 /******************************************************************************
770 * Writes a word to a device over the Management Data Interface (MDI) bus.
771 * This interface is used to manage Physical layer devices.
773 * hw - Struct containing variables accessed by hw code
774 * reg_address - Offset of device register being read.
775 * phy_address - Address of device on MDI.
776 * device_type - Also known as the Device ID or DID.
777 * data - 16-bit value to be written
781 * The 82597EX has support for several MDI access methods. This routine
782 * uses the new protocol MDI Single Command and Address Operation.
783 * This requires that first an address cycle command is sent, followed by a
785 *****************************************************************************/
787 ixgb_write_phy_reg(struct ixgb_hw
*hw
,
788 uint32_t reg_address
,
789 uint32_t phy_address
, uint32_t device_type
, uint16_t data
)
792 uint32_t command
= 0;
794 ASSERT(reg_address
<= IXGB_MAX_PHY_REG_ADDRESS
);
795 ASSERT(phy_address
<= IXGB_MAX_PHY_ADDRESS
);
796 ASSERT(device_type
<= IXGB_MAX_PHY_DEV_TYPE
);
798 /* Put the data in the MDIO Read/Write Data register */
799 IXGB_WRITE_REG(hw
, MSRWD
, (uint32_t) data
);
801 /* Setup and write the address cycle command */
802 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
803 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
804 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
805 (IXGB_MSCA_ADDR_CYCLE
| IXGB_MSCA_MDI_COMMAND
));
807 IXGB_WRITE_REG(hw
, MSCA
, command
);
809 /**************************************************************
810 ** Check every 10 usec to see if the address cycle completed
811 ** The COMMAND bit will clear when the operation is complete.
812 ** This may take as long as 64 usecs (we'll wait 100 usecs max)
813 ** from the CPU Write to the Ready bit assertion.
814 **************************************************************/
816 for (i
= 0; i
< 10; i
++) {
819 command
= IXGB_READ_REG(hw
, MSCA
);
821 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
825 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
827 /* Address cycle complete, setup and write the write command */
828 command
= ((reg_address
<< IXGB_MSCA_NP_ADDR_SHIFT
) |
829 (device_type
<< IXGB_MSCA_DEV_TYPE_SHIFT
) |
830 (phy_address
<< IXGB_MSCA_PHY_ADDR_SHIFT
) |
831 (IXGB_MSCA_WRITE
| IXGB_MSCA_MDI_COMMAND
));
833 IXGB_WRITE_REG(hw
, MSCA
, command
);
835 /**************************************************************
836 ** Check every 10 usec to see if the read command completed
837 ** The COMMAND bit will clear when the operation is complete.
838 ** The write may take as long as 64 usecs (we'll wait 100 usecs max)
839 ** from the CPU Write to the Ready bit assertion.
840 **************************************************************/
842 for (i
= 0; i
< 10; i
++) {
845 command
= IXGB_READ_REG(hw
, MSCA
);
847 if ((command
& IXGB_MSCA_MDI_COMMAND
) == 0)
851 ASSERT((command
& IXGB_MSCA_MDI_COMMAND
) == 0);
853 /* Operation is complete, return. */
856 /******************************************************************************
857 * Checks to see if the link status of the hardware has changed.
859 * hw - Struct containing variables accessed by hw code
861 * Called by any function that needs to check the link status of the adapter.
862 *****************************************************************************/
863 void ixgb_check_for_link(struct ixgb_hw
*hw
)
868 DEBUGFUNC("ixgb_check_for_link");
870 xpcss_reg
= IXGB_READ_REG(hw
, XPCSS
);
871 status_reg
= IXGB_READ_REG(hw
, STATUS
);
873 if ((xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
874 (status_reg
& IXGB_STATUS_LU
)) {
876 } else if (!(xpcss_reg
& IXGB_XPCSS_ALIGN_STATUS
) &&
877 (status_reg
& IXGB_STATUS_LU
)) {
878 DEBUGOUT("XPCSS Not Aligned while Status:LU is set.\n");
879 hw
->link_up
= ixgb_link_reset(hw
);
882 * 82597EX errata. Since the lane deskew problem may prevent
883 * link, reset the link before reporting link down.
885 hw
->link_up
= ixgb_link_reset(hw
);
887 /* Anything else for 10 Gig?? */
890 /******************************************************************************
891 * Check for a bad link condition that may have occured.
892 * The indication is that the RFC / LFC registers may be incrementing
893 * continually. A full adapter reset is required to recover.
895 * hw - Struct containing variables accessed by hw code
897 * Called by any function that needs to check the link status of the adapter.
898 *****************************************************************************/
899 boolean_t
ixgb_check_for_bad_link(struct ixgb_hw
*hw
)
901 uint32_t newLFC
, newRFC
;
902 boolean_t bad_link_returncode
= FALSE
;
904 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
905 newLFC
= IXGB_READ_REG(hw
, LFC
);
906 newRFC
= IXGB_READ_REG(hw
, RFC
);
907 if ((hw
->lastLFC
+ 250 < newLFC
)
908 || (hw
->lastRFC
+ 250 < newRFC
)) {
910 ("BAD LINK! too many LFC/RFC since last check\n");
911 bad_link_returncode
= TRUE
;
913 hw
->lastLFC
= newLFC
;
914 hw
->lastRFC
= newRFC
;
917 return bad_link_returncode
;
920 /******************************************************************************
921 * Clears all hardware statistics counters.
923 * hw - Struct containing variables accessed by shared code
924 *****************************************************************************/
925 void ixgb_clear_hw_cntrs(struct ixgb_hw
*hw
)
927 volatile uint32_t temp_reg
;
929 DEBUGFUNC("ixgb_clear_hw_cntrs");
931 /* if we are stopped or resetting exit gracefully */
932 if (hw
->adapter_stopped
) {
933 DEBUGOUT("Exiting because the adapter is stopped!!!\n");
937 temp_reg
= IXGB_READ_REG(hw
, TPRL
);
938 temp_reg
= IXGB_READ_REG(hw
, TPRH
);
939 temp_reg
= IXGB_READ_REG(hw
, GPRCL
);
940 temp_reg
= IXGB_READ_REG(hw
, GPRCH
);
941 temp_reg
= IXGB_READ_REG(hw
, BPRCL
);
942 temp_reg
= IXGB_READ_REG(hw
, BPRCH
);
943 temp_reg
= IXGB_READ_REG(hw
, MPRCL
);
944 temp_reg
= IXGB_READ_REG(hw
, MPRCH
);
945 temp_reg
= IXGB_READ_REG(hw
, UPRCL
);
946 temp_reg
= IXGB_READ_REG(hw
, UPRCH
);
947 temp_reg
= IXGB_READ_REG(hw
, VPRCL
);
948 temp_reg
= IXGB_READ_REG(hw
, VPRCH
);
949 temp_reg
= IXGB_READ_REG(hw
, JPRCL
);
950 temp_reg
= IXGB_READ_REG(hw
, JPRCH
);
951 temp_reg
= IXGB_READ_REG(hw
, GORCL
);
952 temp_reg
= IXGB_READ_REG(hw
, GORCH
);
953 temp_reg
= IXGB_READ_REG(hw
, TORL
);
954 temp_reg
= IXGB_READ_REG(hw
, TORH
);
955 temp_reg
= IXGB_READ_REG(hw
, RNBC
);
956 temp_reg
= IXGB_READ_REG(hw
, RUC
);
957 temp_reg
= IXGB_READ_REG(hw
, ROC
);
958 temp_reg
= IXGB_READ_REG(hw
, RLEC
);
959 temp_reg
= IXGB_READ_REG(hw
, CRCERRS
);
960 temp_reg
= IXGB_READ_REG(hw
, ICBC
);
961 temp_reg
= IXGB_READ_REG(hw
, ECBC
);
962 temp_reg
= IXGB_READ_REG(hw
, MPC
);
963 temp_reg
= IXGB_READ_REG(hw
, TPTL
);
964 temp_reg
= IXGB_READ_REG(hw
, TPTH
);
965 temp_reg
= IXGB_READ_REG(hw
, GPTCL
);
966 temp_reg
= IXGB_READ_REG(hw
, GPTCH
);
967 temp_reg
= IXGB_READ_REG(hw
, BPTCL
);
968 temp_reg
= IXGB_READ_REG(hw
, BPTCH
);
969 temp_reg
= IXGB_READ_REG(hw
, MPTCL
);
970 temp_reg
= IXGB_READ_REG(hw
, MPTCH
);
971 temp_reg
= IXGB_READ_REG(hw
, UPTCL
);
972 temp_reg
= IXGB_READ_REG(hw
, UPTCH
);
973 temp_reg
= IXGB_READ_REG(hw
, VPTCL
);
974 temp_reg
= IXGB_READ_REG(hw
, VPTCH
);
975 temp_reg
= IXGB_READ_REG(hw
, JPTCL
);
976 temp_reg
= IXGB_READ_REG(hw
, JPTCH
);
977 temp_reg
= IXGB_READ_REG(hw
, GOTCL
);
978 temp_reg
= IXGB_READ_REG(hw
, GOTCH
);
979 temp_reg
= IXGB_READ_REG(hw
, TOTL
);
980 temp_reg
= IXGB_READ_REG(hw
, TOTH
);
981 temp_reg
= IXGB_READ_REG(hw
, DC
);
982 temp_reg
= IXGB_READ_REG(hw
, PLT64C
);
983 temp_reg
= IXGB_READ_REG(hw
, TSCTC
);
984 temp_reg
= IXGB_READ_REG(hw
, TSCTFC
);
985 temp_reg
= IXGB_READ_REG(hw
, IBIC
);
986 temp_reg
= IXGB_READ_REG(hw
, RFC
);
987 temp_reg
= IXGB_READ_REG(hw
, LFC
);
988 temp_reg
= IXGB_READ_REG(hw
, PFRC
);
989 temp_reg
= IXGB_READ_REG(hw
, PFTC
);
990 temp_reg
= IXGB_READ_REG(hw
, MCFRC
);
991 temp_reg
= IXGB_READ_REG(hw
, MCFTC
);
992 temp_reg
= IXGB_READ_REG(hw
, XONRXC
);
993 temp_reg
= IXGB_READ_REG(hw
, XONTXC
);
994 temp_reg
= IXGB_READ_REG(hw
, XOFFRXC
);
995 temp_reg
= IXGB_READ_REG(hw
, XOFFTXC
);
996 temp_reg
= IXGB_READ_REG(hw
, RJC
);
1000 /******************************************************************************
1001 * Turns on the software controllable LED
1003 * hw - Struct containing variables accessed by shared code
1004 *****************************************************************************/
1005 void ixgb_led_on(struct ixgb_hw
*hw
)
1007 uint32_t ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1009 /* To turn on the LED, clear software-definable pin 0 (SDP0). */
1010 ctrl0_reg
&= ~IXGB_CTRL0_SDP0
;
1011 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1015 /******************************************************************************
1016 * Turns off the software controllable LED
1018 * hw - Struct containing variables accessed by shared code
1019 *****************************************************************************/
1020 void ixgb_led_off(struct ixgb_hw
*hw
)
1022 uint32_t ctrl0_reg
= IXGB_READ_REG(hw
, CTRL0
);
1024 /* To turn off the LED, set software-definable pin 0 (SDP0). */
1025 ctrl0_reg
|= IXGB_CTRL0_SDP0
;
1026 IXGB_WRITE_REG(hw
, CTRL0
, ctrl0_reg
);
1030 /******************************************************************************
1031 * Gets the current PCI bus type, speed, and width of the hardware
1033 * hw - Struct containing variables accessed by shared code
1034 *****************************************************************************/
1035 static void ixgb_get_bus_info(struct ixgb_hw
*hw
)
1037 uint32_t status_reg
;
1039 status_reg
= IXGB_READ_REG(hw
, STATUS
);
1041 hw
->bus
.type
= (status_reg
& IXGB_STATUS_PCIX_MODE
) ?
1042 ixgb_bus_type_pcix
: ixgb_bus_type_pci
;
1044 if (hw
->bus
.type
== ixgb_bus_type_pci
) {
1045 hw
->bus
.speed
= (status_reg
& IXGB_STATUS_PCI_SPD
) ?
1046 ixgb_bus_speed_66
: ixgb_bus_speed_33
;
1048 switch (status_reg
& IXGB_STATUS_PCIX_SPD_MASK
) {
1049 case IXGB_STATUS_PCIX_SPD_66
:
1050 hw
->bus
.speed
= ixgb_bus_speed_66
;
1052 case IXGB_STATUS_PCIX_SPD_100
:
1053 hw
->bus
.speed
= ixgb_bus_speed_100
;
1055 case IXGB_STATUS_PCIX_SPD_133
:
1056 hw
->bus
.speed
= ixgb_bus_speed_133
;
1059 hw
->bus
.speed
= ixgb_bus_speed_reserved
;
1064 hw
->bus
.width
= (status_reg
& IXGB_STATUS_BUS64
) ?
1065 ixgb_bus_width_64
: ixgb_bus_width_32
;
1070 /******************************************************************************
1071 * Tests a MAC address to ensure it is a valid Individual Address
1073 * mac_addr - pointer to MAC address.
1075 *****************************************************************************/
1076 boolean_t
mac_addr_valid(uint8_t * mac_addr
)
1078 boolean_t is_valid
= TRUE
;
1079 DEBUGFUNC("mac_addr_valid");
1081 /* Make sure it is not a multicast address */
1082 if (IS_MULTICAST(mac_addr
)) {
1083 DEBUGOUT("MAC address is multicast\n");
1086 /* Not a broadcast address */
1087 else if (IS_BROADCAST(mac_addr
)) {
1088 DEBUGOUT("MAC address is broadcast\n");
1091 /* Reject the zero address */
1092 else if (mac_addr
[0] == 0 &&
1095 mac_addr
[3] == 0 && mac_addr
[4] == 0 && mac_addr
[5] == 0) {
1096 DEBUGOUT("MAC address is all zeros\n");
1102 /******************************************************************************
1103 * Resets the 10GbE link. Waits the settle time and returns the state of
1106 * hw - Struct containing variables accessed by shared code
1107 *****************************************************************************/
1108 boolean_t
ixgb_link_reset(struct ixgb_hw
* hw
)
1110 boolean_t link_status
= FALSE
;
1111 uint8_t wait_retries
= MAX_RESET_ITERATIONS
;
1112 uint8_t lrst_retries
= MAX_RESET_ITERATIONS
;
1115 /* Reset the link */
1116 IXGB_WRITE_REG(hw
, CTRL0
,
1117 IXGB_READ_REG(hw
, CTRL0
) | IXGB_CTRL0_LRST
);
1119 /* Wait for link-up and lane re-alignment */
1121 udelay(IXGB_DELAY_USECS_AFTER_LINK_RESET
);
1123 ((IXGB_READ_REG(hw
, STATUS
) & IXGB_STATUS_LU
)
1124 && (IXGB_READ_REG(hw
, XPCSS
) &
1125 IXGB_XPCSS_ALIGN_STATUS
)) ? TRUE
: FALSE
;
1126 } while (!link_status
&& --wait_retries
);
1128 } while (!link_status
&& --lrst_retries
);
1133 /******************************************************************************
1134 * Resets the 10GbE optics module.
1136 * hw - Struct containing variables accessed by shared code
1137 *****************************************************************************/
1138 void ixgb_optics_reset(struct ixgb_hw
*hw
)
1140 if (hw
->phy_type
== ixgb_phy_type_txn17401
) {
1143 ixgb_write_phy_reg(hw
,
1146 MDIO_PMA_PMD_DID
, MDIO_PMA_PMD_CR1_RESET
);
1148 mdio_reg
= ixgb_read_phy_reg(hw
,