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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / net / bagetlance.c
blobe62ad3ad6e58d37332db9c17491983d1cff80343
1 /*
2 * bagetlance.c: Ethernet driver for VME Lance cards on Baget/MIPS
3 * This code stealed and adopted from linux/drivers/net/atarilance.c
4 * See that for author info
5 *
6 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
7 */
8
9 /*
10 * Driver code for Baget/Lance taken from atarilance.c, which also
11 * works well in case of Besta. Most significant changes made here
12 * related with 16BIT-only access to A24 space.
13 */
14
15 static char *version = "bagetlance.c: v1.1 11/10/98\n";
16
17 #include <linux/module.h>
18 #include <linux/stddef.h>
19 #include <linux/kernel.h>
20 #include <linux/string.h>
21 #include <linux/errno.h>
22 #include <linux/slab.h>
23 #include <linux/interrupt.h>
24 #include <linux/init.h>
25 #include <linux/netdevice.h>
26 #include <linux/etherdevice.h>
27 #include <linux/skbuff.h>
28
29 #include <asm/irq.h>
30 #include <asm/bitops.h>
31 #include <asm/io.h>
32 #include <asm/baget/baget.h>
33
34 #define BAGET_LANCE_IRQ BAGET_IRQ_MASK(0xdf)
35
36 /*
37 * Define following if you don't need 16BIT-only access to Lance memory
38 * (Normally BAGET needs it)
39 */
40 #undef NORMAL_MEM_ACCESS
41
42 /* Debug level:
43 * 0 = silent, print only serious errors
44 * 1 = normal, print error messages
45 * 2 = debug, print debug infos
46 * 3 = debug, print even more debug infos (packet data)
47 */
48
49 #define LANCE_DEBUG 1
50
51 #ifdef LANCE_DEBUG
52 static int lance_debug = LANCE_DEBUG;
53 #else
54 static int lance_debug = 1;
55 #endif
56 MODULE_PARM(lance_debug, "i");
57 MODULE_PARM_DESC(lance_debug, "Lance debug level (0-3)");
58 MODULE_LICENSE("GPL");
59
60 /* Print debug messages on probing? */
61 #undef LANCE_DEBUG_PROBE
62
63 #define DPRINTK(n,a) \
64 do { \
65 if (lance_debug >= n) \
66 printk a; \
67 } while( 0 )
68
69 #ifdef LANCE_DEBUG_PROBE
70 # define PROBE_PRINT(a) printk a
71 #else
72 # define PROBE_PRINT(a)
73 #endif
74
75 /* These define the number of Rx and Tx buffers as log2. (Only powers
76 * of two are valid)
77 * Much more rx buffers (32) are reserved than tx buffers (8), since receiving
78 * is more time critical then sending and packets may have to remain in the
79 * board's memory when main memory is low.
80 */
81
82 /* Baget Lance has 64K on-board memory, so it looks we can't increase
83 buffer quantity (40*1.5K is about 64K) */
84
85 #define TX_LOG_RING_SIZE 3
86 #define RX_LOG_RING_SIZE 5
87
88 /* These are the derived values */
89
90 #define TX_RING_SIZE (1 << TX_LOG_RING_SIZE)
91 #define TX_RING_LEN_BITS (TX_LOG_RING_SIZE << 5)
92 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
93
94 #define RX_RING_SIZE (1 << RX_LOG_RING_SIZE)
95 #define RX_RING_LEN_BITS (RX_LOG_RING_SIZE << 5)
96 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
97
98 /* The LANCE Rx and Tx ring descriptors. */
99 struct lance_rx_head {
100 volatile unsigned short base; /* Low word of base addr */
101 #ifdef NORMAL_MEM_ACCESS
102 /* Following two fields are joined into one short to guarantee
103 16BIT access to Baget lance registers */
104 volatile unsigned char flag;
105 unsigned char base_hi; /* High word of base addr (unused) */
106 #else
107 /* Following macros are used as replecements to 8BIT fields */
108 #define GET_FLAG(h) (((h)->flag_base_hi >> 8) & 0xff)
109 #define SET_FLAG(h,f) (h)->flag_base_hi = ((h)->flag_base_hi & 0xff) | \
110 (((unsigned)(f)) << 8)
111 volatile unsigned short flag_base_hi;
112 #endif
113 volatile short buf_length; /* This length is 2s complement! */
114 volatile short msg_length; /* This length is "normal". */
115 };
116
117
118 struct lance_tx_head {
119 volatile unsigned short base; /* Low word of base addr */
120 #ifdef NORMAL_MEM_ACCESS
121 /* See comments above about 8BIT-access Baget A24-space problems */
122 volatile unsigned char flag;
123 unsigned char base_hi; /* High word of base addr (unused) */
124 #else
125 volatile unsigned short flag_base_hi;
126 #endif
127 volatile short length; /* Length is 2s complement! */
128 volatile short misc;
129 };
130
131 struct ringdesc {
132 volatile unsigned short adr_lo; /* Low 16 bits of address */
133 #ifdef NORMAL_MEM_ACCESS
134 /* See comments above about 8BIT-access Bage A24-space problems */
135 unsigned char len; /* Length bits */
136 unsigned char adr_hi; /* High 8 bits of address (unused) */
137 #else
138 volatile unsigned short len_adr_hi;
139 #endif
140 };
141
142 /* The LANCE initialization block, described in databook. */
143 struct lance_init_block {
144 unsigned short mode; /* Pre-set mode */
145 unsigned char hwaddr[6]; /* Physical ethernet address */
146 unsigned filter[2]; /* Multicast filter (unused). */
147 /* Receive and transmit ring base, along with length bits. */
148 struct ringdesc rx_ring;
149 struct ringdesc tx_ring;
150 };
151
152 /* The whole layout of the Lance shared memory */
153 struct lance_memory {
154 struct lance_init_block init;
155 struct lance_tx_head tx_head[TX_RING_SIZE];
156 struct lance_rx_head rx_head[RX_RING_SIZE];
157 char packet_area[0]; /* packet data follow after the
158 * init block and the ring
159 * descriptors and are located
160 * at runtime */
161 };
162
163 /* RieblCard specifics:
164 * The original TOS driver for these cards reserves the area from offset
165 * 0xee70 to 0xeebb for storing configuration data. Of interest to us is the
166 * Ethernet address there, and the magic for verifying the data's validity.
167 * The reserved area isn't touch by packet buffers. Furthermore, offset 0xfffe
168 * is reserved for the interrupt vector number.
169 */
170 #define RIEBL_RSVD_START 0xee70
171 #define RIEBL_RSVD_END 0xeec0
172 #define RIEBL_MAGIC 0x09051990
173 #define RIEBL_MAGIC_ADDR ((unsigned long *)(((char *)MEM) + 0xee8a))
174 #define RIEBL_HWADDR_ADDR ((unsigned char *)(((char *)MEM) + 0xee8e))
175 #define RIEBL_IVEC_ADDR ((unsigned short *)(((char *)MEM) + 0xfffe))
176
177 /* This is a default address for the old RieblCards without a battery
178 * that have no ethernet address at boot time. 00:00:36:04 is the
179 * prefix for Riebl cards, the 00:00 at the end is arbitrary.
180 */
181
182 static unsigned char OldRieblDefHwaddr[6] = {
183 0x00, 0x00, 0x36, 0x04, 0x00, 0x00
184 };
185
186 /* I/O registers of the Lance chip */
187
188 struct lance_ioreg {
189 /* base+0x0 */ volatile unsigned short data;
190 /* base+0x2 */ volatile unsigned short addr;
191 unsigned char _dummy1[3];
192 /* base+0x7 */ volatile unsigned char ivec;
193 unsigned char _dummy2[5];
194 /* base+0xd */ volatile unsigned char eeprom;
195 unsigned char _dummy3;
196 /* base+0xf */ volatile unsigned char mem;
197 };
198
199 /* Types of boards this driver supports */
200
201 enum lance_type {
202 OLD_RIEBL, /* old Riebl card without battery */
203 NEW_RIEBL, /* new Riebl card with battery */
204 PAM_CARD /* PAM card with EEPROM */
205 };
206
207 static char *lance_names[] = {
208 "Riebl-Card (without battery)",
209 "Riebl-Card (with battery)",
210 "PAM intern card"
211 };
212
213 /* The driver's private device structure */
214
215 struct lance_private {
216 enum lance_type cardtype;
217 struct lance_ioreg *iobase;
218 struct lance_memory *mem;
219 int cur_rx, cur_tx; /* The next free ring entry */
220 int dirty_tx; /* Ring entries to be freed. */
221 /* copy function */
222 void *(*memcpy_f)( void *, const void *, size_t );
223 struct net_device_stats stats;
224 /* These two must be longs for set_bit() */
225 long tx_full;
226 long lock;
227 };
228
229 /* I/O register access macros */
230
231 #define MEM lp->mem
232 #define DREG IO->data
233 #define AREG IO->addr
234 #define REGA(a) ( AREG = (a), DREG )
235
236 /* Definitions for packet buffer access: */
237 #define PKT_BUF_SZ 1544
238 /* Get the address of a packet buffer corresponding to a given buffer head */
239 #define PKTBUF_ADDR(head) (((unsigned char *)(MEM)) + (head)->base)
240
241 /* Possible memory/IO addresses for probing */
242
243 struct lance_addr {
244 unsigned long memaddr;
245 unsigned long ioaddr;
246 int slow_flag;
247 } lance_addr_list[] = {
248 { BAGET_LANCE_MEM_BASE, BAGET_LANCE_IO_BASE, 1 } /* Baget Lance */
249 };
250
251 #define N_LANCE_ADDR (sizeof(lance_addr_list)/sizeof(*lance_addr_list))
252
253
254 #define LANCE_HI_BASE (0xff & (BAGET_LANCE_MEM_BASE >> 16))
255
256 /* Definitions for the Lance */
257
258 /* tx_head flags */
259 #define TMD1_ENP 0x01 /* end of packet */
260 #define TMD1_STP 0x02 /* start of packet */
261 #define TMD1_DEF 0x04 /* deferred */
262 #define TMD1_ONE 0x08 /* one retry needed */
263 #define TMD1_MORE 0x10 /* more than one retry needed */
264 #define TMD1_ERR 0x40 /* error summary */
265 #define TMD1_OWN 0x80 /* ownership (set: chip owns) */
266
267 #define TMD1_OWN_CHIP TMD1_OWN
268 #define TMD1_OWN_HOST 0
269
270 /* tx_head misc field */
271 #define TMD3_TDR 0x03FF /* Time Domain Reflectometry counter */
272 #define TMD3_RTRY 0x0400 /* failed after 16 retries */
273 #define TMD3_LCAR 0x0800 /* carrier lost */
274 #define TMD3_LCOL 0x1000 /* late collision */
275 #define TMD3_UFLO 0x4000 /* underflow (late memory) */
276 #define TMD3_BUFF 0x8000 /* buffering error (no ENP) */
277
278 /* rx_head flags */
279 #define RMD1_ENP 0x01 /* end of packet */
280 #define RMD1_STP 0x02 /* start of packet */
281 #define RMD1_BUFF 0x04 /* buffer error */
282 #define RMD1_CRC 0x08 /* CRC error */
283 #define RMD1_OFLO 0x10 /* overflow */
284 #define RMD1_FRAM 0x20 /* framing error */
285 #define RMD1_ERR 0x40 /* error summary */
286 #define RMD1_OWN 0x80 /* ownership (set: ship owns) */
287
288 #define RMD1_OWN_CHIP RMD1_OWN
289 #define RMD1_OWN_HOST 0
290
291 /* register names */
292 #define CSR0 0 /* mode/status */
293 #define CSR1 1 /* init block addr (low) */
294 #define CSR2 2 /* init block addr (high) */
295 #define CSR3 3 /* misc */
296 #define CSR8 8 /* address filter */
297 #define CSR15 15 /* promiscuous mode */
298
299 /* CSR0 */
300 /* (R=readable, W=writeable, S=set on write, C=clear on write) */
301 #define CSR0_INIT 0x0001 /* initialize (RS) */
302 #define CSR0_STRT 0x0002 /* start (RS) */
303 #define CSR0_STOP 0x0004 /* stop (RS) */
304 #define CSR0_TDMD 0x0008 /* transmit demand (RS) */
305 #define CSR0_TXON 0x0010 /* transmitter on (R) */
306 #define CSR0_RXON 0x0020 /* receiver on (R) */
307 #define CSR0_INEA 0x0040 /* interrupt enable (RW) */
308 #define CSR0_INTR 0x0080 /* interrupt active (R) */
309 #define CSR0_IDON 0x0100 /* initialization done (RC) */
310 #define CSR0_TINT 0x0200 /* transmitter interrupt (RC) */
311 #define CSR0_RINT 0x0400 /* receiver interrupt (RC) */
312 #define CSR0_MERR 0x0800 /* memory error (RC) */
313 #define CSR0_MISS 0x1000 /* missed frame (RC) */
314 #define CSR0_CERR 0x2000 /* carrier error (no heartbeat :-) (RC) */
315 #define CSR0_BABL 0x4000 /* babble: tx-ed too many bits (RC) */
316 #define CSR0_ERR 0x8000 /* error (RC) */
317
318 /* CSR3 */
319 #define CSR3_BCON 0x0001 /* byte control */
320 #define CSR3_ACON 0 // fixme: 0x0002 /* ALE control */
321 #define CSR3_BSWP 0x0004 /* byte swap (1=big endian) */
322
323
324
325 /***************************** Prototypes *****************************/
326
327 static int addr_accessible( volatile void *regp, int wordflag, int
328 writeflag );
329 static int lance_probe1( struct net_device *dev, struct lance_addr *init_rec );
330 static int lance_open( struct net_device *dev );
331 static void lance_init_ring( struct net_device *dev );
332 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev );
333 static irqreturn_t lance_interrupt( int irq, void *dev_id, struct pt_regs *fp );
334 static int lance_rx( struct net_device *dev );
335 static int lance_close( struct net_device *dev );
336 static struct net_device_stats *lance_get_stats( struct net_device *dev );
337 static void set_multicast_list( struct net_device *dev );
338 static int lance_set_mac_address( struct net_device *dev, void *addr );
339
340 /************************* End of Prototypes **************************/
341
342 /* Network traffic statistic (bytes) */
343
344 int lance_stat = 0;
345
346 static void update_lance_stat (int len) {
347 lance_stat += len;
348 }
349
350 /*
351 This function is used to access Baget/Lance memory to avoid
352 8/32BIT access to VAC A24 space
353 ALL memcpy calls was chenged to this function to avoid dbe problems
354 Don't confuse with function name -- it stays from original code
355 */
356
357 void *slow_memcpy( void *dst, const void *src, size_t len )
358
359 {
360 unsigned long to = (unsigned long)dst;
361 unsigned long from = (unsigned long)src;
362 unsigned long to_end = to +len;
363
364 /* Unaligned flags */
365
366 int odd_from = from & 1;
367 int odd_to = to & 1;
368 int odd_to_end = to_end & 1;
369
370 /* Align for 16BIT-access first */
371
372 register unsigned short *from_a = (unsigned short*) (from & ~1);
373 register unsigned short *to_a = (unsigned short*) (to & ~1);
374 register unsigned short *to_end_a = (unsigned short*) (to_end & ~1);
375
376 /* Caching values -- not in loop invariant */
377
378 register unsigned short from_v;
379 register unsigned short to_v;
380
381 /* Invariant is: from_a and to_a are pointers before or exactly to
382 currently copying byte */
383
384 if (odd_to) {
385 /* First byte unaligned case */
386 from_v = *from_a;
387 to_v = *to_a;
388
389 to_v &= ~0xff;
390 to_v |= 0xff & (from_v >> (odd_from ? 0 : 8));
391 *to_a++ = to_v;
392
393 if (odd_from) from_a++;
394 }
395 if (odd_from == odd_to) {
396 /* Same parity */
397 while (to_a + 7 < to_end_a) {
398 unsigned long dummy1, dummy2;
399 unsigned long reg1, reg2, reg3, reg4;
400
401 __asm__ __volatile__(
402 ".set\tnoreorder\n\t"
403 ".set\tnoat\n\t"
404 "lh\t%2,0(%1)\n\t"
405 "nop\n\t"
406 "lh\t%3,2(%1)\n\t"
407 "sh\t%2,0(%0)\n\t"
408 "lh\t%4,4(%1)\n\t"
409 "sh\t%3,2(%0)\n\t"
410 "lh\t%5,6(%1)\n\t"
411 "sh\t%4,4(%0)\n\t"
412 "lh\t%2,8(%1)\n\t"
413 "sh\t%5,6(%0)\n\t"
414 "lh\t%3,10(%1)\n\t"
415 "sh\t%2,8(%0)\n\t"
416 "lh\t%4,12(%1)\n\t"
417 "sh\t%3,10(%0)\n\t"
418 "lh\t%5,14(%1)\n\t"
419 "sh\t%4,12(%0)\n\t"
420 "nop\n\t"
421 "sh\t%5,14(%0)\n\t"
422 ".set\tat\n\t"
423 ".set\treorder"
424 :"=r" (dummy1), "=r" (dummy2),
425 "=&r" (reg1), "=&r" (reg2), "=&r" (reg3), "=&r" (reg4)
426 :"0" (to_a), "1" (from_a)
427 :"memory");
428
429 to_a += 8;
430 from_a += 8;
431
432 }
433 while (to_a < to_end_a) {
434 *to_a++ = *from_a++;
435 }
436 } else {
437 /* Different parity */
438 from_v = *from_a;
439 while (to_a < to_end_a) {
440 unsigned short from_v_next;
441 from_v_next = *++from_a;
442 *to_a++ = ((from_v & 0xff)<<8) | ((from_v_next>>8) & 0xff);
443 from_v = from_v_next;
444 }
445
446 }
447 if (odd_to_end) {
448 /* Last byte unaligned case */
449 to_v = *to_a;
450 from_v = *from_a;
451
452 to_v &= ~0xff00;
453 if (odd_from == odd_to) {
454 to_v |= from_v & 0xff00;
455 } else {
456 to_v |= (from_v<<8) & 0xff00;
457 }
458
459 *to_a = to_v;
460 }
461
462 update_lance_stat( len );
463
464 return( dst );
465 }
466
467
468 struct net_device * __init bagetlance_probe(int unit)
469 {
470 struct net_device *dev;
471 int i;
472 static int found;
473 int err = -ENODEV;
474
475 if (found)
476 /* Assume there's only one board possible... That seems true, since
477 * the Riebl/PAM board's address cannot be changed. */
478 return ERR_PTR(-ENODEV);
479
480 dev = alloc_etherdev(sizeof(struct lance_private));
481 if (!dev)
482 return ERR_PTR(-ENOMEM);
483
484 SET_MODULE_OWNER(dev);
485
486 for( i = 0; i < N_LANCE_ADDR; ++i ) {
487 if (lance_probe1( dev, &lance_addr_list[i] )) {
488 found = 1;
489 break;
490 }
491 }
492 if (!found)
493 goto out;
494 err = register_netdev(dev);
495 if (err)
496 goto out1;
497 return dev;
498 out1:
499 free_irq(dev->irq, dev);
500 out:
501 free_netdev(dev);
502 return ERR_PTR(err);
503 }
504
505 /* Derived from hwreg_present() in vme/config.c: */
506
507 static int __init addr_accessible( volatile void *regp,
508 int wordflag,
509 int writeflag )
510 {
511 /* We have a fine function to do it */
512 extern int try_read(unsigned long, int);
513 return try_read((unsigned long)regp, sizeof(short)) != -1;
514 }
515
516
517
518 /* Original atari driver uses it */
519 #define IRQ_TYPE_PRIO SA_INTERRUPT
520 #define IRQ_SOURCE_TO_VECTOR(x) (x)
521
522 static int __init lance_probe1( struct net_device *dev,
523 struct lance_addr *init_rec )
524
525 { volatile unsigned short *memaddr =
526 (volatile unsigned short *)init_rec->memaddr;
527 volatile unsigned short *ioaddr =
528 (volatile unsigned short *)init_rec->ioaddr;
529 struct lance_private *lp;
530 struct lance_ioreg *IO;
531 int i;
532 static int did_version;
533 unsigned short save1, save2;
534
535 PROBE_PRINT(( "Probing for Lance card at mem %#lx io %#lx\n",
536 (long)memaddr, (long)ioaddr ));
537
538 /* Test whether memory readable and writable */
539 PROBE_PRINT(( "lance_probe1: testing memory to be accessible\n" ));
540 if (!addr_accessible( memaddr, 1, 1 )) goto probe_fail;
541
542 if ((unsigned long)memaddr >= KSEG2) {
543 /* FIXME: do we need to undo that on cleanup paths? */
544 extern int kseg2_alloc_io (unsigned long addr, unsigned long size);
545 if (kseg2_alloc_io((unsigned long)memaddr, BAGET_LANCE_MEM_SIZE)) {
546 printk("bagetlance: unable map lance memory\n");
547 goto probe_fail;
548 }
549 }
550
551 /* Written values should come back... */
552 PROBE_PRINT(( "lance_probe1: testing memory to be writable (1)\n" ));
553 save1 = *memaddr;
554 *memaddr = 0x0001;
555 if (*memaddr != 0x0001) goto probe_fail;
556 PROBE_PRINT(( "lance_probe1: testing memory to be writable (2)\n" ));
557 *memaddr = 0x0000;
558 if (*memaddr != 0x0000) goto probe_fail;
559 *memaddr = save1;
560
561 /* First port should be readable and writable */
562 PROBE_PRINT(( "lance_probe1: testing ioport to be accessible\n" ));
563 if (!addr_accessible( ioaddr, 1, 1 )) goto probe_fail;
564
565 /* and written values should be readable */
566 PROBE_PRINT(( "lance_probe1: testing ioport to be writeable\n" ));
567 save2 = ioaddr[1];
568 ioaddr[1] = 0x0001;
569 if (ioaddr[1] != 0x0001) goto probe_fail;
570
571 /* The CSR0_INIT bit should not be readable */
572 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (1)\n" ));
573 save1 = ioaddr[0];
574 ioaddr[1] = CSR0;
575 ioaddr[0] = CSR0_INIT | CSR0_STOP;
576 if (ioaddr[0] != CSR0_STOP) {
577 ioaddr[0] = save1;
578 ioaddr[1] = save2;
579 goto probe_fail;
580 }
581 PROBE_PRINT(( "lance_probe1: testing CSR0 register function (2)\n" ));
582 ioaddr[0] = CSR0_STOP;
583 if (ioaddr[0] != CSR0_STOP) {
584 ioaddr[0] = save1;
585 ioaddr[1] = save2;
586 goto probe_fail;
587 }
588
589 /* Now ok... */
590 PROBE_PRINT(( "lance_probe1: Lance card detected\n" ));
591 goto probe_ok;
592
593 probe_fail:
594 return( 0 );
595
596 probe_ok:
597 lp = netdev_priv(dev);
598 MEM = (struct lance_memory *)memaddr;
599 IO = lp->iobase = (struct lance_ioreg *)ioaddr;
600 dev->base_addr = (unsigned long)ioaddr; /* informational only */
601 lp->memcpy_f = init_rec->slow_flag ? slow_memcpy : memcpy;
602
603 REGA( CSR0 ) = CSR0_STOP;
604
605 /* Now test for type: If the eeprom I/O port is readable, it is a
606 * PAM card */
607 if (addr_accessible( &(IO->eeprom), 0, 0 )) {
608 /* Switch back to Ram */
609 i = IO->mem;
610 lp->cardtype = PAM_CARD;
611 }
612 #ifdef NORMAL_MEM_ACCESS
613 else if (*RIEBL_MAGIC_ADDR == RIEBL_MAGIC) {
614 #else
615 else if (({
616 unsigned short *a = (unsigned short*)RIEBL_MAGIC_ADDR;
617 (((int)a[0]) << 16) + ((int)a[1]) == RIEBL_MAGIC;
618 })) {
619 #endif
620 lp->cardtype = NEW_RIEBL;
621 }
622 else
623 lp->cardtype = OLD_RIEBL;
624
625 if (lp->cardtype == PAM_CARD ||
626 memaddr == (unsigned short *)0xffe00000) {
627 /* PAMs card and Riebl on ST use level 5 autovector */
628 if (request_irq(BAGET_LANCE_IRQ, lance_interrupt, IRQ_TYPE_PRIO,
629 "PAM/Riebl-ST Ethernet", dev))
630 goto probe_fail;
631 dev->irq = (unsigned short)BAGET_LANCE_IRQ;
632 }
633 else {
634 /* For VME-RieblCards, request a free VME int;
635 * (This must be unsigned long, since dev->irq is short and the
636 * IRQ_MACHSPEC bit would be cut off...)
637 */
638 unsigned long irq = BAGET_LANCE_IRQ;
639 if (!irq) {
640 printk( "Lance: request for VME interrupt failed\n" );
641 goto probe_fail;
642 }
643 if (request_irq(irq, lance_interrupt, IRQ_TYPE_PRIO,
644 "Riebl-VME Ethernet", dev))
645 goto probe_fail;
646 dev->irq = irq;
647 }
648
649 printk("%s: %s at io %#lx, mem %#lx, irq %d%s, hwaddr ",
650 dev->name, lance_names[lp->cardtype],
651 (unsigned long)ioaddr,
652 (unsigned long)memaddr,
653 dev->irq,
654 init_rec->slow_flag ? " (slow memcpy)" : "" );
655
656 /* Get the ethernet address */
657 switch( lp->cardtype ) {
658 case OLD_RIEBL:
659 /* No ethernet address! (Set some default address) */
660 slow_memcpy( dev->dev_addr, OldRieblDefHwaddr, 6 );
661 break;
662 case NEW_RIEBL:
663 lp->memcpy_f( dev->dev_addr, RIEBL_HWADDR_ADDR, 6 );
664 break;
665 case PAM_CARD:
666 i = IO->eeprom;
667 for( i = 0; i < 6; ++i )
668 dev->dev_addr[i] =
669 ((((unsigned short *)MEM)[i*2] & 0x0f) << 4) |
670 ((((unsigned short *)MEM)[i*2+1] & 0x0f));
671 i = IO->mem;
672 break;
673 }
674 for( i = 0; i < 6; ++i )
675 printk( "%02x%s", dev->dev_addr[i], (i < 5) ? ":" : "\n" );
676 if (lp->cardtype == OLD_RIEBL) {
677 printk( "%s: Warning: This is a default ethernet address!\n",
678 dev->name );
679 printk( " Use \"ifconfig hw ether ...\" to set the address.\n" );
680 }
681
682 MEM->init.mode = 0x0000; /* Disable Rx and Tx. */
683
684 {
685 unsigned char hwaddr[6];
686 for( i = 0; i < 6; i++ )
687 hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
688 slow_memcpy(MEM->init.hwaddr, hwaddr, sizeof(hwaddr));
689 }
690
691 MEM->init.filter[0] = 0x00000000;
692 MEM->init.filter[1] = 0x00000000;
693 MEM->init.rx_ring.adr_lo = offsetof( struct lance_memory, rx_head );
694
695 #ifdef NORMAL_MEM_ACCESS
696 MEM->init.rx_ring.adr_hi = LANCE_HI_BASE;
697 MEM->init.rx_ring.len = RX_RING_LEN_BITS;
698 #else
699 MEM->init.rx_ring.len_adr_hi =
700 ((unsigned)RX_RING_LEN_BITS << 8) | LANCE_HI_BASE;
701 #endif
702
703
704 MEM->init.tx_ring.adr_lo = offsetof( struct lance_memory, tx_head );
705
706 #ifdef NORMAL_MEM_ACCESS
707 MEM->init.tx_ring.adr_hi = LANCE_HI_BASE;
708 MEM->init.tx_ring.len = TX_RING_LEN_BITS;
709 #else
710 MEM->init.tx_ring.len_adr_hi =
711 ((unsigned)TX_RING_LEN_BITS<<8) | LANCE_HI_BASE;
712 #endif
713
714 if (lp->cardtype == PAM_CARD)
715 IO->ivec = IRQ_SOURCE_TO_VECTOR(dev->irq);
716 else
717 *RIEBL_IVEC_ADDR = IRQ_SOURCE_TO_VECTOR(dev->irq);
718
719 if (did_version++ == 0)
720 DPRINTK( 1, ( version ));
721
722 /* The LANCE-specific entries in the device structure. */
723 dev->open = &lance_open;
724 dev->hard_start_xmit = &lance_start_xmit;
725 dev->stop = &lance_close;
726 dev->get_stats = &lance_get_stats;
727 dev->set_multicast_list = &set_multicast_list;
728 dev->set_mac_address = &lance_set_mac_address;
729 dev->start = 0;
730
731 memset( &lp->stats, 0, sizeof(lp->stats) );
732
733 return( 1 );
734 }
735
736
737 static int lance_open( struct net_device *dev )
738
739 { struct lance_private *lp = netdev_priv(dev);
740 struct lance_ioreg *IO = lp->iobase;
741 int i;
742
743 DPRINTK( 2, ( "%s: lance_open()\n", dev->name ));
744
745 lance_init_ring(dev);
746 /* Re-initialize the LANCE, and start it when done. */
747
748 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
749 REGA( CSR2 ) = 0;
750 REGA( CSR1 ) = 0;
751 REGA( CSR0 ) = CSR0_INIT;
752 /* From now on, AREG is kept to point to CSR0 */
753
754 i = 1000000;
755 while (--i > 0)
756 if (DREG & CSR0_IDON)
757 break;
758 if (i < 0 || (DREG & CSR0_ERR)) {
759 DPRINTK( 2, ( "lance_open(): opening %s failed, i=%d, csr0=%04x\n",
760 dev->name, i, DREG ));
761 DREG = CSR0_STOP;
762 return( -EIO );
763 }
764 DREG = CSR0_IDON;
765 DREG = CSR0_STRT;
766 DREG = CSR0_INEA;
767
768 dev->tbusy = 0;
769 dev->interrupt = 0;
770 dev->start = 1;
771
772 DPRINTK( 2, ( "%s: LANCE is open, csr0 %04x\n", dev->name, DREG ));
773 return( 0 );
774 }
775
776
777 /* Initialize the LANCE Rx and Tx rings. */
778
779 static void lance_init_ring( struct net_device *dev )
780
781 { struct lance_private *lp = netdev_priv(dev);
782 int i;
783 unsigned offset;
784
785 lp->lock = 0;
786 lp->tx_full = 0;
787 lp->cur_rx = lp->cur_tx = 0;
788 lp->dirty_tx = 0;
789
790 offset = offsetof( struct lance_memory, packet_area );
791
792 /* If the packet buffer at offset 'o' would conflict with the reserved area
793 * of RieblCards, advance it */
794 #define CHECK_OFFSET(o) \
795 do { \
796 if (lp->cardtype == OLD_RIEBL || lp->cardtype == NEW_RIEBL) { \
797 if (((o) < RIEBL_RSVD_START) ? (o)+PKT_BUF_SZ > RIEBL_RSVD_START \
798 : (o) < RIEBL_RSVD_END) \
799 (o) = RIEBL_RSVD_END; \
800 } \
801 } while(0)
802
803 for( i = 0; i < TX_RING_SIZE; i++ ) {
804 CHECK_OFFSET(offset);
805 MEM->tx_head[i].base = offset;
806 #ifdef NORMAL_MEM_ACCESS
807 MEM->tx_head[i].flag = TMD1_OWN_HOST;
808 MEM->tx_head[i].base_hi = LANCE_HI_BASE;
809 #else
810 MEM->tx_head[i].flag_base_hi =
811 (TMD1_OWN_HOST<<8) | LANCE_HI_BASE;
812 #endif
813 MEM->tx_head[i].length = 0;
814 MEM->tx_head[i].misc = 0;
815 offset += PKT_BUF_SZ;
816 }
817
818 for( i = 0; i < RX_RING_SIZE; i++ ) {
819 CHECK_OFFSET(offset);
820 MEM->rx_head[i].base = offset;
821 #ifdef NORMAL_MEM_ACCESS
822 MEM->rx_head[i].flag = TMD1_OWN_CHIP;
823 MEM->rx_head[i].base_hi = LANCE_HI_BASE;
824 #else
825 MEM->rx_head[i].flag_base_hi =
826 (TMD1_OWN_CHIP<<8) | LANCE_HI_BASE;
827 #endif
828 MEM->rx_head[i].buf_length = -PKT_BUF_SZ;
829 MEM->rx_head[i].msg_length = 0;
830 offset += PKT_BUF_SZ;
831 }
832 }
833
834
835 static int lance_start_xmit( struct sk_buff *skb, struct net_device *dev )
836
837 { struct lance_private *lp = netdev_priv(dev);
838 struct lance_ioreg *IO = lp->iobase;
839 int entry, len;
840 struct lance_tx_head *head;
841 unsigned long flags;
842
843 /* The old LANCE chips doesn't automatically pad buffers to min. size. */
844 len = (ETH_ZLEN < skb->len) ? skb->len : ETH_ZLEN;
845 /* PAM-Card has a bug: Can only send packets with even number of bytes! */
846 if (lp->cardtype == PAM_CARD && (len & 1))
847 ++len;
848
849 if (len > skb->len) {
850 skb = skb_padto(skb, len);
851 if (skb == NULL)
852 return 0;
853 }
854
855 /* Transmitter timeout, serious problems. */
856 if (dev->tbusy) {
857 int tickssofar = jiffies - dev->trans_start;
858 if (tickssofar < 20)
859 return( 1 );
860 AREG = CSR0;
861 DPRINTK( 1, ( "%s: transmit timed out, status %04x, resetting.\n",
862 dev->name, DREG ));
863 DREG = CSR0_STOP;
864 /*
865 * Always set BSWP after a STOP as STOP puts it back into
866 * little endian mode.
867 */
868 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
869 lp->stats.tx_errors++;
870 #ifndef final_version
871 { int i;
872 DPRINTK( 2, ( "Ring data: dirty_tx %d cur_tx %d%s cur_rx %d\n",
873 lp->dirty_tx, lp->cur_tx,
874 lp->tx_full ? " (full)" : "",
875 lp->cur_rx ));
876 for( i = 0 ; i < RX_RING_SIZE; i++ )
877 DPRINTK( 2, ( "rx #%d: base=%04x blen=%04x mlen=%04x\n",
878 i, MEM->rx_head[i].base,
879 -MEM->rx_head[i].buf_length,
880 MEM->rx_head[i].msg_length ));
881 for( i = 0 ; i < TX_RING_SIZE; i++ )
882 DPRINTK( 2, ( "tx #%d: base=%04x len=%04x misc=%04x\n",
883 i, MEM->tx_head[i].base,
884 -MEM->tx_head[i].length,
885 MEM->tx_head[i].misc ));
886 }
887 #endif
888 lance_init_ring(dev);
889 REGA( CSR0 ) = CSR0_INEA | CSR0_INIT | CSR0_STRT;
890
891 dev->tbusy = 0;
892 dev->trans_start = jiffies;
893
894 return( 0 );
895 }
896
897 DPRINTK( 2, ( "%s: lance_start_xmit() called, csr0 %4.4x.\n",
898 dev->name, DREG ));
899
900 /* Block a timer-based transmit from overlapping. This could better be
901 done with atomic_swap(1, dev->tbusy), but set_bit() works as well. */
902 if (test_and_set_bit( 0, (void*)&dev->tbusy ) != 0) {
903 DPRINTK( 0, ( "%s: Transmitter access conflict.\n", dev->name ));
904 return 1;
905 }
906
907 if (test_and_set_bit( 0, (void*)&lp->lock ) != 0) {
908 DPRINTK( 0, ( "%s: tx queue lock!.\n", dev->name ));
909 /* don't clear dev->tbusy flag. */
910 return 1;
911 }
912
913 /* Fill in a Tx ring entry */
914 if (lance_debug >= 3) {
915 u_char *p;
916 int i;
917 printk( "%s: TX pkt type 0x%04x from ", dev->name,
918 ((u_short *)skb->data)[6]);
919 for( p = &((u_char *)skb->data)[6], i = 0; i < 6; i++ )
920 printk("%02x%s", *p++, i != 5 ? ":" : "" );
921 printk(" to ");
922 for( p = (u_char *)skb->data, i = 0; i < 6; i++ )
923 printk("%02x%s", *p++, i != 5 ? ":" : "" );
924 printk(" data at 0x%08x len %d\n", (int)skb->data,
925 (int)skb->len );
926 }
927
928 /* We're not prepared for the int until the last flags are set/reset. And
929 * the int may happen already after setting the OWN_CHIP... */
930 save_flags(flags);
931 cli();
932
933 /* Mask to ring buffer boundary. */
934 entry = lp->cur_tx & TX_RING_MOD_MASK;
935 head = &(MEM->tx_head[entry]);
936
937 /* Caution: the write order is important here, set the "ownership" bits
938 * last.
939 */
940
941 head->length = -len;
942 head->misc = 0;
943 lp->memcpy_f( PKTBUF_ADDR(head), (void *)skb->data, skb->len );
944 #ifdef NORMAL_MEM_ACCESS
945 head->flag = TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP;
946 #else
947 SET_FLAG(head,(TMD1_OWN_CHIP | TMD1_ENP | TMD1_STP));
948 #endif
949 lp->stats.tx_bytes += skb->len;
950 dev_kfree_skb( skb );
951 lp->cur_tx++;
952 while( lp->cur_tx >= TX_RING_SIZE && lp->dirty_tx >= TX_RING_SIZE ) {
953 lp->cur_tx -= TX_RING_SIZE;
954 lp->dirty_tx -= TX_RING_SIZE;
955 }
956
957 /* Trigger an immediate send poll. */
958 DREG = CSR0_INEA | CSR0_TDMD;
959 dev->trans_start = jiffies;
960
961 lp->lock = 0;
962 #ifdef NORMAL_MEM_ACCESS
963 if ((MEM->tx_head[(entry+1) & TX_RING_MOD_MASK].flag & TMD1_OWN) ==
964 #else
965 if ((GET_FLAG(&MEM->tx_head[(entry+1) & TX_RING_MOD_MASK]) & TMD1_OWN) ==
966 #endif
967 TMD1_OWN_HOST)
968 dev->tbusy = 0;
969 else
970 lp->tx_full = 1;
971 restore_flags(flags);
972
973 return 0;
974 }
975
976 /* The LANCE interrupt handler. */
977
978 static irqreturn_t lance_interrupt( int irq, void *dev_id, struct pt_regs *fp)
979 {
980 struct net_device *dev = dev_id;
981 struct lance_private *lp;
982 struct lance_ioreg *IO;
983 int csr0, boguscnt = 10;
984 int handled = 0;
985
986 if (dev == NULL) {
987 DPRINTK( 1, ( "lance_interrupt(): interrupt for unknown device.\n" ));
988 return IRQ_NONE;
989 }
990
991 lp = netdev_priv(dev);
992 IO = lp->iobase;
993 AREG = CSR0;
994
995 if (dev->interrupt) {
996 DPRINTK( 1, ( "Re-entering CAUSE=%08x STATUS=%08x\n",
997 read_32bit_cp0_register(CP0_CAUSE),
998 read_32bit_cp0_register(CP0_STATUS) ));
999 panic("lance: interrupt handler reentered !");
1000 }
1001
1002 dev->interrupt = 1;
1003
1004 while( ((csr0 = DREG) & (CSR0_ERR | CSR0_TINT | CSR0_RINT)) &&
1005 --boguscnt >= 0) {
1006 handled = 1;
1007 /* Acknowledge all of the current interrupt sources ASAP. */
1008 DREG = csr0 & ~(CSR0_INIT | CSR0_STRT | CSR0_STOP |
1009 CSR0_TDMD | CSR0_INEA);
1010
1011 DPRINTK( 2, ( "%s: interrupt csr0=%04x new csr=%04x.\n",
1012 dev->name, csr0, DREG ));
1013
1014 if (csr0 & CSR0_RINT) /* Rx interrupt */
1015 lance_rx( dev );
1016
1017 if (csr0 & CSR0_TINT) { /* Tx-done interrupt */
1018 int dirty_tx = lp->dirty_tx;
1019
1020 while( dirty_tx < lp->cur_tx) {
1021 int entry = dirty_tx & TX_RING_MOD_MASK;
1022 #ifdef NORMAL_MEM_ACCESS
1023 int status = MEM->tx_head[entry].flag;
1024 #else
1025 int status = GET_FLAG(&MEM->tx_head[entry]);
1026 #endif
1027 if (status & TMD1_OWN_CHIP)
1028 break; /* It still hasn't been Txed */
1029
1030 #ifdef NORMAL_MEM_ACCESS
1031 MEM->tx_head[entry].flag = 0;
1032 #else
1033 SET_FLAG(&MEM->tx_head[entry],0);
1034 #endif
1035
1036 if (status & TMD1_ERR) {
1037 /* There was an major error, log it. */
1038 int err_status = MEM->tx_head[entry].misc;
1039 lp->stats.tx_errors++;
1040 if (err_status & TMD3_RTRY) lp->stats.tx_aborted_errors++;
1041 if (err_status & TMD3_LCAR) lp->stats.tx_carrier_errors++;
1042 if (err_status & TMD3_LCOL) lp->stats.tx_window_errors++;
1043 if (err_status & TMD3_UFLO) {
1044 /* Ackk! On FIFO errors the Tx unit is turned off! */
1045 lp->stats.tx_fifo_errors++;
1046 /* Remove this verbosity later! */
1047 DPRINTK( 1, ( "%s: Tx FIFO error! Status %04x\n",
1048 dev->name, csr0 ));
1049 /* Restart the chip. */
1050 DREG = CSR0_STRT;
1051 }
1052 } else {
1053 if (status & (TMD1_MORE | TMD1_ONE | TMD1_DEF))
1054 lp->stats.collisions++;
1055 lp->stats.tx_packets++;
1056 }
1057 dirty_tx++;
1058 }
1059
1060 #ifndef final_version
1061 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1062 DPRINTK( 0, ( "out-of-sync dirty pointer,"
1063 " %d vs. %d, full=%d.\n",
1064 dirty_tx, lp->cur_tx, lp->tx_full ));
1065 dirty_tx += TX_RING_SIZE;
1066 }
1067 #endif
1068
1069 if (lp->tx_full && dev->tbusy
1070 && dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1071 /* The ring is no longer full, clear tbusy. */
1072 lp->tx_full = 0;
1073 dev->tbusy = 0;
1074 mark_bh( NET_BH );
1075 }
1076
1077 lp->dirty_tx = dirty_tx;
1078 }
1079
1080 /* Log misc errors. */
1081 if (csr0 & CSR0_BABL) lp->stats.tx_errors++; /* Tx babble. */
1082 if (csr0 & CSR0_MISS) lp->stats.rx_errors++; /* Missed a Rx frame. */
1083 if (csr0 & CSR0_MERR) {
1084 DPRINTK( 1, ( "%s: Bus master arbitration failure (?!?), "
1085 "status %04x.\n", dev->name, csr0 ));
1086 /* Restart the chip. */
1087 DREG = CSR0_STRT;
1088 }
1089 }
1090
1091 /* Clear any other interrupt, and set interrupt enable. */
1092 DREG = CSR0_BABL | CSR0_CERR | CSR0_MISS | CSR0_MERR |
1093 CSR0_IDON | CSR0_INEA;
1094
1095 DPRINTK( 2, ( "%s: exiting interrupt, csr0=%#04x.\n",
1096 dev->name, DREG ));
1097 dev->interrupt = 0;
1098 return IRQ_RETVAL(handled);
1099 }
1100
1101
1102 static int lance_rx( struct net_device *dev )
1103
1104 { struct lance_private *lp = netdev_priv(dev);
1105 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1106 int i;
1107
1108 #ifdef NORMAL_MEM_ACCESS
1109 DPRINTK( 2, ( "%s: rx int, flag=%04x\n", dev->name,
1110 MEM->rx_head[entry].flag ));
1111 #else
1112 DPRINTK( 2, ( "%s: rx int, flag=%04x\n", dev->name,
1113 GET_FLAG(&MEM->rx_head[entry]) ));
1114 #endif
1115
1116 /* If we own the next entry, it's a new packet. Send it up. */
1117 #ifdef NORMAL_MEM_ACCESS
1118 while( (MEM->rx_head[entry].flag & RMD1_OWN) == RMD1_OWN_HOST ) {
1119 #else
1120 while( (GET_FLAG(&MEM->rx_head[entry]) & RMD1_OWN) == RMD1_OWN_HOST ) {
1121 #endif
1122 struct lance_rx_head *head = &(MEM->rx_head[entry]);
1123 #ifdef NORMAL_MEM_ACCESS
1124 int status = head->flag;
1125 #else
1126 int status = GET_FLAG(head);
1127 #endif
1128
1129 if (status != (RMD1_ENP|RMD1_STP)) { /* There was an error. */
1130 /* There is a tricky error noted by John Murphy,
1131 <murf@perftech.com> to Russ Nelson: Even with full-sized
1132 buffers it's possible for a jabber packet to use two
1133 buffers, with only the last correctly noting the error. */
1134 if (status & RMD1_ENP) /* Only count a general error at the */
1135 lp->stats.rx_errors++; /* end of a packet.*/
1136 if (status & RMD1_FRAM) lp->stats.rx_frame_errors++;
1137 if (status & RMD1_OFLO) lp->stats.rx_over_errors++;
1138 if (status & RMD1_CRC) lp->stats.rx_crc_errors++;
1139 if (status & RMD1_BUFF) lp->stats.rx_fifo_errors++;
1140 #ifdef NORMAL_MEM_ACCESS
1141 head->flag &= (RMD1_ENP|RMD1_STP);
1142 #else
1143 SET_FLAG(head,GET_FLAG(head) & (RMD1_ENP|RMD1_STP));
1144 #endif
1145 } else {
1146 /* Malloc up new buffer, compatible with net-3. */
1147 short pkt_len = head->msg_length & 0xfff;
1148 struct sk_buff *skb;
1149
1150 if (pkt_len < 60) {
1151 printk( "%s: Runt packet!\n", dev->name );
1152 lp->stats.rx_errors++;
1153 }
1154 else {
1155 skb = dev_alloc_skb( pkt_len+2 );
1156 if (skb == NULL) {
1157 DPRINTK( 1, ( "%s: Memory squeeze, deferring packet.\n",
1158 dev->name ));
1159 for( i = 0; i < RX_RING_SIZE; i++ )
1160 #ifdef NORMAL_MEM_ACCESS
1161 if (MEM->rx_head[(entry+i) & RX_RING_MOD_MASK].flag &
1162 #else
1163 if (GET_FLAG(&MEM->rx_head[(entry+i) & \
1164 RX_RING_MOD_MASK]) &
1165 #endif
1166 RMD1_OWN_CHIP)
1167 break;
1168
1169 if (i > RX_RING_SIZE - 2) {
1170 lp->stats.rx_dropped++;
1171 #ifdef NORMAL_MEM_ACCESS
1172 head->flag |= RMD1_OWN_CHIP;
1173 #else
1174 SET_FLAG(head,GET_FLAG(head) | RMD1_OWN_CHIP);
1175 #endif
1176 lp->cur_rx++;
1177 }
1178 break;
1179 }
1180
1181 if (lance_debug >= 3) {
1182 u_char *data = PKTBUF_ADDR(head), *p;
1183 printk( "%s: RX pkt type 0x%04x from ", dev->name,
1184 ((u_short *)data)[6]);
1185 for( p = &data[6], i = 0; i < 6; i++ )
1186 printk("%02x%s", *p++, i != 5 ? ":" : "" );
1187 printk(" to ");
1188 for( p = data, i = 0; i < 6; i++ )
1189 printk("%02x%s", *p++, i != 5 ? ":" : "" );
1190 printk(" data %02x %02x %02x %02x %02x %02x %02x %02x "
1191 "len %d\n",
1192 data[15], data[16], data[17], data[18],
1193 data[19], data[20], data[21], data[22],
1194 pkt_len );
1195 }
1196
1197 skb->dev = dev;
1198 skb_reserve( skb, 2 ); /* 16 byte align */
1199 skb_put( skb, pkt_len ); /* Make room */
1200 lp->memcpy_f( skb->data, PKTBUF_ADDR(head), pkt_len );
1201 skb->protocol = eth_type_trans( skb, dev );
1202 netif_rx( skb );
1203 dev->last_rx = jiffies;
1204 lp->stats.rx_packets++;
1205 lp->stats.rx_bytes += pkt_len;
1206 }
1207 }
1208
1209 #ifdef NORMAL_MEM_ACCESS
1210 head->flag |= RMD1_OWN_CHIP;
1211 #else
1212 SET_FLAG(head,GET_FLAG(head) | RMD1_OWN_CHIP);
1213 #endif
1214 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1215 }
1216 lp->cur_rx &= RX_RING_MOD_MASK;
1217
1218 /* From lance.c (Donald Becker): */
1219 /* We should check that at least two ring entries are free. If not,
1220 we should free one and mark stats->rx_dropped++. */
1221
1222 return 0;
1223 }
1224
1225
1226 static int lance_close( struct net_device *dev )
1227
1228 { struct lance_private *lp = netdev_priv(dev);
1229 struct lance_ioreg *IO = lp->iobase;
1230
1231 dev->start = 0;
1232 dev->tbusy = 1;
1233
1234 AREG = CSR0;
1235
1236 DPRINTK( 2, ( "%s: Shutting down ethercard, status was %2.2x.\n",
1237 dev->name, DREG ));
1238
1239 /* We stop the LANCE here -- it occasionally polls
1240 memory if we don't. */
1241 DREG = CSR0_STOP;
1242
1243 return 0;
1244 }
1245
1246
1247 static struct net_device_stats *lance_get_stats( struct net_device *dev )
1248
1249 {
1250 struct lance_private *lp = netdev_priv(dev);
1251 return &lp->stats;
1252 }
1253
1254
1255 /* Set or clear the multicast filter for this adaptor.
1256 num_addrs == -1 Promiscuous mode, receive all packets
1257 num_addrs == 0 Normal mode, clear multicast list
1258 num_addrs > 0 Multicast mode, receive normal and MC packets, and do
1259 best-effort filtering.
1260 */
1261
1262 static void set_multicast_list( struct net_device *dev )
1263
1264 { struct lance_private *lp = netdev_priv(dev);
1265 struct lance_ioreg *IO = lp->iobase;
1266
1267 if (!dev->start)
1268 /* Only possible if board is already started */
1269 return;
1270
1271 /* We take the simple way out and always enable promiscuous mode. */
1272 DREG = CSR0_STOP; /* Temporarily stop the lance. */
1273
1274 if (dev->flags & IFF_PROMISC) {
1275 /* Log any net taps. */
1276 DPRINTK( 1, ( "%s: Promiscuous mode enabled.\n", dev->name ));
1277 REGA( CSR15 ) = 0x8000; /* Set promiscuous mode */
1278 } else {
1279 short multicast_table[4];
1280 int num_addrs = dev->mc_count;
1281 int i;
1282 /* We don't use the multicast table, but rely on upper-layer
1283 * filtering. */
1284 memset( multicast_table, (num_addrs == 0) ? 0 : -1,
1285 sizeof(multicast_table) );
1286 for( i = 0; i < 4; i++ )
1287 REGA( CSR8+i ) = multicast_table[i];
1288 REGA( CSR15 ) = 0; /* Unset promiscuous mode */
1289 }
1290
1291 /*
1292 * Always set BSWP after a STOP as STOP puts it back into
1293 * little endian mode.
1294 */
1295 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0);
1296
1297 /* Resume normal operation and reset AREG to CSR0 */
1298 REGA( CSR0 ) = CSR0_IDON | CSR0_INEA | CSR0_STRT;
1299 }
1300
1301
1302 /* This is needed for old RieblCards and possible for new RieblCards */
1303
1304 static int lance_set_mac_address( struct net_device *dev, void *addr )
1305
1306 { struct lance_private *lp = netdev_priv(dev);
1307 struct sockaddr *saddr = addr;
1308 int i;
1309
1310 if (lp->cardtype != OLD_RIEBL && lp->cardtype != NEW_RIEBL)
1311 return( -EOPNOTSUPP );
1312
1313 if (dev->start) {
1314 /* Only possible while card isn't started */
1315 DPRINTK( 1, ( "%s: hwaddr can be set only while card isn't open.\n",
1316 dev->name ));
1317 return( -EIO );
1318 }
1319
1320 slow_memcpy( dev->dev_addr, saddr->sa_data, dev->addr_len );
1321
1322 {
1323 unsigned char hwaddr[6];
1324 for( i = 0; i < 6; i++ )
1325 hwaddr[i] = dev->dev_addr[i^1]; /* <- 16 bit swap! */
1326 slow_memcpy(MEM->init.hwaddr, hwaddr, sizeof(hwaddr));
1327 }
1328
1329 lp->memcpy_f( RIEBL_HWADDR_ADDR, dev->dev_addr, 6 );
1330 /* set also the magic for future sessions */
1331 #ifdef NORMAL_MEM_ACCESS
1332 *RIEBL_MAGIC_ADDR = RIEBL_MAGIC;
1333 #else
1334 {
1335 unsigned long magic = RIEBL_MAGIC;
1336 slow_memcpy(RIEBL_MAGIC_ADDR, &magic, sizeof(*RIEBL_MAGIC_ADDR));
1337 }
1338 #endif
1339 return( 0 );
1340 }
1341
1342
1343 #ifdef MODULE
1344 static struct net_device *bagetlance_dev;
1345
1346 int init_module(void)
1347 {
1348 bagetlance_dev = bagetlance_probe(-1);
1349 if (IS_ERR(bagetlance_dev))
1350 return PTR_ERR(bagetlance_dev);
1351 return 0;
1352 }
1353
1354 void cleanup_module(void)
1355 {
1356 unregister_netdev(bagetlance_dev);
1357 free_irq(bagetlance_dev->irq, bagetlance_dev);
1358 free_netdev(bagetlance_dev);
1359 }
1360
1361 #endif /* MODULE */
1362
1363 /*
1364 * Local variables:
1365 * c-indent-level: 4
1366 * tab-width: 4
1367 * End:
1368 */
MOXA 2.6.9 from sdlinux-moxaart.tgz