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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / drivers / net / 8139too.c
blob2a94719a4226a7f4d3d36d25a9838195de515d93
1 /*
2
3 8139too.c: A RealTek RTL-8139 Fast Ethernet driver for Linux.
4
5 Maintained by Jeff Garzik <jgarzik@pobox.com>
6 Copyright 2000-2002 Jeff Garzik
7
8 Much code comes from Donald Becker's rtl8139.c driver,
9 versions 1.13 and older. This driver was originally based
10 on rtl8139.c version 1.07. Header of rtl8139.c version 1.13:
11
12 -----<snip>-----
13
14 Written 1997-2001 by Donald Becker.
15 This software may be used and distributed according to the
16 terms of the GNU General Public License (GPL), incorporated
17 herein by reference. Drivers based on or derived from this
18 code fall under the GPL and must retain the authorship,
19 copyright and license notice. This file is not a complete
20 program and may only be used when the entire operating
21 system is licensed under the GPL.
22
23 This driver is for boards based on the RTL8129 and RTL8139
24 PCI ethernet chips.
25
26 The author may be reached as becker@scyld.com, or C/O Scyld
27 Computing Corporation 410 Severn Ave., Suite 210 Annapolis
28 MD 21403
29
30 Support and updates available at
31 http://www.scyld.com/network/rtl8139.html
32
33 Twister-tuning table provided by Kinston
34 <shangh@realtek.com.tw>.
35
36 -----<snip>-----
37
38 This software may be used and distributed according to the terms
39 of the GNU General Public License, incorporated herein by reference.
40
41 Contributors:
42
43 Donald Becker - he wrote the original driver, kudos to him!
44 (but please don't e-mail him for support, this isn't his driver)
45
46 Tigran Aivazian - bug fixes, skbuff free cleanup
47
48 Martin Mares - suggestions for PCI cleanup
49
50 David S. Miller - PCI DMA and softnet updates
51
52 Ernst Gill - fixes ported from BSD driver
53
54 Daniel Kobras - identified specific locations of
55 posted MMIO write bugginess
56
57 Gerard Sharp - bug fix, testing and feedback
58
59 David Ford - Rx ring wrap fix
60
61 Dan DeMaggio - swapped RTL8139 cards with me, and allowed me
62 to find and fix a crucial bug on older chipsets.
63
64 Donald Becker/Chris Butterworth/Marcus Westergren -
65 Noticed various Rx packet size-related buglets.
66
67 Santiago Garcia Mantinan - testing and feedback
68
69 Jens David - 2.2.x kernel backports
70
71 Martin Dennett - incredibly helpful insight on undocumented
72 features of the 8139 chips
73
74 Jean-Jacques Michel - bug fix
75
76 Tobias Ringström - Rx interrupt status checking suggestion
77
78 Andrew Morton - Clear blocked signals, avoid
79 buffer overrun setting current->comm.
80
81 Kalle Olavi Niemitalo - Wake-on-LAN ioctls
82
83 Robert Kuebel - Save kernel thread from dying on any signal.
84
85 Submitting bug reports:
86
87 "rtl8139-diag -mmmaaavvveefN" output
88 enable RTL8139_DEBUG below, and look at 'dmesg' or kernel log
89
90 */
91
92 #define DRV_NAME "8139too"
93 #define DRV_VERSION "0.9.27"
94
95
96 #include <linux/config.h>
97 #include <linux/module.h>
98 #include <linux/kernel.h>
99 #include <linux/compiler.h>
100 #include <linux/pci.h>
101 #include <linux/init.h>
102 #include <linux/ioport.h>
103 #include <linux/netdevice.h>
104 #include <linux/etherdevice.h>
105 #include <linux/rtnetlink.h>
106 #include <linux/delay.h>
107 #include <linux/ethtool.h>
108 #include <linux/mii.h>
109 #include <linux/completion.h>
110 #include <linux/crc32.h>
111 #include <linux/suspend.h>
112 #include <asm/io.h>
113 #include <asm/uaccess.h>
114 #include <asm/irq.h>
115
116 #define RTL8139_DRIVER_NAME DRV_NAME " Fast Ethernet driver " DRV_VERSION
117 #define PFX DRV_NAME ": "
118
119 /* Default Message level */
120 #define RTL8139_DEF_MSG_ENABLE (NETIF_MSG_DRV | \
121 NETIF_MSG_PROBE | \
122 NETIF_MSG_LINK)
123
124
125 /* enable PIO instead of MMIO, if CONFIG_8139TOO_PIO is selected */
126 #ifdef CONFIG_8139TOO_PIO
127 #define USE_IO_OPS 1
128 #endif
129
130 /* define to 1 to enable copious debugging info */
131 #undef RTL8139_DEBUG
132
133 /* define to 1 to disable lightweight runtime debugging checks */
134 #undef RTL8139_NDEBUG
135
136
137 #ifdef RTL8139_DEBUG
138 /* note: prints function name for you */
139 # define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
140 #else
141 # define DPRINTK(fmt, args...)
142 #endif
143
144 #ifdef RTL8139_NDEBUG
145 # define assert(expr) do {} while (0)
146 #else
147 # define assert(expr) \
148 if(unlikely(!(expr))) { \
149 printk(KERN_ERR "Assertion failed! %s,%s,%s,line=%d\n", \
150 #expr,__FILE__,__FUNCTION__,__LINE__); \
151 }
152 #endif
153
154
155 /* A few user-configurable values. */
156 /* media options */
157 #define MAX_UNITS 8
158 static int media[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
159 static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1};
160
161 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
162 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
163 static int multicast_filter_limit = 32;
164
165 /* bitmapped message enable number */
166 static int debug = -1;
167
168 /*
169 * Receive ring size
170 * Warning: 64K ring has hardware issues and may lock up.
171 */
172 #if defined(CONFIG_SH_DREAMCAST)
173 #define RX_BUF_IDX 1 /* 16K ring */
174 #else
175 #define RX_BUF_IDX 2 /* 32K ring */
176 #endif
177 #define RX_BUF_LEN (8192 << RX_BUF_IDX)
178 #define RX_BUF_PAD 16
179 #define RX_BUF_WRAP_PAD 2048 /* spare padding to handle lack of packet wrap */
180
181 #if RX_BUF_LEN == 65536
182 #define RX_BUF_TOT_LEN RX_BUF_LEN
183 #else
184 #define RX_BUF_TOT_LEN (RX_BUF_LEN + RX_BUF_PAD + RX_BUF_WRAP_PAD)
185 #endif
186
187 /* Number of Tx descriptor registers. */
188 #define NUM_TX_DESC 4
189
190 /* max supported ethernet frame size -- must be at least (dev->mtu+14+4).*/
191 #define MAX_ETH_FRAME_SIZE 1536
192
193 /* Size of the Tx bounce buffers -- must be at least (dev->mtu+14+4). */
194 #define TX_BUF_SIZE MAX_ETH_FRAME_SIZE
195 #define TX_BUF_TOT_LEN (TX_BUF_SIZE * NUM_TX_DESC)
196
197 /* PCI Tuning Parameters
198 Threshold is bytes transferred to chip before transmission starts. */
199 #define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
200
201 /* The following settings are log_2(bytes)-4: 0 == 16 bytes .. 6==1024, 7==end of packet. */
202 #define RX_FIFO_THRESH 7 /* Rx buffer level before first PCI xfer. */
203 #define RX_DMA_BURST 7 /* Maximum PCI burst, '6' is 1024 */
204 #define TX_DMA_BURST 6 /* Maximum PCI burst, '6' is 1024 */
205 #define TX_RETRY 8 /* 0-15. retries = 16 + (TX_RETRY * 16) */
206
207 /* Operational parameters that usually are not changed. */
208 /* Time in jiffies before concluding the transmitter is hung. */
209 #define TX_TIMEOUT (6*HZ)
210
211
212 enum {
213 HAS_MII_XCVR = 0x010000,
214 HAS_CHIP_XCVR = 0x020000,
215 HAS_LNK_CHNG = 0x040000,
216 };
217
218 #define RTL_NUM_STATS 4 /* number of ETHTOOL_GSTATS u64's */
219 #define RTL_REGS_VER 1 /* version of reg. data in ETHTOOL_GREGS */
220 #define RTL_MIN_IO_SIZE 0x80
221 #define RTL8139B_IO_SIZE 256
222
223 #define RTL8129_CAPS HAS_MII_XCVR
224 #define RTL8139_CAPS HAS_CHIP_XCVR|HAS_LNK_CHNG
225
226 typedef enum {
227 RTL8139 = 0,
228 RTL8129,
229 } board_t;
230
231
232 /* indexed by board_t, above */
233 static struct {
234 const char *name;
235 u32 hw_flags;
236 } board_info[] __devinitdata = {
237 { "RealTek RTL8139", RTL8139_CAPS },
238 { "RealTek RTL8129", RTL8129_CAPS },
239 };
240
241
242 static struct pci_device_id rtl8139_pci_tbl[] = {
243 {0x10ec, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
244 {0x10ec, 0x8138, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
245 {0x1113, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
246 {0x1500, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
247 {0x4033, 0x1360, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
248 {0x1186, 0x1300, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
249 {0x1186, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
250 {0x13d1, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
251 {0x1259, 0xa117, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
252 {0x1259, 0xa11e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
253 {0x14ea, 0xab06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
254 {0x14ea, 0xab07, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
255 {0x11db, 0x1234, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
256 {0x1432, 0x9130, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
257 {0x02ac, 0x1012, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
258 {0x018a, 0x0106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
259 {0x126c, 0x1211, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
260 {0x1743, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
261 {0x021b, 0x8139, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
262
263 #ifdef CONFIG_SH_SECUREEDGE5410
264 /* Bogus 8139 silicon reports 8129 without external PROM :-( */
265 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8139 },
266 #endif
267 #ifdef CONFIG_8139TOO_8129
268 {0x10ec, 0x8129, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RTL8129 },
269 #endif
270
271 /* some crazy cards report invalid vendor ids like
272 * 0x0001 here. The other ids are valid and constant,
273 * so we simply don't match on the main vendor id.
274 */
275 {PCI_ANY_ID, 0x8139, 0x10ec, 0x8139, 0, 0, RTL8139 },
276 {PCI_ANY_ID, 0x8139, 0x1186, 0x1300, 0, 0, RTL8139 },
277 {PCI_ANY_ID, 0x8139, 0x13d1, 0xab06, 0, 0, RTL8139 },
278
279 {0,}
280 };
281 MODULE_DEVICE_TABLE (pci, rtl8139_pci_tbl);
282
283 static struct {
284 const char str[ETH_GSTRING_LEN];
285 } ethtool_stats_keys[] = {
286 { "early_rx" },
287 { "tx_buf_mapped" },
288 { "tx_timeouts" },
289 { "rx_lost_in_ring" },
290 };
291
292 /* The rest of these values should never change. */
293
294 /* Symbolic offsets to registers. */
295 enum RTL8139_registers {
296 MAC0 = 0, /* Ethernet hardware address. */
297 MAR0 = 8, /* Multicast filter. */
298 TxStatus0 = 0x10, /* Transmit status (Four 32bit registers). */
299 TxAddr0 = 0x20, /* Tx descriptors (also four 32bit). */
300 RxBuf = 0x30,
301 ChipCmd = 0x37,
302 RxBufPtr = 0x38,
303 RxBufAddr = 0x3A,
304 IntrMask = 0x3C,
305 IntrStatus = 0x3E,
306 TxConfig = 0x40,
307 RxConfig = 0x44,
308 Timer = 0x48, /* A general-purpose counter. */
309 RxMissed = 0x4C, /* 24 bits valid, write clears. */
310 Cfg9346 = 0x50,
311 Config0 = 0x51,
312 Config1 = 0x52,
313 FlashReg = 0x54,
314 MediaStatus = 0x58,
315 Config3 = 0x59,
316 Config4 = 0x5A, /* absent on RTL-8139A */
317 HltClk = 0x5B,
318 MultiIntr = 0x5C,
319 TxSummary = 0x60,
320 BasicModeCtrl = 0x62,
321 BasicModeStatus = 0x64,
322 NWayAdvert = 0x66,
323 NWayLPAR = 0x68,
324 NWayExpansion = 0x6A,
325 /* Undocumented registers, but required for proper operation. */
326 FIFOTMS = 0x70, /* FIFO Control and test. */
327 CSCR = 0x74, /* Chip Status and Configuration Register. */
328 PARA78 = 0x78,
329 PARA7c = 0x7c, /* Magic transceiver parameter register. */
330 Config5 = 0xD8, /* absent on RTL-8139A */
331 };
332
333 enum ClearBitMasks {
334 MultiIntrClear = 0xF000,
335 ChipCmdClear = 0xE2,
336 Config1Clear = (1<<7)|(1<<6)|(1<<3)|(1<<2)|(1<<1),
337 };
338
339 enum ChipCmdBits {
340 CmdReset = 0x10,
341 CmdRxEnb = 0x08,
342 CmdTxEnb = 0x04,
343 RxBufEmpty = 0x01,
344 };
345
346 /* Interrupt register bits, using my own meaningful names. */
347 enum IntrStatusBits {
348 PCIErr = 0x8000,
349 PCSTimeout = 0x4000,
350 RxFIFOOver = 0x40,
351 RxUnderrun = 0x20,
352 RxOverflow = 0x10,
353 TxErr = 0x08,
354 TxOK = 0x04,
355 RxErr = 0x02,
356 RxOK = 0x01,
357
358 RxAckBits = RxFIFOOver | RxOverflow | RxOK,
359 };
360
361 enum TxStatusBits {
362 TxHostOwns = 0x2000,
363 TxUnderrun = 0x4000,
364 TxStatOK = 0x8000,
365 TxOutOfWindow = 0x20000000,
366 TxAborted = 0x40000000,
367 TxCarrierLost = 0x80000000,
368 };
369 enum RxStatusBits {
370 RxMulticast = 0x8000,
371 RxPhysical = 0x4000,
372 RxBroadcast = 0x2000,
373 RxBadSymbol = 0x0020,
374 RxRunt = 0x0010,
375 RxTooLong = 0x0008,
376 RxCRCErr = 0x0004,
377 RxBadAlign = 0x0002,
378 RxStatusOK = 0x0001,
379 };
380
381 /* Bits in RxConfig. */
382 enum rx_mode_bits {
383 AcceptErr = 0x20,
384 AcceptRunt = 0x10,
385 AcceptBroadcast = 0x08,
386 AcceptMulticast = 0x04,
387 AcceptMyPhys = 0x02,
388 AcceptAllPhys = 0x01,
389 };
390
391 /* Bits in TxConfig. */
392 enum tx_config_bits {
393 TxIFG1 = (1 << 25), /* Interframe Gap Time */
394 TxIFG0 = (1 << 24), /* Enabling these bits violates IEEE 802.3 */
395 TxLoopBack = (1 << 18) | (1 << 17), /* enable loopback test mode */
396 TxCRC = (1 << 16), /* DISABLE appending CRC to end of Tx packets */
397 TxClearAbt = (1 << 0), /* Clear abort (WO) */
398 TxDMAShift = 8, /* DMA burst value (0-7) is shifted this many bits */
399 TxRetryShift = 4, /* TXRR value (0-15) is shifted this many bits */
400
401 TxVersionMask = 0x7C800000, /* mask out version bits 30-26, 23 */
402 };
403
404 /* Bits in Config1 */
405 enum Config1Bits {
406 Cfg1_PM_Enable = 0x01,
407 Cfg1_VPD_Enable = 0x02,
408 Cfg1_PIO = 0x04,
409 Cfg1_MMIO = 0x08,
410 LWAKE = 0x10, /* not on 8139, 8139A */
411 Cfg1_Driver_Load = 0x20,
412 Cfg1_LED0 = 0x40,
413 Cfg1_LED1 = 0x80,
414 SLEEP = (1 << 1), /* only on 8139, 8139A */
415 PWRDN = (1 << 0), /* only on 8139, 8139A */
416 };
417
418 /* Bits in Config3 */
419 enum Config3Bits {
420 Cfg3_FBtBEn = (1 << 0), /* 1 = Fast Back to Back */
421 Cfg3_FuncRegEn = (1 << 1), /* 1 = enable CardBus Function registers */
422 Cfg3_CLKRUN_En = (1 << 2), /* 1 = enable CLKRUN */
423 Cfg3_CardB_En = (1 << 3), /* 1 = enable CardBus registers */
424 Cfg3_LinkUp = (1 << 4), /* 1 = wake up on link up */
425 Cfg3_Magic = (1 << 5), /* 1 = wake up on Magic Packet (tm) */
426 Cfg3_PARM_En = (1 << 6), /* 0 = software can set twister parameters */
427 Cfg3_GNTSel = (1 << 7), /* 1 = delay 1 clock from PCI GNT signal */
428 };
429
430 /* Bits in Config4 */
431 enum Config4Bits {
432 LWPTN = (1 << 2), /* not on 8139, 8139A */
433 };
434
435 /* Bits in Config5 */
436 enum Config5Bits {
437 Cfg5_PME_STS = (1 << 0), /* 1 = PCI reset resets PME_Status */
438 Cfg5_LANWake = (1 << 1), /* 1 = enable LANWake signal */
439 Cfg5_LDPS = (1 << 2), /* 0 = save power when link is down */
440 Cfg5_FIFOAddrPtr = (1 << 3), /* Realtek internal SRAM testing */
441 Cfg5_UWF = (1 << 4), /* 1 = accept unicast wakeup frame */
442 Cfg5_MWF = (1 << 5), /* 1 = accept multicast wakeup frame */
443 Cfg5_BWF = (1 << 6), /* 1 = accept broadcast wakeup frame */
444 };
445
446 enum RxConfigBits {
447 /* rx fifo threshold */
448 RxCfgFIFOShift = 13,
449 RxCfgFIFONone = (7 << RxCfgFIFOShift),
450
451 /* Max DMA burst */
452 RxCfgDMAShift = 8,
453 RxCfgDMAUnlimited = (7 << RxCfgDMAShift),
454
455 /* rx ring buffer length */
456 RxCfgRcv8K = 0,
457 RxCfgRcv16K = (1 << 11),
458 RxCfgRcv32K = (1 << 12),
459 RxCfgRcv64K = (1 << 11) | (1 << 12),
460
461 /* Disable packet wrap at end of Rx buffer. (not possible with 64k) */
462 RxNoWrap = (1 << 7),
463 };
464
465 /* Twister tuning parameters from RealTek.
466 Completely undocumented, but required to tune bad links on some boards. */
467 enum CSCRBits {
468 CSCR_LinkOKBit = 0x0400,
469 CSCR_LinkChangeBit = 0x0800,
470 CSCR_LinkStatusBits = 0x0f000,
471 CSCR_LinkDownOffCmd = 0x003c0,
472 CSCR_LinkDownCmd = 0x0f3c0,
473 };
474
475 enum Cfg9346Bits {
476 Cfg9346_Lock = 0x00,
477 Cfg9346_Unlock = 0xC0,
478 };
479
480 typedef enum {
481 CH_8139 = 0,
482 CH_8139_K,
483 CH_8139A,
484 CH_8139A_G,
485 CH_8139B,
486 CH_8130,
487 CH_8139C,
488 CH_8100,
489 CH_8100B_8139D,
490 CH_8101,
491 } chip_t;
492
493 enum chip_flags {
494 HasHltClk = (1 << 0),
495 HasLWake = (1 << 1),
496 };
497
498 #define HW_REVID(b30, b29, b28, b27, b26, b23, b22) \
499 (b30<<30 | b29<<29 | b28<<28 | b27<<27 | b26<<26 | b23<<23 | b22<<22)
500 #define HW_REVID_MASK HW_REVID(1, 1, 1, 1, 1, 1, 1)
501
502 /* directly indexed by chip_t, above */
503 const static struct {
504 const char *name;
505 u32 version; /* from RTL8139C/RTL8139D docs */
506 u32 flags;
507 } rtl_chip_info[] = {
508 { "RTL-8139",
509 HW_REVID(1, 0, 0, 0, 0, 0, 0),
510 HasHltClk,
511 },
512
513 { "RTL-8139 rev K",
514 HW_REVID(1, 1, 0, 0, 0, 0, 0),
515 HasHltClk,
516 },
517
518 { "RTL-8139A",
519 HW_REVID(1, 1, 1, 0, 0, 0, 0),
520 HasHltClk, /* XXX undocumented? */
521 },
522
523 { "RTL-8139A rev G",
524 HW_REVID(1, 1, 1, 0, 0, 1, 0),
525 HasHltClk, /* XXX undocumented? */
526 },
527
528 { "RTL-8139B",
529 HW_REVID(1, 1, 1, 1, 0, 0, 0),
530 HasLWake,
531 },
532
533 { "RTL-8130",
534 HW_REVID(1, 1, 1, 1, 1, 0, 0),
535 HasLWake,
536 },
537
538 { "RTL-8139C",
539 HW_REVID(1, 1, 1, 0, 1, 0, 0),
540 HasLWake,
541 },
542
543 { "RTL-8100",
544 HW_REVID(1, 1, 1, 1, 0, 1, 0),
545 HasLWake,
546 },
547
548 { "RTL-8100B/8139D",
549 HW_REVID(1, 1, 1, 0, 1, 0, 1),
550 HasLWake,
551 },
552
553 { "RTL-8101",
554 HW_REVID(1, 1, 1, 0, 1, 1, 1),
555 HasLWake,
556 },
557 };
558
559 struct rtl_extra_stats {
560 unsigned long early_rx;
561 unsigned long tx_buf_mapped;
562 unsigned long tx_timeouts;
563 unsigned long rx_lost_in_ring;
564 };
565
566 struct rtl8139_private {
567 void *mmio_addr;
568 int drv_flags;
569 struct pci_dev *pci_dev;
570 u32 pci_state[16];
571 u32 msg_enable;
572 struct net_device_stats stats;
573 unsigned char *rx_ring;
574 unsigned int cur_rx; /* Index into the Rx buffer of next Rx pkt. */
575 unsigned int tx_flag;
576 unsigned long cur_tx;
577 unsigned long dirty_tx;
578 unsigned char *tx_buf[NUM_TX_DESC]; /* Tx bounce buffers */
579 unsigned char *tx_bufs; /* Tx bounce buffer region. */
580 dma_addr_t rx_ring_dma;
581 dma_addr_t tx_bufs_dma;
582 signed char phys[4]; /* MII device addresses. */
583 char twistie, twist_row, twist_col; /* Twister tune state. */
584 unsigned int default_port:4; /* Last dev->if_port value. */
585 spinlock_t lock;
586 spinlock_t rx_lock;
587 chip_t chipset;
588 pid_t thr_pid;
589 wait_queue_head_t thr_wait;
590 struct completion thr_exited;
591 u32 rx_config;
592 struct rtl_extra_stats xstats;
593 int time_to_die;
594 struct mii_if_info mii;
595 unsigned int regs_len;
596 unsigned long fifo_copy_timeout;
597 };
598
599 MODULE_AUTHOR ("Jeff Garzik <jgarzik@pobox.com>");
600 MODULE_DESCRIPTION ("RealTek RTL-8139 Fast Ethernet driver");
601 MODULE_LICENSE("GPL");
602
603 MODULE_PARM (multicast_filter_limit, "i");
604 MODULE_PARM (media, "1-" __MODULE_STRING(MAX_UNITS) "i");
605 MODULE_PARM (full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
606 MODULE_PARM (debug, "i");
607 MODULE_PARM_DESC (debug, "8139too bitmapped message enable number");
608 MODULE_PARM_DESC (multicast_filter_limit, "8139too maximum number of filtered multicast addresses");
609 MODULE_PARM_DESC (media, "8139too: Bits 4+9: force full duplex, bit 5: 100Mbps");
610 MODULE_PARM_DESC (full_duplex, "8139too: Force full duplex for board(s) (1)");
611
612 static int read_eeprom (void *ioaddr, int location, int addr_len);
613 static int rtl8139_open (struct net_device *dev);
614 static int mdio_read (struct net_device *dev, int phy_id, int location);
615 static void mdio_write (struct net_device *dev, int phy_id, int location,
616 int val);
617 static void rtl8139_start_thread(struct net_device *dev);
618 static void rtl8139_tx_timeout (struct net_device *dev);
619 static void rtl8139_init_ring (struct net_device *dev);
620 static int rtl8139_start_xmit (struct sk_buff *skb,
621 struct net_device *dev);
622 static int rtl8139_poll(struct net_device *dev, int *budget);
623 #ifdef CONFIG_NET_POLL_CONTROLLER
624 static void rtl8139_poll_controller(struct net_device *dev);
625 #endif
626 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
627 struct pt_regs *regs);
628 static int rtl8139_close (struct net_device *dev);
629 static int netdev_ioctl (struct net_device *dev, struct ifreq *rq, int cmd);
630 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev);
631 static void rtl8139_set_rx_mode (struct net_device *dev);
632 static void __set_rx_mode (struct net_device *dev);
633 static void rtl8139_hw_start (struct net_device *dev);
634 static struct ethtool_ops rtl8139_ethtool_ops;
635
636 #ifdef USE_IO_OPS
637
638 #define RTL_R8(reg) inb (((unsigned long)ioaddr) + (reg))
639 #define RTL_R16(reg) inw (((unsigned long)ioaddr) + (reg))
640 #define RTL_R32(reg) ((unsigned long) inl (((unsigned long)ioaddr) + (reg)))
641 #define RTL_W8(reg, val8) outb ((val8), ((unsigned long)ioaddr) + (reg))
642 #define RTL_W16(reg, val16) outw ((val16), ((unsigned long)ioaddr) + (reg))
643 #define RTL_W32(reg, val32) outl ((val32), ((unsigned long)ioaddr) + (reg))
644 #define RTL_W8_F RTL_W8
645 #define RTL_W16_F RTL_W16
646 #define RTL_W32_F RTL_W32
647 #undef readb
648 #undef readw
649 #undef readl
650 #undef writeb
651 #undef writew
652 #undef writel
653 #define readb(addr) inb((unsigned long)(addr))
654 #define readw(addr) inw((unsigned long)(addr))
655 #define readl(addr) inl((unsigned long)(addr))
656 #define writeb(val,addr) outb((val),(unsigned long)(addr))
657 #define writew(val,addr) outw((val),(unsigned long)(addr))
658 #define writel(val,addr) outl((val),(unsigned long)(addr))
659
660 #else
661
662 /* write MMIO register, with flush */
663 /* Flush avoids rtl8139 bug w/ posted MMIO writes */
664 #define RTL_W8_F(reg, val8) do { writeb ((val8), ioaddr + (reg)); readb (ioaddr + (reg)); } while (0)
665 #define RTL_W16_F(reg, val16) do { writew ((val16), ioaddr + (reg)); readw (ioaddr + (reg)); } while (0)
666 #define RTL_W32_F(reg, val32) do { writel ((val32), ioaddr + (reg)); readl (ioaddr + (reg)); } while (0)
667
668
669 #define MMIO_FLUSH_AUDIT_COMPLETE 1
670 #if MMIO_FLUSH_AUDIT_COMPLETE
671
672 /* write MMIO register */
673 #define RTL_W8(reg, val8) writeb ((val8), ioaddr + (reg))
674 #define RTL_W16(reg, val16) writew ((val16), ioaddr + (reg))
675 #define RTL_W32(reg, val32) writel ((val32), ioaddr + (reg))
676
677 #else
678
679 /* write MMIO register, then flush */
680 #define RTL_W8 RTL_W8_F
681 #define RTL_W16 RTL_W16_F
682 #define RTL_W32 RTL_W32_F
683
684 #endif /* MMIO_FLUSH_AUDIT_COMPLETE */
685
686 /* read MMIO register */
687 #define RTL_R8(reg) readb (ioaddr + (reg))
688 #define RTL_R16(reg) readw (ioaddr + (reg))
689 #define RTL_R32(reg) ((unsigned long) readl (ioaddr + (reg)))
690
691 #endif /* USE_IO_OPS */
692
693
694 static const u16 rtl8139_intr_mask =
695 PCIErr | PCSTimeout | RxUnderrun | RxOverflow | RxFIFOOver |
696 TxErr | TxOK | RxErr | RxOK;
697
698 static const u16 rtl8139_norx_intr_mask =
699 PCIErr | PCSTimeout | RxUnderrun |
700 TxErr | TxOK | RxErr ;
701
702 #if RX_BUF_IDX == 0
703 static const unsigned int rtl8139_rx_config =
704 RxCfgRcv8K | RxNoWrap |
705 (RX_FIFO_THRESH << RxCfgFIFOShift) |
706 (RX_DMA_BURST << RxCfgDMAShift);
707 #elif RX_BUF_IDX == 1
708 static const unsigned int rtl8139_rx_config =
709 RxCfgRcv16K | RxNoWrap |
710 (RX_FIFO_THRESH << RxCfgFIFOShift) |
711 (RX_DMA_BURST << RxCfgDMAShift);
712 #elif RX_BUF_IDX == 2
713 static const unsigned int rtl8139_rx_config =
714 RxCfgRcv32K | RxNoWrap |
715 (RX_FIFO_THRESH << RxCfgFIFOShift) |
716 (RX_DMA_BURST << RxCfgDMAShift);
717 #elif RX_BUF_IDX == 3
718 static const unsigned int rtl8139_rx_config =
719 RxCfgRcv64K |
720 (RX_FIFO_THRESH << RxCfgFIFOShift) |
721 (RX_DMA_BURST << RxCfgDMAShift);
722 #else
723 #error "Invalid configuration for 8139_RXBUF_IDX"
724 #endif
725
726 static const unsigned int rtl8139_tx_config =
727 (TX_DMA_BURST << TxDMAShift) | (TX_RETRY << TxRetryShift);
728
729 static void __rtl8139_cleanup_dev (struct net_device *dev)
730 {
731 struct rtl8139_private *tp;
732 struct pci_dev *pdev;
733
734 assert (dev != NULL);
735 assert (dev->priv != NULL);
736
737 tp = dev->priv;
738 assert (tp->pci_dev != NULL);
739 pdev = tp->pci_dev;
740
741 #ifndef USE_IO_OPS
742 if (tp->mmio_addr)
743 iounmap (tp->mmio_addr);
744 #endif /* !USE_IO_OPS */
745
746 /* it's ok to call this even if we have no regions to free */
747 pci_release_regions (pdev);
748
749 free_netdev(dev);
750
751 pci_set_drvdata (pdev, NULL);
752 }
753
754
755 static void rtl8139_chip_reset (void *ioaddr)
756 {
757 int i;
758
759 /* Soft reset the chip. */
760 RTL_W8 (ChipCmd, CmdReset);
761
762 /* Check that the chip has finished the reset. */
763 for (i = 1000; i > 0; i--) {
764 barrier();
765 if ((RTL_R8 (ChipCmd) & CmdReset) == 0)
766 break;
767 udelay (10);
768 }
769 }
770
771
772 static int __devinit rtl8139_init_board (struct pci_dev *pdev,
773 struct net_device **dev_out)
774 {
775 void *ioaddr;
776 struct net_device *dev;
777 struct rtl8139_private *tp;
778 u8 tmp8;
779 int rc;
780 unsigned int i;
781 unsigned long pio_start, pio_end, pio_flags, pio_len;
782 unsigned long mmio_start, mmio_end, mmio_flags, mmio_len;
783 u32 version;
784
785 assert (pdev != NULL);
786
787 *dev_out = NULL;
788
789 /* dev and dev->priv zeroed in alloc_etherdev */
790 dev = alloc_etherdev (sizeof (*tp));
791 if (dev == NULL) {
792 printk (KERN_ERR PFX "%s: Unable to alloc new net device\n", pci_name(pdev));
793 return -ENOMEM;
794 }
795 SET_MODULE_OWNER(dev);
796 SET_NETDEV_DEV(dev, &pdev->dev);
797
798 tp = dev->priv;
799 tp->pci_dev = pdev;
800
801 /* enable device (incl. PCI PM wakeup and hotplug setup) */
802 rc = pci_enable_device (pdev);
803 if (rc)
804 goto err_out;
805
806 pio_start = pci_resource_start (pdev, 0);
807 pio_end = pci_resource_end (pdev, 0);
808 pio_flags = pci_resource_flags (pdev, 0);
809 pio_len = pci_resource_len (pdev, 0);
810
811 mmio_start = pci_resource_start (pdev, 1);
812 mmio_end = pci_resource_end (pdev, 1);
813 mmio_flags = pci_resource_flags (pdev, 1);
814 mmio_len = pci_resource_len (pdev, 1);
815
816 /* set this immediately, we need to know before
817 * we talk to the chip directly */
818 DPRINTK("PIO region size == 0x%02X\n", pio_len);
819 DPRINTK("MMIO region size == 0x%02lX\n", mmio_len);
820
821 #ifdef USE_IO_OPS
822 /* make sure PCI base addr 0 is PIO */
823 if (!(pio_flags & IORESOURCE_IO)) {
824 printk (KERN_ERR PFX "%s: region #0 not a PIO resource, aborting\n", pci_name(pdev));
825 rc = -ENODEV;
826 goto err_out;
827 }
828 /* check for weird/broken PCI region reporting */
829 if (pio_len < RTL_MIN_IO_SIZE) {
830 printk (KERN_ERR PFX "%s: Invalid PCI I/O region size(s), aborting\n", pci_name(pdev));
831 rc = -ENODEV;
832 goto err_out;
833 }
834 #else
835 /* make sure PCI base addr 1 is MMIO */
836 if (!(mmio_flags & IORESOURCE_MEM)) {
837 printk (KERN_ERR PFX "%s: region #1 not an MMIO resource, aborting\n", pci_name(pdev));
838 rc = -ENODEV;
839 goto err_out;
840 }
841 if (mmio_len < RTL_MIN_IO_SIZE) {
842 printk (KERN_ERR PFX "%s: Invalid PCI mem region size(s), aborting\n", pci_name(pdev));
843 rc = -ENODEV;
844 goto err_out;
845 }
846 #endif
847
848 rc = pci_request_regions (pdev, "8139too");
849 if (rc)
850 goto err_out;
851
852 /* enable PCI bus-mastering */
853 pci_set_master (pdev);
854
855 #ifdef USE_IO_OPS
856 ioaddr = (void *) pio_start;
857 dev->base_addr = pio_start;
858 tp->mmio_addr = ioaddr;
859 tp->regs_len = pio_len;
860 #else
861 /* ioremap MMIO region */
862 ioaddr = ioremap (mmio_start, mmio_len);
863 if (ioaddr == NULL) {
864 printk (KERN_ERR PFX "%s: cannot remap MMIO, aborting\n", pci_name(pdev));
865 rc = -EIO;
866 goto err_out;
867 }
868 dev->base_addr = (long) ioaddr;
869 tp->mmio_addr = ioaddr;
870 tp->regs_len = mmio_len;
871 #endif /* USE_IO_OPS */
872
873 /* Bring old chips out of low-power mode. */
874 RTL_W8 (HltClk, 'R');
875
876 /* check for missing/broken hardware */
877 if (RTL_R32 (TxConfig) == 0xFFFFFFFF) {
878 printk (KERN_ERR PFX "%s: Chip not responding, ignoring board\n",
879 pci_name(pdev));
880 rc = -EIO;
881 goto err_out;
882 }
883
884 /* identify chip attached to board */
885 version = RTL_R32 (TxConfig) & HW_REVID_MASK;
886 for (i = 0; i < ARRAY_SIZE (rtl_chip_info); i++)
887 if (version == rtl_chip_info[i].version) {
888 tp->chipset = i;
889 goto match;
890 }
891
892 /* if unknown chip, assume array element #0, original RTL-8139 in this case */
893 printk (KERN_DEBUG PFX "%s: unknown chip version, assuming RTL-8139\n",
894 pci_name(pdev));
895 printk (KERN_DEBUG PFX "%s: TxConfig = 0x%lx\n", pci_name(pdev), RTL_R32 (TxConfig));
896 tp->chipset = 0;
897
898 match:
899 DPRINTK ("chipset id (%d) == index %d, '%s'\n",
900 version, i, rtl_chip_info[i].name);
901
902 if (tp->chipset >= CH_8139B) {
903 u8 new_tmp8 = tmp8 = RTL_R8 (Config1);
904 DPRINTK("PCI PM wakeup\n");
905 if ((rtl_chip_info[tp->chipset].flags & HasLWake) &&
906 (tmp8 & LWAKE))
907 new_tmp8 &= ~LWAKE;
908 new_tmp8 |= Cfg1_PM_Enable;
909 if (new_tmp8 != tmp8) {
910 RTL_W8 (Cfg9346, Cfg9346_Unlock);
911 RTL_W8 (Config1, tmp8);
912 RTL_W8 (Cfg9346, Cfg9346_Lock);
913 }
914 if (rtl_chip_info[tp->chipset].flags & HasLWake) {
915 tmp8 = RTL_R8 (Config4);
916 if (tmp8 & LWPTN) {
917 RTL_W8 (Cfg9346, Cfg9346_Unlock);
918 RTL_W8 (Config4, tmp8 & ~LWPTN);
919 RTL_W8 (Cfg9346, Cfg9346_Lock);
920 }
921 }
922 } else {
923 DPRINTK("Old chip wakeup\n");
924 tmp8 = RTL_R8 (Config1);
925 tmp8 &= ~(SLEEP | PWRDN);
926 RTL_W8 (Config1, tmp8);
927 }
928
929 rtl8139_chip_reset (ioaddr);
930
931 *dev_out = dev;
932 return 0;
933
934 err_out:
935 __rtl8139_cleanup_dev (dev);
936 return rc;
937 }
938
939
940 static int __devinit rtl8139_init_one (struct pci_dev *pdev,
941 const struct pci_device_id *ent)
942 {
943 struct net_device *dev = NULL;
944 struct rtl8139_private *tp;
945 int i, addr_len, option;
946 void *ioaddr;
947 static int board_idx = -1;
948 u8 pci_rev;
949
950 assert (pdev != NULL);
951 assert (ent != NULL);
952
953 board_idx++;
954
955 /* when we're built into the kernel, the driver version message
956 * is only printed if at least one 8139 board has been found
957 */
958 #ifndef MODULE
959 {
960 static int printed_version;
961 if (!printed_version++)
962 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
963 }
964 #endif
965
966 pci_read_config_byte(pdev, PCI_REVISION_ID, &pci_rev);
967
968 if (pdev->vendor == PCI_VENDOR_ID_REALTEK &&
969 pdev->device == PCI_DEVICE_ID_REALTEK_8139 && pci_rev >= 0x20) {
970 printk(KERN_INFO PFX "pci dev %s (id %04x:%04x rev %02x) is an enhanced 8139C+ chip\n",
971 pci_name(pdev), pdev->vendor, pdev->device, pci_rev);
972 printk(KERN_INFO PFX "Use the \"8139cp\" driver for improved performance and stability.\n");
973 }
974
975 i = rtl8139_init_board (pdev, &dev);
976 if (i < 0)
977 return i;
978
979 assert (dev != NULL);
980 tp = dev->priv;
981 assert (tp != NULL);
982 ioaddr = tp->mmio_addr;
983 assert (ioaddr != NULL);
984
985 addr_len = read_eeprom (ioaddr, 0, 8) == 0x8129 ? 8 : 6;
986 for (i = 0; i < 3; i++)
987 ((u16 *) (dev->dev_addr))[i] =
988 le16_to_cpu (read_eeprom (ioaddr, i + 7, addr_len));
989
990 /* The Rtl8139-specific entries in the device structure. */
991 dev->open = rtl8139_open;
992 dev->hard_start_xmit = rtl8139_start_xmit;
993 dev->poll = rtl8139_poll;
994 dev->weight = 64;
995 dev->stop = rtl8139_close;
996 dev->get_stats = rtl8139_get_stats;
997 dev->set_multicast_list = rtl8139_set_rx_mode;
998 dev->do_ioctl = netdev_ioctl;
999 dev->ethtool_ops = &rtl8139_ethtool_ops;
1000 dev->tx_timeout = rtl8139_tx_timeout;
1001 dev->watchdog_timeo = TX_TIMEOUT;
1002 #ifdef CONFIG_NET_POLL_CONTROLLER
1003 dev->poll_controller = rtl8139_poll_controller;
1004 #endif
1005
1006 /* note: the hardware is not capable of sg/csum/highdma, however
1007 * through the use of skb_copy_and_csum_dev we enable these
1008 * features
1009 */
1010 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM | NETIF_F_HIGHDMA;
1011
1012 dev->irq = pdev->irq;
1013
1014 /* dev->priv/tp zeroed and aligned in alloc_etherdev */
1015 tp = dev->priv;
1016
1017 /* note: tp->chipset set in rtl8139_init_board */
1018 tp->drv_flags = board_info[ent->driver_data].hw_flags;
1019 tp->mmio_addr = ioaddr;
1020 tp->msg_enable =
1021 (debug < 0 ? RTL8139_DEF_MSG_ENABLE : ((1 << debug) - 1));
1022 spin_lock_init (&tp->lock);
1023 spin_lock_init (&tp->rx_lock);
1024 init_waitqueue_head (&tp->thr_wait);
1025 init_completion (&tp->thr_exited);
1026 tp->mii.dev = dev;
1027 tp->mii.mdio_read = mdio_read;
1028 tp->mii.mdio_write = mdio_write;
1029 tp->mii.phy_id_mask = 0x3f;
1030 tp->mii.reg_num_mask = 0x1f;
1031
1032 /* dev is fully set up and ready to use now */
1033 DPRINTK("about to register device named %s (%p)...\n", dev->name, dev);
1034 i = register_netdev (dev);
1035 if (i) goto err_out;
1036
1037 pci_set_drvdata (pdev, dev);
1038
1039 printk (KERN_INFO "%s: %s at 0x%lx, "
1040 "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
1041 "IRQ %d\n",
1042 dev->name,
1043 board_info[ent->driver_data].name,
1044 dev->base_addr,
1045 dev->dev_addr[0], dev->dev_addr[1],
1046 dev->dev_addr[2], dev->dev_addr[3],
1047 dev->dev_addr[4], dev->dev_addr[5],
1048 dev->irq);
1049
1050 printk (KERN_DEBUG "%s: Identified 8139 chip type '%s'\n",
1051 dev->name, rtl_chip_info[tp->chipset].name);
1052
1053 /* Find the connected MII xcvrs.
1054 Doing this in open() would allow detecting external xcvrs later, but
1055 takes too much time. */
1056 #ifdef CONFIG_8139TOO_8129
1057 if (tp->drv_flags & HAS_MII_XCVR) {
1058 int phy, phy_idx = 0;
1059 for (phy = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {
1060 int mii_status = mdio_read(dev, phy, 1);
1061 if (mii_status != 0xffff && mii_status != 0x0000) {
1062 u16 advertising = mdio_read(dev, phy, 4);
1063 tp->phys[phy_idx++] = phy;
1064 printk(KERN_INFO "%s: MII transceiver %d status 0x%4.4x "
1065 "advertising %4.4x.\n",
1066 dev->name, phy, mii_status, advertising);
1067 }
1068 }
1069 if (phy_idx == 0) {
1070 printk(KERN_INFO "%s: No MII transceivers found! Assuming SYM "
1071 "transceiver.\n",
1072 dev->name);
1073 tp->phys[0] = 32;
1074 }
1075 } else
1076 #endif
1077 tp->phys[0] = 32;
1078 tp->mii.phy_id = tp->phys[0];
1079
1080 /* The lower four bits are the media type. */
1081 option = (board_idx >= MAX_UNITS) ? 0 : media[board_idx];
1082 if (option > 0) {
1083 tp->mii.full_duplex = (option & 0x210) ? 1 : 0;
1084 tp->default_port = option & 0xFF;
1085 if (tp->default_port)
1086 tp->mii.force_media = 1;
1087 }
1088 if (board_idx < MAX_UNITS && full_duplex[board_idx] > 0)
1089 tp->mii.full_duplex = full_duplex[board_idx];
1090 if (tp->mii.full_duplex) {
1091 printk(KERN_INFO "%s: Media type forced to Full Duplex.\n", dev->name);
1092 /* Changing the MII-advertised media because might prevent
1093 re-connection. */
1094 tp->mii.force_media = 1;
1095 }
1096 if (tp->default_port) {
1097 printk(KERN_INFO " Forcing %dMbps %s-duplex operation.\n",
1098 (option & 0x20 ? 100 : 10),
1099 (option & 0x10 ? "full" : "half"));
1100 mdio_write(dev, tp->phys[0], 0,
1101 ((option & 0x20) ? 0x2000 : 0) | /* 100Mbps? */
1102 ((option & 0x10) ? 0x0100 : 0)); /* Full duplex? */
1103 }
1104
1105 /* Put the chip into low-power mode. */
1106 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1107 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
1108
1109 return 0;
1110
1111 err_out:
1112 __rtl8139_cleanup_dev (dev);
1113 return i;
1114 }
1115
1116
1117 static void __devexit rtl8139_remove_one (struct pci_dev *pdev)
1118 {
1119 struct net_device *dev = pci_get_drvdata (pdev);
1120 struct rtl8139_private *np;
1121
1122 assert (dev != NULL);
1123 np = dev->priv;
1124 assert (np != NULL);
1125
1126 unregister_netdev (dev);
1127
1128 __rtl8139_cleanup_dev (dev);
1129 }
1130
1131
1132 /* Serial EEPROM section. */
1133
1134 /* EEPROM_Ctrl bits. */
1135 #define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
1136 #define EE_CS 0x08 /* EEPROM chip select. */
1137 #define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
1138 #define EE_WRITE_0 0x00
1139 #define EE_WRITE_1 0x02
1140 #define EE_DATA_READ 0x01 /* EEPROM chip data out. */
1141 #define EE_ENB (0x80 | EE_CS)
1142
1143 /* Delay between EEPROM clock transitions.
1144 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
1145 */
1146
1147 #define eeprom_delay() readl(ee_addr)
1148
1149 /* The EEPROM commands include the alway-set leading bit. */
1150 #define EE_WRITE_CMD (5)
1151 #define EE_READ_CMD (6)
1152 #define EE_ERASE_CMD (7)
1153
1154 static int __devinit read_eeprom (void *ioaddr, int location, int addr_len)
1155 {
1156 int i;
1157 unsigned retval = 0;
1158 void *ee_addr = ioaddr + Cfg9346;
1159 int read_cmd = location | (EE_READ_CMD << addr_len);
1160
1161 writeb (EE_ENB & ~EE_CS, ee_addr);
1162 writeb (EE_ENB, ee_addr);
1163 eeprom_delay ();
1164
1165 /* Shift the read command bits out. */
1166 for (i = 4 + addr_len; i >= 0; i--) {
1167 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
1168 writeb (EE_ENB | dataval, ee_addr);
1169 eeprom_delay ();
1170 writeb (EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
1171 eeprom_delay ();
1172 }
1173 writeb (EE_ENB, ee_addr);
1174 eeprom_delay ();
1175
1176 for (i = 16; i > 0; i--) {
1177 writeb (EE_ENB | EE_SHIFT_CLK, ee_addr);
1178 eeprom_delay ();
1179 retval =
1180 (retval << 1) | ((readb (ee_addr) & EE_DATA_READ) ? 1 :
1181 0);
1182 writeb (EE_ENB, ee_addr);
1183 eeprom_delay ();
1184 }
1185
1186 /* Terminate the EEPROM access. */
1187 writeb (~EE_CS, ee_addr);
1188 eeprom_delay ();
1189
1190 return retval;
1191 }
1192
1193 /* MII serial management: mostly bogus for now. */
1194 /* Read and write the MII management registers using software-generated
1195 serial MDIO protocol.
1196 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
1197 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
1198 "overclocking" issues. */
1199 #define MDIO_DIR 0x80
1200 #define MDIO_DATA_OUT 0x04
1201 #define MDIO_DATA_IN 0x02
1202 #define MDIO_CLK 0x01
1203 #define MDIO_WRITE0 (MDIO_DIR)
1204 #define MDIO_WRITE1 (MDIO_DIR | MDIO_DATA_OUT)
1205
1206 #define mdio_delay(mdio_addr) readb(mdio_addr)
1207
1208
1209 static char mii_2_8139_map[8] = {
1210 BasicModeCtrl,
1211 BasicModeStatus,
1212 0,
1213 0,
1214 NWayAdvert,
1215 NWayLPAR,
1216 NWayExpansion,
1217 0
1218 };
1219
1220
1221 #ifdef CONFIG_8139TOO_8129
1222 /* Syncronize the MII management interface by shifting 32 one bits out. */
1223 static void mdio_sync (void *mdio_addr)
1224 {
1225 int i;
1226
1227 for (i = 32; i >= 0; i--) {
1228 writeb (MDIO_WRITE1, mdio_addr);
1229 mdio_delay (mdio_addr);
1230 writeb (MDIO_WRITE1 | MDIO_CLK, mdio_addr);
1231 mdio_delay (mdio_addr);
1232 }
1233 }
1234 #endif
1235
1236 static int mdio_read (struct net_device *dev, int phy_id, int location)
1237 {
1238 struct rtl8139_private *tp = dev->priv;
1239 int retval = 0;
1240 #ifdef CONFIG_8139TOO_8129
1241 void *mdio_addr = tp->mmio_addr + Config4;
1242 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
1243 int i;
1244 #endif
1245
1246 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1247 return location < 8 && mii_2_8139_map[location] ?
1248 readw (tp->mmio_addr + mii_2_8139_map[location]) : 0;
1249 }
1250
1251 #ifdef CONFIG_8139TOO_8129
1252 mdio_sync (mdio_addr);
1253 /* Shift the read command bits out. */
1254 for (i = 15; i >= 0; i--) {
1255 int dataval = (mii_cmd & (1 << i)) ? MDIO_DATA_OUT : 0;
1256
1257 writeb (MDIO_DIR | dataval, mdio_addr);
1258 mdio_delay (mdio_addr);
1259 writeb (MDIO_DIR | dataval | MDIO_CLK, mdio_addr);
1260 mdio_delay (mdio_addr);
1261 }
1262
1263 /* Read the two transition, 16 data, and wire-idle bits. */
1264 for (i = 19; i > 0; i--) {
1265 writeb (0, mdio_addr);
1266 mdio_delay (mdio_addr);
1267 retval = (retval << 1) | ((readb (mdio_addr) & MDIO_DATA_IN) ? 1 : 0);
1268 writeb (MDIO_CLK, mdio_addr);
1269 mdio_delay (mdio_addr);
1270 }
1271 #endif
1272
1273 return (retval >> 1) & 0xffff;
1274 }
1275
1276
1277 static void mdio_write (struct net_device *dev, int phy_id, int location,
1278 int value)
1279 {
1280 struct rtl8139_private *tp = dev->priv;
1281 #ifdef CONFIG_8139TOO_8129
1282 void *mdio_addr = tp->mmio_addr + Config4;
1283 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
1284 int i;
1285 #endif
1286
1287 if (phy_id > 31) { /* Really a 8139. Use internal registers. */
1288 void *ioaddr = tp->mmio_addr;
1289 if (location == 0) {
1290 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1291 RTL_W16 (BasicModeCtrl, value);
1292 RTL_W8 (Cfg9346, Cfg9346_Lock);
1293 } else if (location < 8 && mii_2_8139_map[location])
1294 RTL_W16 (mii_2_8139_map[location], value);
1295 return;
1296 }
1297
1298 #ifdef CONFIG_8139TOO_8129
1299 mdio_sync (mdio_addr);
1300
1301 /* Shift the command bits out. */
1302 for (i = 31; i >= 0; i--) {
1303 int dataval =
1304 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
1305 writeb (dataval, mdio_addr);
1306 mdio_delay (mdio_addr);
1307 writeb (dataval | MDIO_CLK, mdio_addr);
1308 mdio_delay (mdio_addr);
1309 }
1310 /* Clear out extra bits. */
1311 for (i = 2; i > 0; i--) {
1312 writeb (0, mdio_addr);
1313 mdio_delay (mdio_addr);
1314 writeb (MDIO_CLK, mdio_addr);
1315 mdio_delay (mdio_addr);
1316 }
1317 #endif
1318 }
1319
1320
1321 static int rtl8139_open (struct net_device *dev)
1322 {
1323 struct rtl8139_private *tp = dev->priv;
1324 int retval;
1325 void *ioaddr = tp->mmio_addr;
1326
1327 retval = request_irq (dev->irq, rtl8139_interrupt, SA_SHIRQ, dev->name, dev);
1328 if (retval)
1329 return retval;
1330
1331 tp->tx_bufs = pci_alloc_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1332 &tp->tx_bufs_dma);
1333 tp->rx_ring = pci_alloc_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1334 &tp->rx_ring_dma);
1335 if (tp->tx_bufs == NULL || tp->rx_ring == NULL) {
1336 free_irq(dev->irq, dev);
1337
1338 if (tp->tx_bufs)
1339 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
1340 tp->tx_bufs, tp->tx_bufs_dma);
1341 if (tp->rx_ring)
1342 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
1343 tp->rx_ring, tp->rx_ring_dma);
1344
1345 return -ENOMEM;
1346
1347 }
1348
1349 tp->mii.full_duplex = tp->mii.force_media;
1350 tp->tx_flag = (TX_FIFO_THRESH << 11) & 0x003f0000;
1351
1352 rtl8139_init_ring (dev);
1353 rtl8139_hw_start (dev);
1354 netif_start_queue (dev);
1355
1356 if (netif_msg_ifup(tp))
1357 printk(KERN_DEBUG "%s: rtl8139_open() ioaddr %#lx IRQ %d"
1358 " GP Pins %2.2x %s-duplex.\n",
1359 dev->name, pci_resource_start (tp->pci_dev, 1),
1360 dev->irq, RTL_R8 (MediaStatus),
1361 tp->mii.full_duplex ? "full" : "half");
1362
1363 rtl8139_start_thread(dev);
1364
1365 return 0;
1366 }
1367
1368
1369 static void rtl_check_media (struct net_device *dev, unsigned int init_media)
1370 {
1371 struct rtl8139_private *tp = dev->priv;
1372
1373 if (tp->phys[0] >= 0) {
1374 mii_check_media(&tp->mii, netif_msg_link(tp), init_media);
1375 }
1376 }
1377
1378 /* Start the hardware at open or resume. */
1379 static void rtl8139_hw_start (struct net_device *dev)
1380 {
1381 struct rtl8139_private *tp = dev->priv;
1382 void *ioaddr = tp->mmio_addr;
1383 u32 i;
1384 u8 tmp;
1385
1386 /* Bring old chips out of low-power mode. */
1387 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
1388 RTL_W8 (HltClk, 'R');
1389
1390 rtl8139_chip_reset (ioaddr);
1391
1392 /* unlock Config[01234] and BMCR register writes */
1393 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1394 /* Restore our idea of the MAC address. */
1395 RTL_W32_F (MAC0 + 0, cpu_to_le32 (*(u32 *) (dev->dev_addr + 0)));
1396 RTL_W32_F (MAC0 + 4, cpu_to_le32 (*(u32 *) (dev->dev_addr + 4)));
1397
1398 /* Must enable Tx/Rx before setting transfer thresholds! */
1399 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1400
1401 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1402 RTL_W32 (RxConfig, tp->rx_config);
1403
1404 /* Check this value: the documentation for IFG contradicts ifself. */
1405 RTL_W32 (TxConfig, rtl8139_tx_config);
1406
1407 tp->cur_rx = 0;
1408
1409 rtl_check_media (dev, 1);
1410
1411 if (tp->chipset >= CH_8139B) {
1412 /* Disable magic packet scanning, which is enabled
1413 * when PM is enabled in Config1. It can be reenabled
1414 * via ETHTOOL_SWOL if desired. */
1415 RTL_W8 (Config3, RTL_R8 (Config3) & ~Cfg3_Magic);
1416 }
1417
1418 DPRINTK("init buffer addresses\n");
1419
1420 /* Lock Config[01234] and BMCR register writes */
1421 RTL_W8 (Cfg9346, Cfg9346_Lock);
1422
1423 /* init Rx ring buffer DMA address */
1424 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1425
1426 /* init Tx buffer DMA addresses */
1427 for (i = 0; i < NUM_TX_DESC; i++)
1428 RTL_W32_F (TxAddr0 + (i * 4), tp->tx_bufs_dma + (tp->tx_buf[i] - tp->tx_bufs));
1429
1430 RTL_W32 (RxMissed, 0);
1431
1432 rtl8139_set_rx_mode (dev);
1433
1434 /* no early-rx interrupts */
1435 RTL_W16 (MultiIntr, RTL_R16 (MultiIntr) & MultiIntrClear);
1436
1437 /* make sure RxTx has started */
1438 tmp = RTL_R8 (ChipCmd);
1439 if ((!(tmp & CmdRxEnb)) || (!(tmp & CmdTxEnb)))
1440 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1441
1442 /* Enable all known interrupts by setting the interrupt mask. */
1443 RTL_W16 (IntrMask, rtl8139_intr_mask);
1444 }
1445
1446
1447 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1448 static void rtl8139_init_ring (struct net_device *dev)
1449 {
1450 struct rtl8139_private *tp = dev->priv;
1451 int i;
1452
1453 tp->cur_rx = 0;
1454 tp->cur_tx = 0;
1455 tp->dirty_tx = 0;
1456
1457 for (i = 0; i < NUM_TX_DESC; i++)
1458 tp->tx_buf[i] = &tp->tx_bufs[i * TX_BUF_SIZE];
1459 }
1460
1461
1462 /* This must be global for CONFIG_8139TOO_TUNE_TWISTER case */
1463 static int next_tick = 3 * HZ;
1464
1465 #ifndef CONFIG_8139TOO_TUNE_TWISTER
1466 static inline void rtl8139_tune_twister (struct net_device *dev,
1467 struct rtl8139_private *tp) {}
1468 #else
1469 enum TwisterParamVals {
1470 PARA78_default = 0x78fa8388,
1471 PARA7c_default = 0xcb38de43, /* param[0][3] */
1472 PARA7c_xxx = 0xcb38de43,
1473 };
1474
1475 static const unsigned long param[4][4] = {
1476 {0xcb39de43, 0xcb39ce43, 0xfb38de03, 0xcb38de43},
1477 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1478 {0xcb39de43, 0xcb39ce43, 0xcb39ce83, 0xcb39ce83},
1479 {0xbb39de43, 0xbb39ce43, 0xbb39ce83, 0xbb39ce83}
1480 };
1481
1482 static void rtl8139_tune_twister (struct net_device *dev,
1483 struct rtl8139_private *tp)
1484 {
1485 int linkcase;
1486 void *ioaddr = tp->mmio_addr;
1487
1488 /* This is a complicated state machine to configure the "twister" for
1489 impedance/echos based on the cable length.
1490 All of this is magic and undocumented.
1491 */
1492 switch (tp->twistie) {
1493 case 1:
1494 if (RTL_R16 (CSCR) & CSCR_LinkOKBit) {
1495 /* We have link beat, let us tune the twister. */
1496 RTL_W16 (CSCR, CSCR_LinkDownOffCmd);
1497 tp->twistie = 2; /* Change to state 2. */
1498 next_tick = HZ / 10;
1499 } else {
1500 /* Just put in some reasonable defaults for when beat returns. */
1501 RTL_W16 (CSCR, CSCR_LinkDownCmd);
1502 RTL_W32 (FIFOTMS, 0x20); /* Turn on cable test mode. */
1503 RTL_W32 (PARA78, PARA78_default);
1504 RTL_W32 (PARA7c, PARA7c_default);
1505 tp->twistie = 0; /* Bail from future actions. */
1506 }
1507 break;
1508 case 2:
1509 /* Read how long it took to hear the echo. */
1510 linkcase = RTL_R16 (CSCR) & CSCR_LinkStatusBits;
1511 if (linkcase == 0x7000)
1512 tp->twist_row = 3;
1513 else if (linkcase == 0x3000)
1514 tp->twist_row = 2;
1515 else if (linkcase == 0x1000)
1516 tp->twist_row = 1;
1517 else
1518 tp->twist_row = 0;
1519 tp->twist_col = 0;
1520 tp->twistie = 3; /* Change to state 2. */
1521 next_tick = HZ / 10;
1522 break;
1523 case 3:
1524 /* Put out four tuning parameters, one per 100msec. */
1525 if (tp->twist_col == 0)
1526 RTL_W16 (FIFOTMS, 0);
1527 RTL_W32 (PARA7c, param[(int) tp->twist_row]
1528 [(int) tp->twist_col]);
1529 next_tick = HZ / 10;
1530 if (++tp->twist_col >= 4) {
1531 /* For short cables we are done.
1532 For long cables (row == 3) check for mistune. */
1533 tp->twistie =
1534 (tp->twist_row == 3) ? 4 : 0;
1535 }
1536 break;
1537 case 4:
1538 /* Special case for long cables: check for mistune. */
1539 if ((RTL_R16 (CSCR) &
1540 CSCR_LinkStatusBits) == 0x7000) {
1541 tp->twistie = 0;
1542 break;
1543 } else {
1544 RTL_W32 (PARA7c, 0xfb38de03);
1545 tp->twistie = 5;
1546 next_tick = HZ / 10;
1547 }
1548 break;
1549 case 5:
1550 /* Retune for shorter cable (column 2). */
1551 RTL_W32 (FIFOTMS, 0x20);
1552 RTL_W32 (PARA78, PARA78_default);
1553 RTL_W32 (PARA7c, PARA7c_default);
1554 RTL_W32 (FIFOTMS, 0x00);
1555 tp->twist_row = 2;
1556 tp->twist_col = 0;
1557 tp->twistie = 3;
1558 next_tick = HZ / 10;
1559 break;
1560
1561 default:
1562 /* do nothing */
1563 break;
1564 }
1565 }
1566 #endif /* CONFIG_8139TOO_TUNE_TWISTER */
1567
1568 static inline void rtl8139_thread_iter (struct net_device *dev,
1569 struct rtl8139_private *tp,
1570 void *ioaddr)
1571 {
1572 int mii_lpa;
1573
1574 mii_lpa = mdio_read (dev, tp->phys[0], MII_LPA);
1575
1576 if (!tp->mii.force_media && mii_lpa != 0xffff) {
1577 int duplex = (mii_lpa & LPA_100FULL)
1578 || (mii_lpa & 0x01C0) == 0x0040;
1579 if (tp->mii.full_duplex != duplex) {
1580 tp->mii.full_duplex = duplex;
1581
1582 if (mii_lpa) {
1583 printk (KERN_INFO
1584 "%s: Setting %s-duplex based on MII #%d link"
1585 " partner ability of %4.4x.\n",
1586 dev->name,
1587 tp->mii.full_duplex ? "full" : "half",
1588 tp->phys[0], mii_lpa);
1589 } else {
1590 printk(KERN_INFO"%s: media is unconnected, link down, or incompatible connection\n",
1591 dev->name);
1592 }
1593 #if 0
1594 RTL_W8 (Cfg9346, Cfg9346_Unlock);
1595 RTL_W8 (Config1, tp->mii.full_duplex ? 0x60 : 0x20);
1596 RTL_W8 (Cfg9346, Cfg9346_Lock);
1597 #endif
1598 }
1599 }
1600
1601 next_tick = HZ * 60;
1602
1603 rtl8139_tune_twister (dev, tp);
1604
1605 DPRINTK ("%s: Media selection tick, Link partner %4.4x.\n",
1606 dev->name, RTL_R16 (NWayLPAR));
1607 DPRINTK ("%s: Other registers are IntMask %4.4x IntStatus %4.4x\n",
1608 dev->name, RTL_R16 (IntrMask), RTL_R16 (IntrStatus));
1609 DPRINTK ("%s: Chip config %2.2x %2.2x.\n",
1610 dev->name, RTL_R8 (Config0),
1611 RTL_R8 (Config1));
1612 }
1613
1614 static int rtl8139_thread (void *data)
1615 {
1616 struct net_device *dev = data;
1617 struct rtl8139_private *tp = dev->priv;
1618 unsigned long timeout;
1619
1620 daemonize("%s", dev->name);
1621 allow_signal(SIGTERM);
1622
1623 while (1) {
1624 timeout = next_tick;
1625 do {
1626 timeout = interruptible_sleep_on_timeout (&tp->thr_wait, timeout);
1627 /* make swsusp happy with our thread */
1628 if (current->flags & PF_FREEZE)
1629 refrigerator(PF_FREEZE);
1630 } while (!signal_pending (current) && (timeout > 0));
1631
1632 if (signal_pending (current)) {
1633 flush_signals(current);
1634 }
1635
1636 if (tp->time_to_die)
1637 break;
1638
1639 rtnl_lock ();
1640 rtl8139_thread_iter (dev, tp, tp->mmio_addr);
1641 rtnl_unlock ();
1642 }
1643
1644 complete_and_exit (&tp->thr_exited, 0);
1645 }
1646
1647 static void rtl8139_start_thread(struct net_device *dev)
1648 {
1649 struct rtl8139_private *tp = dev->priv;
1650
1651 tp->thr_pid = -1;
1652 tp->twistie = 0;
1653 tp->time_to_die = 0;
1654 if (tp->chipset == CH_8139_K)
1655 tp->twistie = 1;
1656 else if (tp->drv_flags & HAS_LNK_CHNG)
1657 return;
1658
1659 tp->thr_pid = kernel_thread(rtl8139_thread, dev, CLONE_FS|CLONE_FILES);
1660 if (tp->thr_pid < 0) {
1661 printk (KERN_WARNING "%s: unable to start kernel thread\n",
1662 dev->name);
1663 }
1664 }
1665
1666 static inline void rtl8139_tx_clear (struct rtl8139_private *tp)
1667 {
1668 tp->cur_tx = 0;
1669 tp->dirty_tx = 0;
1670
1671 /* XXX account for unsent Tx packets in tp->stats.tx_dropped */
1672 }
1673
1674
1675 static void rtl8139_tx_timeout (struct net_device *dev)
1676 {
1677 struct rtl8139_private *tp = dev->priv;
1678 void *ioaddr = tp->mmio_addr;
1679 int i;
1680 u8 tmp8;
1681 unsigned long flags;
1682
1683 printk (KERN_DEBUG "%s: Transmit timeout, status %2.2x %4.4x %4.4x "
1684 "media %2.2x.\n", dev->name, RTL_R8 (ChipCmd),
1685 RTL_R16(IntrStatus), RTL_R16(IntrMask), RTL_R8(MediaStatus));
1686 /* Emit info to figure out what went wrong. */
1687 printk (KERN_DEBUG "%s: Tx queue start entry %ld dirty entry %ld.\n",
1688 dev->name, tp->cur_tx, tp->dirty_tx);
1689 for (i = 0; i < NUM_TX_DESC; i++)
1690 printk (KERN_DEBUG "%s: Tx descriptor %d is %8.8lx.%s\n",
1691 dev->name, i, RTL_R32 (TxStatus0 + (i * 4)),
1692 i == tp->dirty_tx % NUM_TX_DESC ?
1693 " (queue head)" : "");
1694
1695 tp->xstats.tx_timeouts++;
1696
1697 /* disable Tx ASAP, if not already */
1698 tmp8 = RTL_R8 (ChipCmd);
1699 if (tmp8 & CmdTxEnb)
1700 RTL_W8 (ChipCmd, CmdRxEnb);
1701
1702 spin_lock(&tp->rx_lock);
1703 /* Disable interrupts by clearing the interrupt mask. */
1704 RTL_W16 (IntrMask, 0x0000);
1705
1706 /* Stop a shared interrupt from scavenging while we are. */
1707 spin_lock_irqsave (&tp->lock, flags);
1708 rtl8139_tx_clear (tp);
1709 spin_unlock_irqrestore (&tp->lock, flags);
1710
1711 /* ...and finally, reset everything */
1712 if (netif_running(dev)) {
1713 rtl8139_hw_start (dev);
1714 netif_wake_queue (dev);
1715 }
1716 spin_unlock(&tp->rx_lock);
1717 }
1718
1719
1720 static int rtl8139_start_xmit (struct sk_buff *skb, struct net_device *dev)
1721 {
1722 struct rtl8139_private *tp = dev->priv;
1723 void *ioaddr = tp->mmio_addr;
1724 unsigned int entry;
1725 unsigned int len = skb->len;
1726
1727 /* Calculate the next Tx descriptor entry. */
1728 entry = tp->cur_tx % NUM_TX_DESC;
1729
1730 /* Note: the chip doesn't have auto-pad! */
1731 if (likely(len < TX_BUF_SIZE)) {
1732 if (len < ETH_ZLEN)
1733 memset(tp->tx_buf[entry], 0, ETH_ZLEN);
1734 skb_copy_and_csum_dev(skb, tp->tx_buf[entry]);
1735 dev_kfree_skb(skb);
1736 } else {
1737 dev_kfree_skb(skb);
1738 tp->stats.tx_dropped++;
1739 return 0;
1740 }
1741
1742 spin_lock_irq(&tp->lock);
1743 RTL_W32_F (TxStatus0 + (entry * sizeof (u32)),
1744 tp->tx_flag | max(len, (unsigned int)ETH_ZLEN));
1745
1746 dev->trans_start = jiffies;
1747
1748 tp->cur_tx++;
1749 wmb();
1750
1751 if ((tp->cur_tx - NUM_TX_DESC) == tp->dirty_tx)
1752 netif_stop_queue (dev);
1753 spin_unlock_irq(&tp->lock);
1754
1755 if (netif_msg_tx_queued(tp))
1756 printk (KERN_DEBUG "%s: Queued Tx packet size %u to slot %d.\n",
1757 dev->name, len, entry);
1758
1759 return 0;
1760 }
1761
1762
1763 static void rtl8139_tx_interrupt (struct net_device *dev,
1764 struct rtl8139_private *tp,
1765 void *ioaddr)
1766 {
1767 unsigned long dirty_tx, tx_left;
1768
1769 assert (dev != NULL);
1770 assert (tp != NULL);
1771 assert (ioaddr != NULL);
1772
1773 dirty_tx = tp->dirty_tx;
1774 tx_left = tp->cur_tx - dirty_tx;
1775 while (tx_left > 0) {
1776 int entry = dirty_tx % NUM_TX_DESC;
1777 int txstatus;
1778
1779 txstatus = RTL_R32 (TxStatus0 + (entry * sizeof (u32)));
1780
1781 if (!(txstatus & (TxStatOK | TxUnderrun | TxAborted)))
1782 break; /* It still hasn't been Txed */
1783
1784 /* Note: TxCarrierLost is always asserted at 100mbps. */
1785 if (txstatus & (TxOutOfWindow | TxAborted)) {
1786 /* There was an major error, log it. */
1787 if (netif_msg_tx_err(tp))
1788 printk(KERN_DEBUG "%s: Transmit error, Tx status %8.8x.\n",
1789 dev->name, txstatus);
1790 tp->stats.tx_errors++;
1791 if (txstatus & TxAborted) {
1792 tp->stats.tx_aborted_errors++;
1793 RTL_W32 (TxConfig, TxClearAbt);
1794 RTL_W16 (IntrStatus, TxErr);
1795 wmb();
1796 }
1797 if (txstatus & TxCarrierLost)
1798 tp->stats.tx_carrier_errors++;
1799 if (txstatus & TxOutOfWindow)
1800 tp->stats.tx_window_errors++;
1801 } else {
1802 if (txstatus & TxUnderrun) {
1803 /* Add 64 to the Tx FIFO threshold. */
1804 if (tp->tx_flag < 0x00300000)
1805 tp->tx_flag += 0x00020000;
1806 tp->stats.tx_fifo_errors++;
1807 }
1808 tp->stats.collisions += (txstatus >> 24) & 15;
1809 tp->stats.tx_bytes += txstatus & 0x7ff;
1810 tp->stats.tx_packets++;
1811 }
1812
1813 dirty_tx++;
1814 tx_left--;
1815 }
1816
1817 #ifndef RTL8139_NDEBUG
1818 if (tp->cur_tx - dirty_tx > NUM_TX_DESC) {
1819 printk (KERN_ERR "%s: Out-of-sync dirty pointer, %ld vs. %ld.\n",
1820 dev->name, dirty_tx, tp->cur_tx);
1821 dirty_tx += NUM_TX_DESC;
1822 }
1823 #endif /* RTL8139_NDEBUG */
1824
1825 /* only wake the queue if we did work, and the queue is stopped */
1826 if (tp->dirty_tx != dirty_tx) {
1827 tp->dirty_tx = dirty_tx;
1828 mb();
1829 netif_wake_queue (dev);
1830 }
1831 }
1832
1833
1834 /* TODO: clean this up! Rx reset need not be this intensive */
1835 static void rtl8139_rx_err (u32 rx_status, struct net_device *dev,
1836 struct rtl8139_private *tp, void *ioaddr)
1837 {
1838 u8 tmp8;
1839 #ifdef CONFIG_8139_OLD_RX_RESET
1840 int tmp_work;
1841 #endif
1842
1843 if (netif_msg_rx_err (tp))
1844 printk(KERN_DEBUG "%s: Ethernet frame had errors, status %8.8x.\n",
1845 dev->name, rx_status);
1846 tp->stats.rx_errors++;
1847 if (!(rx_status & RxStatusOK)) {
1848 if (rx_status & RxTooLong) {
1849 DPRINTK ("%s: Oversized Ethernet frame, status %4.4x!\n",
1850 dev->name, rx_status);
1851 /* A.C.: The chip hangs here. */
1852 }
1853 if (rx_status & (RxBadSymbol | RxBadAlign))
1854 tp->stats.rx_frame_errors++;
1855 if (rx_status & (RxRunt | RxTooLong))
1856 tp->stats.rx_length_errors++;
1857 if (rx_status & RxCRCErr)
1858 tp->stats.rx_crc_errors++;
1859 } else {
1860 tp->xstats.rx_lost_in_ring++;
1861 }
1862
1863 #ifndef CONFIG_8139_OLD_RX_RESET
1864 tmp8 = RTL_R8 (ChipCmd);
1865 RTL_W8 (ChipCmd, tmp8 & ~CmdRxEnb);
1866 RTL_W8 (ChipCmd, tmp8);
1867 RTL_W32 (RxConfig, tp->rx_config);
1868 tp->cur_rx = 0;
1869 #else
1870 /* Reset the receiver, based on RealTek recommendation. (Bug?) */
1871
1872 /* disable receive */
1873 RTL_W8_F (ChipCmd, CmdTxEnb);
1874 tmp_work = 200;
1875 while (--tmp_work > 0) {
1876 udelay(1);
1877 tmp8 = RTL_R8 (ChipCmd);
1878 if (!(tmp8 & CmdRxEnb))
1879 break;
1880 }
1881 if (tmp_work <= 0)
1882 printk (KERN_WARNING PFX "rx stop wait too long\n");
1883 /* restart receive */
1884 tmp_work = 200;
1885 while (--tmp_work > 0) {
1886 RTL_W8_F (ChipCmd, CmdRxEnb | CmdTxEnb);
1887 udelay(1);
1888 tmp8 = RTL_R8 (ChipCmd);
1889 if ((tmp8 & CmdRxEnb) && (tmp8 & CmdTxEnb))
1890 break;
1891 }
1892 if (tmp_work <= 0)
1893 printk (KERN_WARNING PFX "tx/rx enable wait too long\n");
1894
1895 /* and reinitialize all rx related registers */
1896 RTL_W8_F (Cfg9346, Cfg9346_Unlock);
1897 /* Must enable Tx/Rx before setting transfer thresholds! */
1898 RTL_W8 (ChipCmd, CmdRxEnb | CmdTxEnb);
1899
1900 tp->rx_config = rtl8139_rx_config | AcceptBroadcast | AcceptMyPhys;
1901 RTL_W32 (RxConfig, tp->rx_config);
1902 tp->cur_rx = 0;
1903
1904 DPRINTK("init buffer addresses\n");
1905
1906 /* Lock Config[01234] and BMCR register writes */
1907 RTL_W8 (Cfg9346, Cfg9346_Lock);
1908
1909 /* init Rx ring buffer DMA address */
1910 RTL_W32_F (RxBuf, tp->rx_ring_dma);
1911
1912 /* A.C.: Reset the multicast list. */
1913 __set_rx_mode (dev);
1914 #endif
1915 }
1916
1917 #if RX_BUF_IDX == 3
1918 static __inline__ void wrap_copy(struct sk_buff *skb, const unsigned char *ring,
1919 u32 offset, unsigned int size)
1920 {
1921 u32 left = RX_BUF_LEN - offset;
1922
1923 if (size > left) {
1924 memcpy(skb->data, ring + offset, left);
1925 memcpy(skb->data+left, ring, size - left);
1926 } else
1927 memcpy(skb->data, ring + offset, size);
1928 }
1929 #endif
1930
1931 static void rtl8139_isr_ack(struct rtl8139_private *tp)
1932 {
1933 void *ioaddr = tp->mmio_addr;
1934 u16 status;
1935
1936 status = RTL_R16 (IntrStatus) & RxAckBits;
1937
1938 /* Clear out errors and receive interrupts */
1939 if (likely(status != 0)) {
1940 if (unlikely(status & (RxFIFOOver | RxOverflow))) {
1941 tp->stats.rx_errors++;
1942 if (status & RxFIFOOver)
1943 tp->stats.rx_fifo_errors++;
1944 }
1945 RTL_W16_F (IntrStatus, RxAckBits);
1946 }
1947 }
1948
1949 static int rtl8139_rx(struct net_device *dev, struct rtl8139_private *tp,
1950 int budget)
1951 {
1952 void *ioaddr = tp->mmio_addr;
1953 int received = 0;
1954 unsigned char *rx_ring = tp->rx_ring;
1955 unsigned int cur_rx = tp->cur_rx;
1956 unsigned int rx_size = 0;
1957
1958 DPRINTK ("%s: In rtl8139_rx(), current %4.4x BufAddr %4.4x,"
1959 " free to %4.4x, Cmd %2.2x.\n", dev->name, (u16)cur_rx,
1960 RTL_R16 (RxBufAddr),
1961 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
1962
1963 while (netif_running(dev) && received < budget
1964 && (RTL_R8 (ChipCmd) & RxBufEmpty) == 0) {
1965 u32 ring_offset = cur_rx % RX_BUF_LEN;
1966 u32 rx_status;
1967 unsigned int pkt_size;
1968 struct sk_buff *skb;
1969
1970 rmb();
1971
1972 /* read size+status of next frame from DMA ring buffer */
1973 rx_status = le32_to_cpu (*(u32 *) (rx_ring + ring_offset));
1974 rx_size = rx_status >> 16;
1975 pkt_size = rx_size - 4;
1976
1977 if (netif_msg_rx_status(tp))
1978 printk(KERN_DEBUG "%s: rtl8139_rx() status %4.4x, size %4.4x,"
1979 " cur %4.4x.\n", dev->name, rx_status,
1980 rx_size, cur_rx);
1981 #if RTL8139_DEBUG > 2
1982 {
1983 int i;
1984 DPRINTK ("%s: Frame contents ", dev->name);
1985 for (i = 0; i < 70; i++)
1986 printk (" %2.2x",
1987 rx_ring[ring_offset + i]);
1988 printk (".\n");
1989 }
1990 #endif
1991
1992 /* Packet copy from FIFO still in progress.
1993 * Theoretically, this should never happen
1994 * since EarlyRx is disabled.
1995 */
1996 if (unlikely(rx_size == 0xfff0)) {
1997 if (!tp->fifo_copy_timeout)
1998 tp->fifo_copy_timeout = jiffies + 2;
1999 else if (time_after(jiffies, tp->fifo_copy_timeout)) {
2000 DPRINTK ("%s: hung FIFO. Reset.", dev->name);
2001 rx_size = 0;
2002 goto no_early_rx;
2003 }
2004 if (netif_msg_intr(tp)) {
2005 printk(KERN_DEBUG "%s: fifo copy in progress.",
2006 dev->name);
2007 }
2008 tp->xstats.early_rx++;
2009 break;
2010 }
2011
2012 no_early_rx:
2013 tp->fifo_copy_timeout = 0;
2014
2015 /* If Rx err or invalid rx_size/rx_status received
2016 * (which happens if we get lost in the ring),
2017 * Rx process gets reset, so we abort any further
2018 * Rx processing.
2019 */
2020 if (unlikely((rx_size > (MAX_ETH_FRAME_SIZE+4)) ||
2021 (rx_size < 8) ||
2022 (!(rx_status & RxStatusOK)))) {
2023 rtl8139_rx_err (rx_status, dev, tp, ioaddr);
2024 received = -1;
2025 goto out;
2026 }
2027
2028 /* Malloc up new buffer, compatible with net-2e. */
2029 /* Omit the four octet CRC from the length. */
2030
2031 skb = dev_alloc_skb (pkt_size + 2);
2032 if (likely(skb)) {
2033 skb->dev = dev;
2034 skb_reserve (skb, 2); /* 16 byte align the IP fields. */
2035 #if RX_BUF_IDX == 3
2036 wrap_copy(skb, rx_ring, ring_offset+4, pkt_size);
2037 #else
2038 eth_copy_and_sum (skb, &rx_ring[ring_offset + 4], pkt_size, 0);
2039 #endif
2040 skb_put (skb, pkt_size);
2041
2042 skb->protocol = eth_type_trans (skb, dev);
2043
2044 dev->last_rx = jiffies;
2045 tp->stats.rx_bytes += pkt_size;
2046 tp->stats.rx_packets++;
2047
2048 netif_receive_skb (skb);
2049 } else {
2050 if (net_ratelimit())
2051 printk (KERN_WARNING
2052 "%s: Memory squeeze, dropping packet.\n",
2053 dev->name);
2054 tp->stats.rx_dropped++;
2055 }
2056 received++;
2057
2058 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
2059 RTL_W16 (RxBufPtr, (u16) (cur_rx - 16));
2060
2061 rtl8139_isr_ack(tp);
2062 }
2063
2064 if (unlikely(!received || rx_size == 0xfff0))
2065 rtl8139_isr_ack(tp);
2066
2067 #if RTL8139_DEBUG > 1
2068 DPRINTK ("%s: Done rtl8139_rx(), current %4.4x BufAddr %4.4x,"
2069 " free to %4.4x, Cmd %2.2x.\n", dev->name, cur_rx,
2070 RTL_R16 (RxBufAddr),
2071 RTL_R16 (RxBufPtr), RTL_R8 (ChipCmd));
2072 #endif
2073
2074 tp->cur_rx = cur_rx;
2075
2076 /*
2077 * The receive buffer should be mostly empty.
2078 * Tell NAPI to reenable the Rx irq.
2079 */
2080 if (tp->fifo_copy_timeout)
2081 received = budget;
2082
2083 out:
2084 return received;
2085 }
2086
2087
2088 static void rtl8139_weird_interrupt (struct net_device *dev,
2089 struct rtl8139_private *tp,
2090 void *ioaddr,
2091 int status, int link_changed)
2092 {
2093 DPRINTK ("%s: Abnormal interrupt, status %8.8x.\n",
2094 dev->name, status);
2095
2096 assert (dev != NULL);
2097 assert (tp != NULL);
2098 assert (ioaddr != NULL);
2099
2100 /* Update the error count. */
2101 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2102 RTL_W32 (RxMissed, 0);
2103
2104 if ((status & RxUnderrun) && link_changed &&
2105 (tp->drv_flags & HAS_LNK_CHNG)) {
2106 rtl_check_media(dev, 0);
2107 status &= ~RxUnderrun;
2108 }
2109
2110 if (status & (RxUnderrun | RxErr))
2111 tp->stats.rx_errors++;
2112
2113 if (status & PCSTimeout)
2114 tp->stats.rx_length_errors++;
2115 if (status & RxUnderrun)
2116 tp->stats.rx_fifo_errors++;
2117 if (status & PCIErr) {
2118 u16 pci_cmd_status;
2119 pci_read_config_word (tp->pci_dev, PCI_STATUS, &pci_cmd_status);
2120 pci_write_config_word (tp->pci_dev, PCI_STATUS, pci_cmd_status);
2121
2122 printk (KERN_ERR "%s: PCI Bus error %4.4x.\n",
2123 dev->name, pci_cmd_status);
2124 }
2125 }
2126
2127 static int rtl8139_poll(struct net_device *dev, int *budget)
2128 {
2129 struct rtl8139_private *tp = dev->priv;
2130 void *ioaddr = tp->mmio_addr;
2131 int orig_budget = min(*budget, dev->quota);
2132 int done = 1;
2133
2134 spin_lock(&tp->rx_lock);
2135 if (likely(RTL_R16(IntrStatus) & RxAckBits)) {
2136 int work_done;
2137
2138 work_done = rtl8139_rx(dev, tp, orig_budget);
2139 if (likely(work_done > 0)) {
2140 *budget -= work_done;
2141 dev->quota -= work_done;
2142 done = (work_done < orig_budget);
2143 }
2144 }
2145
2146 if (done) {
2147 /*
2148 * Order is important since data can get interrupted
2149 * again when we think we are done.
2150 */
2151 local_irq_disable();
2152 RTL_W16_F(IntrMask, rtl8139_intr_mask);
2153 __netif_rx_complete(dev);
2154 local_irq_enable();
2155 }
2156 spin_unlock(&tp->rx_lock);
2157
2158 return !done;
2159 }
2160
2161 /* The interrupt handler does all of the Rx thread work and cleans up
2162 after the Tx thread. */
2163 static irqreturn_t rtl8139_interrupt (int irq, void *dev_instance,
2164 struct pt_regs *regs)
2165 {
2166 struct net_device *dev = (struct net_device *) dev_instance;
2167 struct rtl8139_private *tp = dev->priv;
2168 void *ioaddr = tp->mmio_addr;
2169 u16 status, ackstat;
2170 int link_changed = 0; /* avoid bogus "uninit" warning */
2171 int handled = 0;
2172
2173 spin_lock (&tp->lock);
2174 status = RTL_R16 (IntrStatus);
2175
2176 /* shared irq? */
2177 if (unlikely((status & rtl8139_intr_mask) == 0))
2178 goto out;
2179
2180 handled = 1;
2181
2182 /* h/w no longer present (hotplug?) or major error, bail */
2183 if (unlikely(status == 0xFFFF))
2184 goto out;
2185
2186 /* close possible race's with dev_close */
2187 if (unlikely(!netif_running(dev))) {
2188 RTL_W16 (IntrMask, 0);
2189 goto out;
2190 }
2191
2192 /* Acknowledge all of the current interrupt sources ASAP, but
2193 an first get an additional status bit from CSCR. */
2194 if (unlikely(status & RxUnderrun))
2195 link_changed = RTL_R16 (CSCR) & CSCR_LinkChangeBit;
2196
2197 ackstat = status & ~(RxAckBits | TxErr);
2198 if (ackstat)
2199 RTL_W16 (IntrStatus, ackstat);
2200
2201 /* Receive packets are processed by poll routine.
2202 If not running start it now. */
2203 if (status & RxAckBits){
2204 if (netif_rx_schedule_prep(dev)) {
2205 RTL_W16_F (IntrMask, rtl8139_norx_intr_mask);
2206 __netif_rx_schedule (dev);
2207 }
2208 }
2209
2210 /* Check uncommon events with one test. */
2211 if (unlikely(status & (PCIErr | PCSTimeout | RxUnderrun | RxErr)))
2212 rtl8139_weird_interrupt (dev, tp, ioaddr,
2213 status, link_changed);
2214
2215 if (status & (TxOK | TxErr)) {
2216 rtl8139_tx_interrupt (dev, tp, ioaddr);
2217 if (status & TxErr)
2218 RTL_W16 (IntrStatus, TxErr);
2219 }
2220 out:
2221 spin_unlock (&tp->lock);
2222
2223 DPRINTK ("%s: exiting interrupt, intr_status=%#4.4x.\n",
2224 dev->name, RTL_R16 (IntrStatus));
2225 return IRQ_RETVAL(handled);
2226 }
2227
2228 #ifdef CONFIG_NET_POLL_CONTROLLER
2229 /*
2230 * Polling receive - used by netconsole and other diagnostic tools
2231 * to allow network i/o with interrupts disabled.
2232 */
2233 static void rtl8139_poll_controller(struct net_device *dev)
2234 {
2235 disable_irq(dev->irq);
2236 rtl8139_interrupt(dev->irq, dev, NULL);
2237 enable_irq(dev->irq);
2238 }
2239 #endif
2240
2241 static int rtl8139_close (struct net_device *dev)
2242 {
2243 struct rtl8139_private *tp = dev->priv;
2244 void *ioaddr = tp->mmio_addr;
2245 int ret = 0;
2246 unsigned long flags;
2247
2248 netif_stop_queue (dev);
2249
2250 if (tp->thr_pid >= 0) {
2251 tp->time_to_die = 1;
2252 wmb();
2253 ret = kill_proc (tp->thr_pid, SIGTERM, 1);
2254 if (ret) {
2255 printk (KERN_ERR "%s: unable to signal thread\n", dev->name);
2256 return ret;
2257 }
2258 wait_for_completion (&tp->thr_exited);
2259 }
2260
2261 if (netif_msg_ifdown(tp))
2262 printk(KERN_DEBUG "%s: Shutting down ethercard, status was 0x%4.4x.\n",
2263 dev->name, RTL_R16 (IntrStatus));
2264
2265 spin_lock_irqsave (&tp->lock, flags);
2266
2267 /* Stop the chip's Tx and Rx DMA processes. */
2268 RTL_W8 (ChipCmd, 0);
2269
2270 /* Disable interrupts by clearing the interrupt mask. */
2271 RTL_W16 (IntrMask, 0);
2272
2273 /* Update the error counts. */
2274 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2275 RTL_W32 (RxMissed, 0);
2276
2277 spin_unlock_irqrestore (&tp->lock, flags);
2278
2279 synchronize_irq (dev->irq); /* racy, but that's ok here */
2280 free_irq (dev->irq, dev);
2281
2282 rtl8139_tx_clear (tp);
2283
2284 pci_free_consistent(tp->pci_dev, RX_BUF_TOT_LEN,
2285 tp->rx_ring, tp->rx_ring_dma);
2286 pci_free_consistent(tp->pci_dev, TX_BUF_TOT_LEN,
2287 tp->tx_bufs, tp->tx_bufs_dma);
2288 tp->rx_ring = NULL;
2289 tp->tx_bufs = NULL;
2290
2291 /* Green! Put the chip in low-power mode. */
2292 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2293
2294 if (rtl_chip_info[tp->chipset].flags & HasHltClk)
2295 RTL_W8 (HltClk, 'H'); /* 'R' would leave the clock running. */
2296
2297 return 0;
2298 }
2299
2300
2301 /* Get the ethtool Wake-on-LAN settings. Assumes that wol points to
2302 kernel memory, *wol has been initialized as {ETHTOOL_GWOL}, and
2303 other threads or interrupts aren't messing with the 8139. */
2304 static void rtl8139_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2305 {
2306 struct rtl8139_private *np = dev->priv;
2307 void *ioaddr = np->mmio_addr;
2308
2309 spin_lock_irq(&np->lock);
2310 if (rtl_chip_info[np->chipset].flags & HasLWake) {
2311 u8 cfg3 = RTL_R8 (Config3);
2312 u8 cfg5 = RTL_R8 (Config5);
2313
2314 wol->supported = WAKE_PHY | WAKE_MAGIC
2315 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST;
2316
2317 wol->wolopts = 0;
2318 if (cfg3 & Cfg3_LinkUp)
2319 wol->wolopts |= WAKE_PHY;
2320 if (cfg3 & Cfg3_Magic)
2321 wol->wolopts |= WAKE_MAGIC;
2322 /* (KON)FIXME: See how netdev_set_wol() handles the
2323 following constants. */
2324 if (cfg5 & Cfg5_UWF)
2325 wol->wolopts |= WAKE_UCAST;
2326 if (cfg5 & Cfg5_MWF)
2327 wol->wolopts |= WAKE_MCAST;
2328 if (cfg5 & Cfg5_BWF)
2329 wol->wolopts |= WAKE_BCAST;
2330 }
2331 spin_unlock_irq(&np->lock);
2332 }
2333
2334
2335 /* Set the ethtool Wake-on-LAN settings. Return 0 or -errno. Assumes
2336 that wol points to kernel memory and other threads or interrupts
2337 aren't messing with the 8139. */
2338 static int rtl8139_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2339 {
2340 struct rtl8139_private *np = dev->priv;
2341 void *ioaddr = np->mmio_addr;
2342 u32 support;
2343 u8 cfg3, cfg5;
2344
2345 support = ((rtl_chip_info[np->chipset].flags & HasLWake)
2346 ? (WAKE_PHY | WAKE_MAGIC
2347 | WAKE_UCAST | WAKE_MCAST | WAKE_BCAST)
2348 : 0);
2349 if (wol->wolopts & ~support)
2350 return -EINVAL;
2351
2352 spin_lock_irq(&np->lock);
2353 cfg3 = RTL_R8 (Config3) & ~(Cfg3_LinkUp | Cfg3_Magic);
2354 if (wol->wolopts & WAKE_PHY)
2355 cfg3 |= Cfg3_LinkUp;
2356 if (wol->wolopts & WAKE_MAGIC)
2357 cfg3 |= Cfg3_Magic;
2358 RTL_W8 (Cfg9346, Cfg9346_Unlock);
2359 RTL_W8 (Config3, cfg3);
2360 RTL_W8 (Cfg9346, Cfg9346_Lock);
2361
2362 cfg5 = RTL_R8 (Config5) & ~(Cfg5_UWF | Cfg5_MWF | Cfg5_BWF);
2363 /* (KON)FIXME: These are untested. We may have to set the
2364 CRC0, Wakeup0 and LSBCRC0 registers too, but I have no
2365 documentation. */
2366 if (wol->wolopts & WAKE_UCAST)
2367 cfg5 |= Cfg5_UWF;
2368 if (wol->wolopts & WAKE_MCAST)
2369 cfg5 |= Cfg5_MWF;
2370 if (wol->wolopts & WAKE_BCAST)
2371 cfg5 |= Cfg5_BWF;
2372 RTL_W8 (Config5, cfg5); /* need not unlock via Cfg9346 */
2373 spin_unlock_irq(&np->lock);
2374
2375 return 0;
2376 }
2377
2378 static void rtl8139_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2379 {
2380 struct rtl8139_private *np = dev->priv;
2381 strcpy(info->driver, DRV_NAME);
2382 strcpy(info->version, DRV_VERSION);
2383 strcpy(info->bus_info, pci_name(np->pci_dev));
2384 info->regdump_len = np->regs_len;
2385 }
2386
2387 static int rtl8139_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2388 {
2389 struct rtl8139_private *np = dev->priv;
2390 spin_lock_irq(&np->lock);
2391 mii_ethtool_gset(&np->mii, cmd);
2392 spin_unlock_irq(&np->lock);
2393 return 0;
2394 }
2395
2396 static int rtl8139_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2397 {
2398 struct rtl8139_private *np = dev->priv;
2399 int rc;
2400 spin_lock_irq(&np->lock);
2401 rc = mii_ethtool_sset(&np->mii, cmd);
2402 spin_unlock_irq(&np->lock);
2403 return rc;
2404 }
2405
2406 static int rtl8139_nway_reset(struct net_device *dev)
2407 {
2408 struct rtl8139_private *np = dev->priv;
2409 return mii_nway_restart(&np->mii);
2410 }
2411
2412 static u32 rtl8139_get_link(struct net_device *dev)
2413 {
2414 struct rtl8139_private *np = dev->priv;
2415 return mii_link_ok(&np->mii);
2416 }
2417
2418 static u32 rtl8139_get_msglevel(struct net_device *dev)
2419 {
2420 struct rtl8139_private *np = dev->priv;
2421 return np->msg_enable;
2422 }
2423
2424 static void rtl8139_set_msglevel(struct net_device *dev, u32 datum)
2425 {
2426 struct rtl8139_private *np = dev->priv;
2427 np->msg_enable = datum;
2428 }
2429
2430 /* TODO: we are too slack to do reg dumping for pio, for now */
2431 #ifdef CONFIG_8139TOO_PIO
2432 #define rtl8139_get_regs_len NULL
2433 #define rtl8139_get_regs NULL
2434 #else
2435 static int rtl8139_get_regs_len(struct net_device *dev)
2436 {
2437 struct rtl8139_private *np = dev->priv;
2438 return np->regs_len;
2439 }
2440
2441 static void rtl8139_get_regs(struct net_device *dev, struct ethtool_regs *regs, void *regbuf)
2442 {
2443 struct rtl8139_private *np = dev->priv;
2444
2445 regs->version = RTL_REGS_VER;
2446
2447 spin_lock_irq(&np->lock);
2448 memcpy_fromio(regbuf, np->mmio_addr, regs->len);
2449 spin_unlock_irq(&np->lock);
2450 }
2451 #endif /* CONFIG_8139TOO_MMIO */
2452
2453 static int rtl8139_get_stats_count(struct net_device *dev)
2454 {
2455 return RTL_NUM_STATS;
2456 }
2457
2458 static void rtl8139_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data)
2459 {
2460 struct rtl8139_private *np = dev->priv;
2461
2462 data[0] = np->xstats.early_rx;
2463 data[1] = np->xstats.tx_buf_mapped;
2464 data[2] = np->xstats.tx_timeouts;
2465 data[3] = np->xstats.rx_lost_in_ring;
2466 }
2467
2468 static void rtl8139_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2469 {
2470 memcpy(data, ethtool_stats_keys, sizeof(ethtool_stats_keys));
2471 }
2472
2473 static struct ethtool_ops rtl8139_ethtool_ops = {
2474 .get_drvinfo = rtl8139_get_drvinfo,
2475 .get_settings = rtl8139_get_settings,
2476 .set_settings = rtl8139_set_settings,
2477 .get_regs_len = rtl8139_get_regs_len,
2478 .get_regs = rtl8139_get_regs,
2479 .nway_reset = rtl8139_nway_reset,
2480 .get_link = rtl8139_get_link,
2481 .get_msglevel = rtl8139_get_msglevel,
2482 .set_msglevel = rtl8139_set_msglevel,
2483 .get_wol = rtl8139_get_wol,
2484 .set_wol = rtl8139_set_wol,
2485 .get_strings = rtl8139_get_strings,
2486 .get_stats_count = rtl8139_get_stats_count,
2487 .get_ethtool_stats = rtl8139_get_ethtool_stats,
2488 };
2489
2490 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2491 {
2492 struct rtl8139_private *np = dev->priv;
2493 int rc;
2494
2495 if (!netif_running(dev))
2496 return -EINVAL;
2497
2498 spin_lock_irq(&np->lock);
2499 rc = generic_mii_ioctl(&np->mii, if_mii(rq), cmd, NULL);
2500 spin_unlock_irq(&np->lock);
2501
2502 return rc;
2503 }
2504
2505
2506 static struct net_device_stats *rtl8139_get_stats (struct net_device *dev)
2507 {
2508 struct rtl8139_private *tp = dev->priv;
2509 void *ioaddr = tp->mmio_addr;
2510 unsigned long flags;
2511
2512 if (netif_running(dev)) {
2513 spin_lock_irqsave (&tp->lock, flags);
2514 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2515 RTL_W32 (RxMissed, 0);
2516 spin_unlock_irqrestore (&tp->lock, flags);
2517 }
2518
2519 return &tp->stats;
2520 }
2521
2522 /* Set or clear the multicast filter for this adaptor.
2523 This routine is not state sensitive and need not be SMP locked. */
2524
2525 static void __set_rx_mode (struct net_device *dev)
2526 {
2527 struct rtl8139_private *tp = dev->priv;
2528 void *ioaddr = tp->mmio_addr;
2529 u32 mc_filter[2]; /* Multicast hash filter */
2530 int i, rx_mode;
2531 u32 tmp;
2532
2533 DPRINTK ("%s: rtl8139_set_rx_mode(%4.4x) done -- Rx config %8.8lx.\n",
2534 dev->name, dev->flags, RTL_R32 (RxConfig));
2535
2536 /* Note: do not reorder, GCC is clever about common statements. */
2537 if (dev->flags & IFF_PROMISC) {
2538 /* Unconditionally log net taps. */
2539 printk (KERN_NOTICE "%s: Promiscuous mode enabled.\n",
2540 dev->name);
2541 rx_mode =
2542 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
2543 AcceptAllPhys;
2544 mc_filter[1] = mc_filter[0] = 0xffffffff;
2545 } else if ((dev->mc_count > multicast_filter_limit)
2546 || (dev->flags & IFF_ALLMULTI)) {
2547 /* Too many to filter perfectly -- accept all multicasts. */
2548 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
2549 mc_filter[1] = mc_filter[0] = 0xffffffff;
2550 } else {
2551 struct dev_mc_list *mclist;
2552 rx_mode = AcceptBroadcast | AcceptMyPhys;
2553 mc_filter[1] = mc_filter[0] = 0;
2554 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
2555 i++, mclist = mclist->next) {
2556 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
2557
2558 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2559 rx_mode |= AcceptMulticast;
2560 }
2561 }
2562
2563 /* We can safely update without stopping the chip. */
2564 tmp = rtl8139_rx_config | rx_mode;
2565 if (tp->rx_config != tmp) {
2566 RTL_W32_F (RxConfig, tmp);
2567 tp->rx_config = tmp;
2568 }
2569 RTL_W32_F (MAR0 + 0, mc_filter[0]);
2570 RTL_W32_F (MAR0 + 4, mc_filter[1]);
2571 }
2572
2573 static void rtl8139_set_rx_mode (struct net_device *dev)
2574 {
2575 unsigned long flags;
2576 struct rtl8139_private *tp = dev->priv;
2577
2578 spin_lock_irqsave (&tp->lock, flags);
2579 __set_rx_mode(dev);
2580 spin_unlock_irqrestore (&tp->lock, flags);
2581 }
2582
2583 #ifdef CONFIG_PM
2584
2585 static int rtl8139_suspend (struct pci_dev *pdev, u32 state)
2586 {
2587 struct net_device *dev = pci_get_drvdata (pdev);
2588 struct rtl8139_private *tp = dev->priv;
2589 void *ioaddr = tp->mmio_addr;
2590 unsigned long flags;
2591
2592 pci_save_state (pdev, tp->pci_state);
2593
2594 if (!netif_running (dev))
2595 return 0;
2596
2597 netif_device_detach (dev);
2598
2599 spin_lock_irqsave (&tp->lock, flags);
2600
2601 /* Disable interrupts, stop Tx and Rx. */
2602 RTL_W16 (IntrMask, 0);
2603 RTL_W8 (ChipCmd, 0);
2604
2605 /* Update the error counts. */
2606 tp->stats.rx_missed_errors += RTL_R32 (RxMissed);
2607 RTL_W32 (RxMissed, 0);
2608
2609 spin_unlock_irqrestore (&tp->lock, flags);
2610
2611 pci_set_power_state (pdev, 3);
2612
2613 return 0;
2614 }
2615
2616
2617 static int rtl8139_resume (struct pci_dev *pdev)
2618 {
2619 struct net_device *dev = pci_get_drvdata (pdev);
2620 struct rtl8139_private *tp = dev->priv;
2621
2622 pci_restore_state (pdev, tp->pci_state);
2623 if (!netif_running (dev))
2624 return 0;
2625 pci_set_power_state (pdev, 0);
2626 rtl8139_init_ring (dev);
2627 rtl8139_hw_start (dev);
2628 netif_device_attach (dev);
2629 return 0;
2630 }
2631
2632 #endif /* CONFIG_PM */
2633
2634
2635 static struct pci_driver rtl8139_pci_driver = {
2636 .name = DRV_NAME,
2637 .id_table = rtl8139_pci_tbl,
2638 .probe = rtl8139_init_one,
2639 .remove = __devexit_p(rtl8139_remove_one),
2640 #ifdef CONFIG_PM
2641 .suspend = rtl8139_suspend,
2642 .resume = rtl8139_resume,
2643 #endif /* CONFIG_PM */
2644 };
2645
2646
2647 static int __init rtl8139_init_module (void)
2648 {
2649 /* when we're a module, we always print a version message,
2650 * even if no 8139 board is found.
2651 */
2652 #ifdef MODULE
2653 printk (KERN_INFO RTL8139_DRIVER_NAME "\n");
2654 #endif
2655
2656 return pci_module_init (&rtl8139_pci_driver);
2657 }
2658
2659
2660 static void __exit rtl8139_cleanup_module (void)
2661 {
2662 pci_unregister_driver (&rtl8139_pci_driver);
2663 }
2664
2665
2666 module_init(rtl8139_init_module);
2667 module_exit(rtl8139_cleanup_module);
MOXA 2.6.9 from sdlinux-moxaart.tgz