drivers/media/dvb/ttpci/av7110_hw.h

   1 #ifndef _AV7110_HW_H_
   2 #define _AV7110_HW_H_
   3
   4 #include "av7110.h"
   5
   6 /* DEBI transfer mode defs */
   7
   8 #define DEBINOSWAP 0x000e0000
   9 #define DEBISWAB   0x001e0000
  10 #define DEBISWAP   0x002e0000
  11
  12 #define ARM_WAIT_FREE  (HZ)
  13 #define ARM_WAIT_SHAKE (HZ/5)
  14 #define ARM_WAIT_OSD (HZ)
  15
  16
  17 enum av7110_bootstate
  18 {
  19         BOOTSTATE_BUFFER_EMPTY  = 0,
  20         BOOTSTATE_BUFFER_FULL   = 1,
  21         BOOTSTATE_BOOT_COMPLETE = 2
  22 };
  23
  24 enum av7110_type_rec_play_format
  25 {       RP_None,
  26         AudioPES,
  27         AudioMp2,
  28         AudioPCM,
  29         VideoPES,
  30         AV_PES
  31 };
  32
  33 enum av7110_osd_palette_type
  34 {
  35         NoPalet =  0,      /* No palette */
  36         Pal1Bit =  2,      /* 2 colors for 1 Bit Palette    */
  37         Pal2Bit =  4,      /* 4 colors for 2 bit palette    */
  38         Pal4Bit =  16,     /* 16 colors for 4 bit palette   */
  39         Pal8Bit =  256     /* 256 colors for 16 bit palette */
  40 };
  41
  42 enum av7110_window_display_type {
  43         BITMAP1,           /* 1 bit bitmap */
  44         BITMAP2,           /* 2 bit bitmap */
  45         BITMAP4,           /* 4 bit bitmap */
  46         BITMAP8,           /* 8 bit bitmap */
  47         BITMAP1HR,         /* 1 Bit bitmap half resolution */
  48         BITMAP2HR,         /* 2 bit bitmap half resolution */
  49         BITMAP4HR,         /* 4 bit bitmap half resolution */
  50         BITMAP8HR,         /* 8 bit bitmap half resolution */
  51         YCRCB422,          /* 4:2:2 YCRCB Graphic Display */
  52         YCRCB444,          /* 4:4:4 YCRCB Graphic Display */
  53         YCRCB444HR,        /* 4:4:4 YCRCB graphic half resolution */
  54         VIDEOTSIZE,        /* True Size Normal MPEG Video Display */
  55         VIDEOHSIZE,        /* MPEG Video Display Half Resolution */
  56         VIDEOQSIZE,        /* MPEG Video Display Quarter Resolution */
  57         VIDEODSIZE,        /* MPEG Video Display Double Resolution */
  58         VIDEOTHSIZE,       /* True Size MPEG Video Display Half Resolution */
  59         VIDEOTQSIZE,       /* True Size MPEG Video Display Quarter Resolution*/
  60         VIDEOTDSIZE,       /* True Size MPEG Video Display Double Resolution */
  61         VIDEONSIZE,        /* Full Size MPEG Video Display */
  62         CURSOR             /* Cursor */
  63 };
  64
  65 /* switch defines */
  66 #define SB_GPIO 3
  67 #define SB_OFF  SAA7146_GPIO_OUTLO  /* SlowBlank off (TV-Mode) */
  68 #define SB_ON   SAA7146_GPIO_INPUT  /* SlowBlank on  (AV-Mode) */
  69 #define SB_WIDE SAA7146_GPIO_OUTHI  /* SlowBlank 6V  (16/9-Mode) (not implemented) */
  70
  71 #define FB_GPIO 1
  72 #define FB_OFF  SAA7146_GPIO_LO     /* FastBlank off (CVBS-Mode) */
  73 #define FB_ON   SAA7146_GPIO_OUTHI  /* FastBlank on  (RGB-Mode) */
  74 #define FB_LOOP SAA7146_GPIO_INPUT  /* FastBlank loop-through (PC graphics ???) */
  75
  76 enum av7110_video_output_mode
  77 {
  78         NO_OUT       = 0,               /* disable analog output */
  79         CVBS_RGB_OUT = 1,
  80         CVBS_YC_OUT  = 2,
  81         YC_OUT       = 3
  82 };
  83
  84 /* firmware internal msg q status: */
  85 #define GPMQFull        0x0001          /* Main Message Queue Full */
  86 #define GPMQOver        0x0002          /* Main Message Queue Overflow */
  87 #define HPQFull         0x0004          /* High Priority Msg Queue Full */
  88 #define HPQOver         0x0008
  89 #define OSDQFull        0x0010          /* OSD Queue Full */
  90 #define OSDQOver        0x0020
  91
  92 /* hw section filter flags */
  93 #define SECTION_EIT             0x01
  94 #define SECTION_SINGLE          0x00
  95 #define SECTION_CYCLE           0x02
  96 #define SECTION_CONTINUOS       0x04
  97 #define SECTION_MODE            0x06
  98 #define SECTION_IPMPE           0x0C    /* size up to 4k */
  99 #define SECTION_HIGH_SPEED      0x1C    /* larger buffer */
 100 #define DATA_PIPING_FLAG        0x20    /* for Data Piping Filter */
 101
 102 #define PBUFSIZE_NONE 0x0000
 103 #define PBUFSIZE_1P   0x0100
 104 #define PBUFSIZE_2P   0x0200
 105 #define PBUFSIZE_1K   0x0300
 106 #define PBUFSIZE_2K   0x0400
 107 #define PBUFSIZE_4K   0x0500
 108 #define PBUFSIZE_8K   0x0600
 109 #define PBUFSIZE_16K  0x0700
 110 #define PBUFSIZE_32K  0x0800
 111
 112
 113 /* firmware command codes */
 114 enum av7110_osd_command {
 115         WCreate,
 116         WDestroy,
 117         WMoveD,
 118         WMoveA,
 119         WHide,
 120         WTop,
 121         DBox,
 122         DLine,
 123         DText,
 124         Set_Font,
 125         SetColor,
 126         SetBlend,
 127         SetWBlend,
 128         SetCBlend,
 129         SetNonBlend,
 130         LoadBmp,
 131         BlitBmp,
 132         ReleaseBmp,
 133         SetWTrans,
 134         SetWNoTrans,
 135         Set_Palette
 136 };
 137
 138 enum av7110_pid_command {
 139         MultiPID,
 140         VideoPID,
 141         AudioPID,
 142         InitFilt,
 143         FiltError,
 144         NewVersion,
 145         CacheError,
 146         AddPIDFilter,
 147         DelPIDFilter,
 148         Scan,
 149         SetDescr,
 150         SetIR,
 151         FlushTSQueue
 152 };
 153
 154 enum av7110_mpeg_command {
 155         SelAudChannels
 156 };
 157
 158 enum av7110_audio_command {
 159         AudioDAC,
 160         CabADAC,
 161         ON22K,
 162         OFF22K,
 163         MainSwitch,
 164         ADSwitch,
 165         SendDiSEqC,
 166         SetRegister
 167 };
 168
 169 enum av7110_request_command {
 170         AudioState,
 171         AudioBuffState,
 172         VideoState1,
 173         VideoState2,
 174         VideoState3,
 175         CrashCounter,
 176         ReqVersion,
 177         ReqVCXO,
 178         ReqRegister,
 179         ReqSecFilterError,
 180         ReqSTC
 181 };
 182
 183 enum av7110_encoder_command {
 184         SetVidMode,
 185         SetTestMode,
 186         LoadVidCode,
 187         SetMonitorType,
 188         SetPanScanType,
 189         SetFreezeMode
 190 };
 191
 192 enum av7110_rec_play_state {
 193         __Record,
 194         __Stop,
 195         __Play,
 196         __Pause,
 197         __Slow,
 198         __FF_IP,
 199         __Scan_I,
 200         __Continue
 201 };
 202
 203 enum av7110_fw_cmd_misc {
 204         AV7110_FW_VIDEO_ZOOM = 1,
 205         AV7110_FW_VIDEO_COMMAND,
 206         AV7110_FW_AUDIO_COMMAND
 207 };
 208
 209 enum av7110_command_type {
 210         COMTYPE_NOCOM,
 211         COMTYPE_PIDFILTER,
 212         COMTYPE_MPEGDECODER,
 213         COMTYPE_OSD,
 214         COMTYPE_BMP,
 215         COMTYPE_ENCODER,
 216         COMTYPE_AUDIODAC,
 217         COMTYPE_REQUEST,
 218         COMTYPE_SYSTEM,
 219         COMTYPE_REC_PLAY,
 220         COMTYPE_COMMON_IF,
 221         COMTYPE_PID_FILTER,
 222         COMTYPE_PES,
 223         COMTYPE_TS,
 224         COMTYPE_VIDEO,
 225         COMTYPE_AUDIO,
 226         COMTYPE_CI_LL,
 227         COMTYPE_MISC = 0x80
 228 };
 229
 230 #define VID_NONE_PREF           0x00    /* No aspect ration processing preferred */
 231 #define VID_PAN_SCAN_PREF       0x01    /* Pan and Scan Display preferred */
 232 #define VID_VERT_COMP_PREF      0x02    /* Vertical compression display preferred */
 233 #define VID_VC_AND_PS_PREF      0x03    /* PanScan and vertical Compression if allowed */
 234 #define VID_CENTRE_CUT_PREF     0x05    /* PanScan with zero vector */
 235
 236 /* MPEG video decoder commands */
 237 #define VIDEO_CMD_STOP          0x000e
 238 #define VIDEO_CMD_PLAY          0x000d
 239 #define VIDEO_CMD_FREEZE        0x0102
 240 #define VIDEO_CMD_FFWD          0x0016
 241 #define VIDEO_CMD_SLOW          0x0022
 242
 243 /* MPEG audio decoder commands */
 244 #define AUDIO_CMD_MUTE          0x0001
 245 #define AUDIO_CMD_UNMUTE        0x0002
 246 #define AUDIO_CMD_PCM16         0x0010
 247 #define AUDIO_CMD_STEREO        0x0080
 248 #define AUDIO_CMD_MONO_L        0x0100
 249 #define AUDIO_CMD_MONO_R        0x0200
 250 #define AUDIO_CMD_SYNC_OFF      0x000e
 251 #define AUDIO_CMD_SYNC_ON       0x000f
 252
 253 /* firmware data interface codes */
 254 #define DATA_NONE                0x00
 255 #define DATA_FSECTION            0x01
 256 #define DATA_IPMPE               0x02
 257 #define DATA_MPEG_RECORD         0x03
 258 #define DATA_DEBUG_MESSAGE       0x04
 259 #define DATA_COMMON_INTERFACE    0x05
 260 #define DATA_MPEG_PLAY           0x06
 261 #define DATA_BMP_LOAD            0x07
 262 #define DATA_IRCOMMAND           0x08
 263 #define DATA_PIPING              0x09
 264 #define DATA_STREAMING           0x0a
 265 #define DATA_CI_GET              0x0b
 266 #define DATA_CI_PUT              0x0c
 267 #define DATA_MPEG_VIDEO_EVENT    0x0d
 268
 269 #define DATA_PES_RECORD          0x10
 270 #define DATA_PES_PLAY            0x11
 271 #define DATA_TS_RECORD           0x12
 272 #define DATA_TS_PLAY             0x13
 273
 274 /* ancient CI command codes, only two are actually still used
 275  * by the link level CI firmware */
 276 #define CI_CMD_ERROR             0x00
 277 #define CI_CMD_ACK               0x01
 278 #define CI_CMD_SYSTEM_READY      0x02
 279 #define CI_CMD_KEYPRESS          0x03
 280 #define CI_CMD_ON_TUNED          0x04
 281 #define CI_CMD_ON_SWITCH_PROGRAM 0x05
 282 #define CI_CMD_SECTION_ARRIVED   0x06
 283 #define CI_CMD_SECTION_TIMEOUT   0x07
 284 #define CI_CMD_TIME              0x08
 285 #define CI_CMD_ENTER_MENU        0x09
 286 #define CI_CMD_FAST_PSI          0x0a
 287 #define CI_CMD_GET_SLOT_INFO     0x0b
 288
 289 #define CI_MSG_NONE              0x00
 290 #define CI_MSG_CI_INFO           0x01
 291 #define CI_MSG_MENU              0x02
 292 #define CI_MSG_LIST              0x03
 293 #define CI_MSG_TEXT              0x04
 294 #define CI_MSG_REQUEST_INPUT     0x05
 295 #define CI_MSG_INPUT_COMPLETE    0x06
 296 #define CI_MSG_LIST_MORE         0x07
 297 #define CI_MSG_MENU_MORE         0x08
 298 #define CI_MSG_CLOSE_MMI_IMM     0x09
 299 #define CI_MSG_SECTION_REQUEST   0x0a
 300 #define CI_MSG_CLOSE_FILTER      0x0b
 301 #define CI_PSI_COMPLETE          0x0c
 302 #define CI_MODULE_READY          0x0d
 303 #define CI_SWITCH_PRG_REPLY      0x0e
 304 #define CI_MSG_TEXT_MORE         0x0f
 305
 306 #define CI_MSG_CA_PMT            0xe0
 307 #define CI_MSG_ERROR             0xf0
 308
 309
 310 /* base address of the dual ported RAM which serves as communication
 311  * area between PCI bus and av7110,
 312  * as seen by the DEBI bus of the saa7146 */
 313 #define DPRAM_BASE 0x4000
 314
 315 /* boot protocol area */
 316 #define BOOT_STATE      (DPRAM_BASE + 0x3F8)
 317 #define BOOT_SIZE       (DPRAM_BASE + 0x3FA)
 318 #define BOOT_BASE       (DPRAM_BASE + 0x3FC)
 319 #define BOOT_BLOCK      (DPRAM_BASE + 0x400)
 320 #define BOOT_MAX_SIZE   0xc00
 321
 322 /* firmware command protocol area */
 323 #define IRQ_STATE       (DPRAM_BASE + 0x0F4)
 324 #define IRQ_STATE_EXT   (DPRAM_BASE + 0x0F6)
 325 #define MSGSTATE        (DPRAM_BASE + 0x0F8)
 326 #define FILT_STATE      (DPRAM_BASE + 0x0FA)
 327 #define COMMAND         (DPRAM_BASE + 0x0FC)
 328 #define COM_BUFF        (DPRAM_BASE + 0x100)
 329 #define COM_BUFF_SIZE   0x20
 330
 331 /* various data buffers */
 332 #define BUFF1_BASE      (DPRAM_BASE + 0x120)
 333 #define BUFF1_SIZE      0xE0
 334
 335 #define DATA_BUFF0_BASE (DPRAM_BASE + 0x200)
 336 #define DATA_BUFF0_SIZE 0x0800
 337
 338 #define DATA_BUFF1_BASE (DATA_BUFF0_BASE+DATA_BUFF0_SIZE)
 339 #define DATA_BUFF1_SIZE 0x0800
 340
 341 #define DATA_BUFF2_BASE (DATA_BUFF1_BASE+DATA_BUFF1_SIZE)
 342 #define DATA_BUFF2_SIZE 0x0800
 343
 344 #define DATA_BUFF3_BASE (DATA_BUFF2_BASE+DATA_BUFF2_SIZE)
 345 #define DATA_BUFF3_SIZE 0x0400
 346
 347 #define Reserved        (DPRAM_BASE + 0x1E00)
 348 #define Reserved_SIZE   0x1C0
 349
 350
 351 /* firmware status area */
 352 #define STATUS_BASE     (DPRAM_BASE + 0x1FC0)
 353 #define STATUS_SCR      (STATUS_BASE + 0x00)
 354 #define STATUS_MODES    (STATUS_BASE + 0x04)
 355 #define STATUS_LOOPS    (STATUS_BASE + 0x08)
 356
 357 #define STATUS_MPEG_WIDTH     (STATUS_BASE + 0x0C)
 358 /* ((aspect_ratio & 0xf) << 12) | (height & 0xfff) */
 359 #define STATUS_MPEG_HEIGHT_AR (STATUS_BASE + 0x0E)
 360
 361 /* firmware data protocol area */
 362 #define RX_TYPE         (DPRAM_BASE + 0x1FE8)
 363 #define RX_LEN          (DPRAM_BASE + 0x1FEA)
 364 #define TX_TYPE         (DPRAM_BASE + 0x1FEC)
 365 #define TX_LEN          (DPRAM_BASE + 0x1FEE)
 366
 367 #define RX_BUFF         (DPRAM_BASE + 0x1FF4)
 368 #define TX_BUFF         (DPRAM_BASE + 0x1FF6)
 369
 370 #define HANDSHAKE_REG   (DPRAM_BASE + 0x1FF8)
 371 #define COM_IF_LOCK     (DPRAM_BASE + 0x1FFA)
 372
 373 #define IRQ_RX          (DPRAM_BASE + 0x1FFC)
 374 #define IRQ_TX          (DPRAM_BASE + 0x1FFE)
 375
 376 /* used by boot protocol to load firmware into av7110 DRAM */
 377 #define DRAM_START_CODE         0x2e000404
 378 #define DRAM_MAX_CODE_SIZE      0x00100000
 379
 380 /* saa7146 gpio lines */
 381 #define RESET_LINE              2
 382 #define DEBI_DONE_LINE          1
 383 #define ARM_IRQ_LINE            0
 384
 385
 386
 387 extern void av7110_reset_arm(struct av7110 *av7110);
 388 extern int av7110_bootarm(struct av7110 *av7110);
 389 extern int av7110_firmversion(struct av7110 *av7110);
 390 #define FW_CI_LL_SUPPORT(arm_app) ((arm_app) & 0x80000000)
 391 #define FW_VERSION(arm_app)       ((arm_app) & 0x0000FFFF)
 392
 393 extern int av7110_fw_cmd(struct av7110 *av7110, int type, int com, int num, ...);
 394 extern int __av7110_send_fw_cmd(struct av7110 *av7110, u16* buf, int length);
 395 extern int av7110_send_fw_cmd(struct av7110 *av7110, u16* buf, int length);
 396 extern int av7110_send_ci_cmd(struct av7110 *av7110, u8 subcom, u8 *buf, u8 len);
 397 extern int av7110_fw_request(struct av7110 *av7110, u16 *request_buf,
 398                              int request_buf_len, u16 *reply_buf, int reply_buf_len);
 399 extern int av7110_fw_query(struct av7110 *av7110, u16 tag, u16* Buff, s16 length);
 400
 401
 402 /* DEBI (saa7146 data extension bus interface) access */
 403 extern int av7110_debiwrite(struct av7110 *av7110, u32 config,
 404                             int addr, u32 val, int count);
 405 extern u32 av7110_debiread(struct av7110 *av7110, u32 config,
 406                            int addr, int count);
 407
 408
 409 /* DEBI during interrupt */
 410 /* single word writes */
 411 static inline void iwdebi(struct av7110 *av7110, u32 config, int addr, u32 val, int count)
 412 {
 413         av7110_debiwrite(av7110, config, addr, val, count);
 414 }
 415
 416 /* buffer writes */
 417 static inline void mwdebi(struct av7110 *av7110, u32 config, int addr, char *val, int count)
 418 {
 419         memcpy(av7110->debi_virt, val, count);
 420         av7110_debiwrite(av7110, config, addr, 0, count);
 421 }
 422
 423 static inline u32 irdebi(struct av7110 *av7110, u32 config, int addr, u32 val, int count)
 424 {
 425         u32 res;
 426
 427         res=av7110_debiread(av7110, config, addr, count);
 428         if (count<=4)
 429                 memcpy(av7110->debi_virt, (char *) &res, count);
 430         return res;
 431 }
 432
 433 /* DEBI outside interrupts, only for count <= 4! */
 434 static inline void wdebi(struct av7110 *av7110, u32 config, int addr, u32 val, int count)
 435 {
 436         unsigned long flags;
 437
 438         spin_lock_irqsave(&av7110->debilock, flags);
 439         av7110_debiwrite(av7110, config, addr, val, count);
 440         spin_unlock_irqrestore(&av7110->debilock, flags);
 441 }
 442
 443 static inline u32 rdebi(struct av7110 *av7110, u32 config, int addr, u32 val, int count)
 444 {
 445         unsigned long flags;
 446         u32 res;
 447
 448         spin_lock_irqsave(&av7110->debilock, flags);
 449         res=av7110_debiread(av7110, config, addr, count);
 450         spin_unlock_irqrestore(&av7110->debilock, flags);
 451         return res;
 452 }
 453
 454 /* handle mailbox registers of the dual ported RAM */
 455 static inline void ARM_ResetMailBox(struct av7110 *av7110)
 456 {
 457         unsigned long flags;
 458
 459         spin_lock_irqsave(&av7110->debilock, flags);
 460         av7110_debiread(av7110, DEBINOSWAP, IRQ_RX, 2);
 461         av7110_debiwrite(av7110, DEBINOSWAP, IRQ_RX, 0, 2);
 462         spin_unlock_irqrestore(&av7110->debilock, flags);
 463 }
 464
 465 static inline void ARM_ClearMailBox(struct av7110 *av7110)
 466 {
 467         iwdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2);
 468 }
 469
 470 static inline void ARM_ClearIrq(struct av7110 *av7110)
 471 {
 472         irdebi(av7110, DEBINOSWAP, IRQ_RX, 0, 2);
 473 }
 474
 475 /****************************************************************************
 476  * Firmware commands
 477  ****************************************************************************/
 478
 479 static inline int SendDAC(struct av7110 *av7110, u8 addr, u8 data)
 480 {
 481         return av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, AudioDAC, 2, addr, data);
 482 }
 483
 484 static inline void av7710_set_video_mode(struct av7110 *av7110, int mode)
 485 {
 486         av7110_fw_cmd(av7110, COMTYPE_ENCODER, SetVidMode, 1, mode);
 487 }
 488
 489 static int inline vidcom(struct av7110 *av7110, u32 com, u32 arg)
 490 {
 491         return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_VIDEO_COMMAND, 4,
 492                              (com>>16), (com&0xffff),
 493                              (arg>>16), (arg&0xffff));
 494 }
 495
 496 static int inline audcom(struct av7110 *av7110, u32 com)
 497 {
 498         return av7110_fw_cmd(av7110, COMTYPE_MISC, AV7110_FW_AUDIO_COMMAND, 4,
 499                              (com>>16), (com&0xffff));
 500 }
 501
 502 static inline void Set22K(struct av7110 *av7110, int state)
 503 {
 504         av7110_fw_cmd(av7110, COMTYPE_AUDIODAC, (state ? ON22K : OFF22K), 0);
 505 }
 506
 507
 508 extern int av7110_diseqc_send(struct av7110 *av7110, int len, u8 *msg, unsigned long burst);
 509
 510
 511 #ifdef CONFIG_DVB_AV7110_OSD
 512 extern int av7110_osd_cmd(struct av7110 *av7110, osd_cmd_t *dc);
 513 #endif /* CONFIG_DVB_AV7110_OSD */
 514
 515
 516
 517 #endif /* _AV7110_HW_H_ */