drivers/input/serio/i8042.h

   1 #ifndef _I8042_H
   2 #define _I8042_H
   3
   4 #include <linux/config.h>
   5
   6 /*
   7  *  Copyright (c) 1999-2002 Vojtech Pavlik
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License version 2 as published by
  11  * the Free Software Foundation.
  12  */
  13
  14 /*
  15  * Arch-dependent inline functions and defines.
  16  */
  17
  18 #if defined(CONFIG_MIPS_JAZZ)
  19 #include "i8042-jazzio.h"
  20 #elif defined(CONFIG_SGI_IP22)
  21 #include "i8042-ip22io.h"
  22 #elif defined(CONFIG_PPC)
  23 #include "i8042-ppcio.h"
  24 #elif defined(CONFIG_SPARC32) || defined(CONFIG_SPARC64)
  25 #include "i8042-sparcio.h"
  26 #else
  27 #include "i8042-io.h"
  28 #endif
  29
  30 /*
  31  * This is in 50us units, the time we wait for the i8042 to react. This
  32  * has to be long enough for the i8042 itself to timeout on sending a byte
  33  * to a non-existent mouse.
  34  */
  35
  36 #define I8042_CTL_TIMEOUT       10000
  37
  38 /*
  39  * When the device isn't opened and it's interrupts aren't used, we poll it at
  40  * regular intervals to see if any characters arrived. If yes, we can start
  41  * probing for any mouse / keyboard connected. This is the period of the
  42  * polling.
  43  */
  44
  45 #define I8042_POLL_PERIOD       HZ/20
  46
  47 /*
  48  * Status register bits.
  49  */
  50
  51 #define I8042_STR_PARITY        0x80
  52 #define I8042_STR_TIMEOUT       0x40
  53 #define I8042_STR_AUXDATA       0x20
  54 #define I8042_STR_KEYLOCK       0x10
  55 #define I8042_STR_CMDDAT        0x08
  56 #define I8042_STR_MUXERR        0x04
  57 #define I8042_STR_IBF           0x02
  58 #define I8042_STR_OBF           0x01
  59
  60 /*
  61  * Control register bits.
  62  */
  63
  64 #define I8042_CTR_KBDINT        0x01
  65 #define I8042_CTR_AUXINT        0x02
  66 #define I8042_CTR_IGNKEYLOCK    0x08
  67 #define I8042_CTR_KBDDIS        0x10
  68 #define I8042_CTR_AUXDIS        0x20
  69 #define I8042_CTR_XLATE         0x40
  70
  71 /*
  72  * Commands.
  73  */
  74
  75 #define I8042_CMD_CTL_RCTR      0x0120
  76 #define I8042_CMD_CTL_WCTR      0x1060
  77 #define I8042_CMD_CTL_TEST      0x01aa
  78
  79 #define I8042_CMD_KBD_DISABLE   0x00ad
  80 #define I8042_CMD_KBD_ENABLE    0x00ae
  81 #define I8042_CMD_KBD_TEST      0x01ab
  82 #define I8042_CMD_KBD_LOOP      0x11d2
  83
  84 #define I8042_CMD_AUX_DISABLE   0x00a7
  85 #define I8042_CMD_AUX_ENABLE    0x00a8
  86 #define I8042_CMD_AUX_TEST      0x01a9
  87 #define I8042_CMD_AUX_SEND      0x10d4
  88 #define I8042_CMD_AUX_LOOP      0x11d3
  89
  90 #define I8042_CMD_MUX_PFX       0x0090
  91 #define I8042_CMD_MUX_SEND      0x1090
  92
  93 /*
  94  * Return codes.
  95  */
  96
  97 #define I8042_RET_CTL_TEST      0x55
  98
  99 /*
 100  * Expected maximum internal i8042 buffer size. This is used for flushing
 101  * the i8042 buffers. 32 should be more than enough.
 102  */
 103
 104 #define I8042_BUFFER_SIZE       32
 105
 106 /*
 107  * Number of AUX ports on controllers supporting active multiplexing
 108  * specification
 109  */
 110
 111 #define I8042_NUM_MUX_PORTS     4
 112
 113 /*
 114  * Debug.
 115  */
 116
 117 #ifdef DEBUG
 118 static unsigned long i8042_start;
 119 #define dbg_init() do { i8042_start = jiffies; } while (0)
 120 #define dbg(format, arg...) printk(KERN_DEBUG __FILE__ ": " format " [%d]\n" ,\
 121          ## arg, (int) (jiffies - i8042_start))
 122 #else
 123 #define dbg_init() do { } while (0)
 124 #define dbg(format, arg...) do {} while (0)
 125 #endif
 126
 127 #endif /* _I8042_H */