drivers/ide/pci/siimage.c

   1 /*
   2  * linux/drivers/ide/pci/siimage.c              Version 1.07    Nov 30, 2003
   3  *
   4  * Copyright (C) 2001-2002      Andre Hedrick <andre@linux-ide.org>
   5  * Copyright (C) 2003           Red Hat <alan@redhat.com>
   6  *
   7  *  May be copied or modified under the terms of the GNU General Public License
   8  *
   9  *  Documentation available under NDA only
  10  *
  11  *
  12  *  FAQ Items:
  13  *      If you are using Marvell SATA-IDE adapters with Maxtor drives
  14  *      ensure the system is set up for ATA100/UDMA5 not UDMA6.
  15  *
  16  *      If you are using WD drives with SATA bridges you must set the
  17  *      drive to "Single". "Master" will hang
  18  *
  19  *      If you have strange problems with nVidia chipset systems please
  20  *      see the SI support documentation and update your system BIOS
  21  *      if neccessary
  22  */
  23
  24 #include <linux/config.h>
  25 #include <linux/types.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include <linux/delay.h>
  29 #include <linux/hdreg.h>
  30 #include <linux/ide.h>
  31 #include <linux/init.h>
  32
  33 #include <asm/io.h>
  34
  35 #undef SIIMAGE_VIRTUAL_DMAPIO
  36 #undef SIIMAGE_LARGE_DMA
  37
  38 /**
  39  *      pdev_is_sata            -       check if device is SATA
  40  *      @pdev:  PCI device to check
  41  *
  42  *      Returns true if this is a SATA controller
  43  */
  44
  45 static int pdev_is_sata(struct pci_dev *pdev)
  46 {
  47         switch(pdev->device)
  48         {
  49                 case PCI_DEVICE_ID_SII_3112:
  50                 case PCI_DEVICE_ID_SII_1210SA:
  51                         return 1;
  52                 case PCI_DEVICE_ID_SII_680:
  53                         return 0;
  54         }
  55         BUG();
  56         return 0;
  57 }
  58
  59 /**
  60  *      is_sata                 -       check if hwif is SATA
  61  *      @hwif:  interface to check
  62  *
  63  *      Returns true if this is a SATA controller
  64  */
  65
  66 static inline int is_sata(ide_hwif_t *hwif)
  67 {
  68         return pdev_is_sata(hwif->pci_dev);
  69 }
  70
  71 /**
  72  *      siimage_selreg          -       return register base
  73  *      @hwif: interface
  74  *      @r: config offset
  75  *
  76  *      Turn a config register offset into the right address in either
  77  *      PCI space or MMIO space to access the control register in question
  78  *      Thankfully this is a configuration operation so isnt performance
  79  *      criticial.
  80  */
  81
  82 static unsigned long siimage_selreg(ide_hwif_t *hwif, int r)
  83 {
  84         unsigned long base = (unsigned long)hwif->hwif_data;
  85         base += 0xA0 + r;
  86         if(hwif->mmio)
  87                 base += (hwif->channel << 6);
  88         else
  89                 base += (hwif->channel << 4);
  90         return base;
  91 }
  92
  93 /**
  94  *      siimage_seldev          -       return register base
  95  *      @hwif: interface
  96  *      @r: config offset
  97  *
  98  *      Turn a config register offset into the right address in either
  99  *      PCI space or MMIO space to access the control register in question
 100  *      including accounting for the unit shift.
 101  */
 102
 103 static inline unsigned long siimage_seldev(ide_drive_t *drive, int r)
 104 {
 105         ide_hwif_t *hwif        = HWIF(drive);
 106         unsigned long base = (unsigned long)hwif->hwif_data;
 107         base += 0xA0 + r;
 108         if(hwif->mmio)
 109                 base += (hwif->channel << 6);
 110         else
 111                 base += (hwif->channel << 4);
 112         base |= drive->select.b.unit << drive->select.b.unit;
 113         return base;
 114 }
 115
 116 /**
 117  *      siimage_ratemask        -       Compute available modes
 118  *      @drive: IDE drive
 119  *
 120  *      Compute the available speeds for the devices on the interface.
 121  *      For the CMD680 this depends on the clocking mode (scsc), for the
 122  *      SI3312 SATA controller life is a bit simpler. Enforce UDMA33
 123  *      as a limit if there is no 80pin cable present.
 124  */
 125
 126 static byte siimage_ratemask (ide_drive_t *drive)
 127 {
 128         ide_hwif_t *hwif        = HWIF(drive);
 129         u8 mode = 0, scsc = 0;
 130         unsigned long base = (unsigned long) hwif->hwif_data;
 131
 132         if (hwif->mmio)
 133                 scsc = hwif->INB(base + 0x4A);
 134         else
 135                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 136
 137         if(is_sata(hwif))
 138         {
 139                 if(strstr(drive->id->model, "Maxtor"))
 140                         return 3;
 141                 return 4;
 142         }
 143
 144         if ((scsc & 0x30) == 0x10)      /* 133 */
 145                 mode = 4;
 146         else if ((scsc & 0x30) == 0x20) /* 2xPCI */
 147                 mode = 4;
 148         else if ((scsc & 0x30) == 0x00) /* 100 */
 149                 mode = 3;
 150         else    /* Disabled ? */
 151                 BUG();
 152
 153         if (!eighty_ninty_three(drive))
 154                 mode = min(mode, (u8)1);
 155         return mode;
 156 }
 157
 158 /**
 159  *      siimage_taskfile_timing -       turn timing data to a mode
 160  *      @hwif: interface to query
 161  *
 162  *      Read the timing data for the interface and return the
 163  *      mode that is being used.
 164  */
 165
 166 static byte siimage_taskfile_timing (ide_hwif_t *hwif)
 167 {
 168         u16 timing      = 0x328a;
 169         unsigned long addr = siimage_selreg(hwif, 2);
 170
 171         if (hwif->mmio)
 172                 timing = hwif->INW(addr);
 173         else
 174                 pci_read_config_word(hwif->pci_dev, addr, &timing);
 175
 176         switch (timing) {
 177                 case 0x10c1:    return 4;
 178                 case 0x10c3:    return 3;
 179                 case 0x1104:
 180                 case 0x1281:    return 2;
 181                 case 0x2283:    return 1;
 182                 case 0x328a:
 183                 default:        return 0;
 184         }
 185 }
 186
 187 /**
 188  *      simmage_tuneproc        -       tune a drive
 189  *      @drive: drive to tune
 190  *      @mode_wanted: the target operating mode
 191  *
 192  *      Load the timing settings for this device mode into the
 193  *      controller. If we are in PIO mode 3 or 4 turn on IORDY
 194  *      monitoring (bit 9). The TF timing is bits 31:16
 195  */
 196
 197 static void siimage_tuneproc (ide_drive_t *drive, byte mode_wanted)
 198 {
 199         ide_hwif_t *hwif        = HWIF(drive);
 200         u32 speedt              = 0;
 201         u16 speedp              = 0;
 202         unsigned long addr      = siimage_seldev(drive, 0x04);
 203         unsigned long tfaddr    = siimage_selreg(hwif, 0x02);
 204
 205         /* cheat for now and use the docs */
 206         switch(mode_wanted) {
 207                 case 4:
 208                         speedp = 0x10c1;
 209                         speedt = 0x10c1;
 210                         break;
 211                 case 3:
 212                         speedp = 0x10C3;
 213                         speedt = 0x10C3;
 214                         break;
 215                 case 2:
 216                         speedp = 0x1104;
 217                         speedt = 0x1281;
 218                         break;
 219                 case 1:
 220                         speedp = 0x2283;
 221                         speedt = 0x1281;
 222                         break;
 223                 case 0:
 224                 default:
 225                         speedp = 0x328A;
 226                         speedt = 0x328A;
 227                         break;
 228         }
 229         if (hwif->mmio)
 230         {
 231                 hwif->OUTW(speedt, addr);
 232                 hwif->OUTW(speedp, tfaddr);
 233                 /* Now set up IORDY */
 234                 if(mode_wanted == 3 || mode_wanted == 4)
 235                         hwif->OUTW(hwif->INW(tfaddr-2)|0x200, tfaddr-2);
 236                 else
 237                         hwif->OUTW(hwif->INW(tfaddr-2)&~0x200, tfaddr-2);
 238         }
 239         else
 240         {
 241                 pci_write_config_word(hwif->pci_dev, addr, speedp);
 242                 pci_write_config_word(hwif->pci_dev, tfaddr, speedt);
 243                 pci_read_config_word(hwif->pci_dev, tfaddr-2, &speedp);
 244                 speedp &= ~0x200;
 245                 /* Set IORDY for mode 3 or 4 */
 246                 if(mode_wanted == 3 || mode_wanted == 4)
 247                         speedp |= 0x200;
 248                 pci_write_config_word(hwif->pci_dev, tfaddr-2, speedp);
 249         }
 250 }
 251
 252 /**
 253  *      config_siimage_chipset_for_pio  -       set drive timings
 254  *      @drive: drive to tune
 255  *      @speed we want
 256  *
 257  *      Compute the best pio mode we can for a given device. Also honour
 258  *      the timings for the driver when dealing with mixed devices. Some
 259  *      of this is ugly but its all wrapped up here
 260  *
 261  *      The SI680 can also do VDMA - we need to start using that
 262  *
 263  *      FIXME: we use the BIOS channel timings to avoid driving the task
 264  *      files too fast at the disk. We need to compute the master/slave
 265  *      drive PIO mode properly so that we can up the speed on a hotplug
 266  *      system.
 267  */
 268
 269 static void config_siimage_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 270 {
 271         u8 channel_timings      = siimage_taskfile_timing(HWIF(drive));
 272         u8 speed = 0, set_pio   = ide_get_best_pio_mode(drive, 4, 5, NULL);
 273
 274         /* WARNING PIO timing mess is going to happen b/w devices, argh */
 275         if ((channel_timings != set_pio) && (set_pio > channel_timings))
 276                 set_pio = channel_timings;
 277
 278         siimage_tuneproc(drive, set_pio);
 279         speed = XFER_PIO_0 + set_pio;
 280         if (set_speed)
 281                 (void) ide_config_drive_speed(drive, speed);
 282 }
 283
 284 static void config_chipset_for_pio (ide_drive_t *drive, byte set_speed)
 285 {
 286         config_siimage_chipset_for_pio(drive, set_speed);
 287 }
 288
 289 /**
 290  *      siimage_tune_chipset    -       set controller timings
 291  *      @drive: Drive to set up
 292  *      @xferspeed: speed we want to achieve
 293  *
 294  *      Tune the SII chipset for the desired mode. If we can't achieve
 295  *      the desired mode then tune for a lower one, but ultimately
 296  *      make the thing work.
 297  */
 298
 299 static int siimage_tune_chipset (ide_drive_t *drive, byte xferspeed)
 300 {
 301         u8 ultra6[]             = { 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 };
 302         u8 ultra5[]             = { 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01 };
 303         u16 dma[]               = { 0x2208, 0x10C2, 0x10C1 };
 304
 305         ide_hwif_t *hwif        = HWIF(drive);
 306         u16 ultra = 0, multi    = 0;
 307         u8 mode = 0, unit       = drive->select.b.unit;
 308         u8 speed                = ide_rate_filter(siimage_ratemask(drive), xferspeed);
 309         unsigned long base      = (unsigned long)hwif->hwif_data;
 310         u8 scsc = 0, addr_mask  = ((hwif->channel) ?
 311                                     ((hwif->mmio) ? 0xF4 : 0x84) :
 312                                     ((hwif->mmio) ? 0xB4 : 0x80));
 313
 314         unsigned long ma        = siimage_seldev(drive, 0x08);
 315         unsigned long ua        = siimage_seldev(drive, 0x0C);
 316
 317         if (hwif->mmio) {
 318                 scsc = hwif->INB(base + 0x4A);
 319                 mode = hwif->INB(base + addr_mask);
 320                 multi = hwif->INW(ma);
 321                 ultra = hwif->INW(ua);
 322         } else {
 323                 pci_read_config_byte(hwif->pci_dev, 0x8A, &scsc);
 324                 pci_read_config_byte(hwif->pci_dev, addr_mask, &mode);
 325                 pci_read_config_word(hwif->pci_dev, ma, &multi);
 326                 pci_read_config_word(hwif->pci_dev, ua, &ultra);
 327         }
 328
 329         mode &= ~((unit) ? 0x30 : 0x03);
 330         ultra &= ~0x3F;
 331         scsc = ((scsc & 0x30) == 0x00) ? 0 : 1;
 332
 333         scsc = is_sata(hwif) ? 1 : scsc;
 334
 335         switch(speed) {
 336                 case XFER_PIO_4:
 337                 case XFER_PIO_3:
 338                 case XFER_PIO_2:
 339                 case XFER_PIO_1:
 340                 case XFER_PIO_0:
 341                         siimage_tuneproc(drive, (speed - XFER_PIO_0));
 342                         mode |= ((unit) ? 0x10 : 0x01);
 343                         break;
 344                 case XFER_MW_DMA_2:
 345                 case XFER_MW_DMA_1:
 346                 case XFER_MW_DMA_0:
 347                         multi = dma[speed - XFER_MW_DMA_0];
 348                         mode |= ((unit) ? 0x20 : 0x02);
 349                         config_siimage_chipset_for_pio(drive, 0);
 350                         break;
 351                 case XFER_UDMA_6:
 352                 case XFER_UDMA_5:
 353                 case XFER_UDMA_4:
 354                 case XFER_UDMA_3:
 355                 case XFER_UDMA_2:
 356                 case XFER_UDMA_1:
 357                 case XFER_UDMA_0:
 358                         multi = dma[2];
 359                         ultra |= ((scsc) ? (ultra6[speed - XFER_UDMA_0]) :
 360                                            (ultra5[speed - XFER_UDMA_0]));
 361                         mode |= ((unit) ? 0x30 : 0x03);
 362                         config_siimage_chipset_for_pio(drive, 0);
 363                         break;
 364                 default:
 365                         return 1;
 366         }
 367
 368         if (hwif->mmio) {
 369                 hwif->OUTB(mode, base + addr_mask);
 370                 hwif->OUTW(multi, ma);
 371                 hwif->OUTW(ultra, ua);
 372         } else {
 373                 pci_write_config_byte(hwif->pci_dev, addr_mask, mode);
 374                 pci_write_config_word(hwif->pci_dev, ma, multi);
 375                 pci_write_config_word(hwif->pci_dev, ua, ultra);
 376         }
 377         return (ide_config_drive_speed(drive, speed));
 378 }
 379
 380 /**
 381  *      config_chipset_for_dma  -       configure for DMA
 382  *      @drive: drive to configure
 383  *
 384  *      Called by the IDE layer when it wants the timings set up.
 385  *      For the CMD680 we also need to set up the PIO timings and
 386  *      enable DMA.
 387  */
 388
 389 static int config_chipset_for_dma (ide_drive_t *drive)
 390 {
 391         u8 speed        = ide_dma_speed(drive, siimage_ratemask(drive));
 392
 393         config_chipset_for_pio(drive, !speed);
 394
 395         if (!speed)
 396                 return 0;
 397
 398         if (ide_set_xfer_rate(drive, speed))
 399                 return 0;
 400
 401         if (!drive->init_speed)
 402                 drive->init_speed = speed;
 403
 404         return ide_dma_enable(drive);
 405 }
 406
 407 /**
 408  *      siimage_configure_drive_for_dma -       set up for DMA transfers
 409  *      @drive: drive we are going to set up
 410  *
 411  *      Set up the drive for DMA, tune the controller and drive as
 412  *      required. If the drive isn't suitable for DMA or we hit
 413  *      other problems then we will drop down to PIO and set up
 414  *      PIO appropriately
 415  */
 416
 417 static int siimage_config_drive_for_dma (ide_drive_t *drive)
 418 {
 419         ide_hwif_t *hwif        = HWIF(drive);
 420         struct hd_driveid *id   = drive->id;
 421
 422         if ((id->capability & 1) != 0 && drive->autodma) {
 423                 /* Consult the list of known "bad" drives */
 424                 if (__ide_dma_bad_drive(drive))
 425                         goto fast_ata_pio;
 426
 427                 if ((id->field_valid & 4) && siimage_ratemask(drive)) {
 428                         if (id->dma_ultra & hwif->ultra_mask) {
 429                                 /* Force if Capable UltraDMA */
 430                                 int dma = config_chipset_for_dma(drive);
 431                                 if ((id->field_valid & 2) && !dma)
 432                                         goto try_dma_modes;
 433                         }
 434                 } else if (id->field_valid & 2) {
 435 try_dma_modes:
 436                         if ((id->dma_mword & hwif->mwdma_mask) ||
 437                             (id->dma_1word & hwif->swdma_mask)) {
 438                                 /* Force if Capable regular DMA modes */
 439                                 if (!config_chipset_for_dma(drive))
 440                                         goto no_dma_set;
 441                         }
 442                 } else if (__ide_dma_good_drive(drive) &&
 443                            (id->eide_dma_time < 150)) {
 444                         /* Consult the list of known "good" drives */
 445                         if (!config_chipset_for_dma(drive))
 446                                 goto no_dma_set;
 447                 } else {
 448                         goto fast_ata_pio;
 449                 }
 450                 return hwif->ide_dma_on(drive);
 451         } else if ((id->capability & 8) || (id->field_valid & 2)) {
 452 fast_ata_pio:
 453 no_dma_set:
 454                 config_chipset_for_pio(drive, 1);
 455                 return hwif->ide_dma_off_quietly(drive);
 456         }
 457         /* IORDY not supported */
 458         return 0;
 459 }
 460
 461 /* returns 1 if dma irq issued, 0 otherwise */
 462 static int siimage_io_ide_dma_test_irq (ide_drive_t *drive)
 463 {
 464         ide_hwif_t *hwif        = HWIF(drive);
 465         u8 dma_altstat          = 0;
 466         unsigned long addr      = siimage_selreg(hwif, 1);
 467
 468         /* return 1 if INTR asserted */
 469         if ((hwif->INB(hwif->dma_status) & 4) == 4)
 470                 return 1;
 471
 472         /* return 1 if Device INTR asserted */
 473         pci_read_config_byte(hwif->pci_dev, addr, &dma_altstat);
 474         if (dma_altstat & 8)
 475                 return 0;       //return 1;
 476         return 0;
 477 }
 478
 479 #if 0
 480 /**
 481  *      siimage_mmio_ide_dma_count      -       DMA bytes done
 482  *      @drive
 483  *
 484  *      If we are doing VDMA the CMD680 requires a little bit
 485  *      of more careful handling and we have to read the counts
 486  *      off ourselves. For non VDMA life is normal.
 487  */
 488
 489 static int siimage_mmio_ide_dma_count (ide_drive_t *drive)
 490 {
 491 #ifdef SIIMAGE_VIRTUAL_DMAPIO
 492         struct request *rq      = HWGROUP(drive)->rq;
 493         ide_hwif_t *hwif        = HWIF(drive);
 494         u32 count               = (rq->nr_sectors * SECTOR_SIZE);
 495         u32 rcount              = 0;
 496         unsigned long addr      = siimage_selreg(hwif, 0x1C);
 497
 498         hwif->OUTL(count, addr);
 499         rcount = hwif->INL(addr);
 500
 501         printk("\n%s: count = %d, rcount = %d, nr_sectors = %lu\n",
 502                 drive->name, count, rcount, rq->nr_sectors);
 503
 504 #endif /* SIIMAGE_VIRTUAL_DMAPIO */
 505         return __ide_dma_count(drive);
 506 }
 507 #endif
 508
 509 /**
 510  *      siimage_mmio_ide_dma_test_irq   -       check we caused an IRQ
 511  *      @drive: drive we are testing
 512  *
 513  *      Check if we caused an IDE DMA interrupt. We may also have caused
 514  *      SATA status interrupts, if so we clean them up and continue.
 515  */
 516
 517 static int siimage_mmio_ide_dma_test_irq (ide_drive_t *drive)
 518 {
 519         ide_hwif_t *hwif        = HWIF(drive);
 520         unsigned long base      = (unsigned long)hwif->hwif_data;
 521         unsigned long addr      = siimage_selreg(hwif, 0x1);
 522
 523         if (SATA_ERROR_REG) {
 524                 u32 ext_stat = hwif->INL(base + 0x10);
 525                 u8 watchdog = 0;
 526                 if (ext_stat & ((hwif->channel) ? 0x40 : 0x10)) {
 527                         u32 sata_error = hwif->INL(SATA_ERROR_REG);
 528                         hwif->OUTL(sata_error, SATA_ERROR_REG);
 529                         watchdog = (sata_error & 0x00680000) ? 1 : 0;
 530 #if 1
 531                         printk(KERN_WARNING "%s: sata_error = 0x%08x, "
 532                                 "watchdog = %d, %s\n",
 533                                 drive->name, sata_error, watchdog,
 534                                 __FUNCTION__);
 535 #endif
 536
 537                 } else {
 538                         watchdog = (ext_stat & 0x8000) ? 1 : 0;
 539                 }
 540                 ext_stat >>= 16;
 541
 542                 if (!(ext_stat & 0x0404) && !watchdog)
 543                         return 0;
 544         }
 545
 546         /* return 1 if INTR asserted */
 547         if ((hwif->INB(hwif->dma_status) & 0x04) == 0x04)
 548                 return 1;
 549
 550         /* return 1 if Device INTR asserted */
 551         if ((hwif->INB(addr) & 8) == 8)
 552                 return 0;       //return 1;
 553
 554         return 0;
 555 }
 556
 557 static int siimage_mmio_ide_dma_verbose (ide_drive_t *drive)
 558 {
 559         int temp = __ide_dma_verbose(drive);
 560         return temp;
 561 }
 562
 563 /**
 564  *      siimage_busproc         -       bus isolation ioctl
 565  *      @drive: drive to isolate/restore
 566  *      @state: bus state to set
 567  *
 568  *      Used by the SII3112 to handle bus isolation. As this is a
 569  *      SATA controller the work required is quite limited, we
 570  *      just have to clean up the statistics
 571  */
 572
 573 static int siimage_busproc (ide_drive_t * drive, int state)
 574 {
 575         ide_hwif_t *hwif        = HWIF(drive);
 576         u32 stat_config         = 0;
 577         unsigned long addr      = siimage_selreg(hwif, 0);
 578
 579         if (hwif->mmio) {
 580                 stat_config = hwif->INL(addr);
 581         } else
 582                 pci_read_config_dword(hwif->pci_dev, addr, &stat_config);
 583
 584         switch (state) {
 585                 case BUSSTATE_ON:
 586                         hwif->drives[0].failures = 0;
 587                         hwif->drives[1].failures = 0;
 588                         break;
 589                 case BUSSTATE_OFF:
 590                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 591                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 592                         break;
 593                 case BUSSTATE_TRISTATE:
 594                         hwif->drives[0].failures = hwif->drives[0].max_failures + 1;
 595                         hwif->drives[1].failures = hwif->drives[1].max_failures + 1;
 596                         break;
 597                 default:
 598                         return -EINVAL;
 599         }
 600         hwif->bus_state = state;
 601         return 0;
 602 }
 603
 604 /**
 605  *      siimage_reset_poll      -       wait for sata reset
 606  *      @drive: drive we are resetting
 607  *
 608  *      Poll the SATA phy and see whether it has come back from the dead
 609  *      yet.
 610  */
 611
 612 static int siimage_reset_poll (ide_drive_t *drive)
 613 {
 614         if (SATA_STATUS_REG) {
 615                 ide_hwif_t *hwif        = HWIF(drive);
 616
 617                 if ((hwif->INL(SATA_STATUS_REG) & 0x03) != 0x03) {
 618                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 619                                 hwif->name, hwif->INL(SATA_STATUS_REG));
 620                         HWGROUP(drive)->poll_timeout = 0;
 621                         return ide_started;
 622                 }
 623                 return 0;
 624         } else {
 625                 return 0;
 626         }
 627 }
 628
 629 /**
 630  *      siimage_pre_reset       -       reset hook
 631  *      @drive: IDE device being reset
 632  *
 633  *      For the SATA devices we need to handle recalibration/geometry
 634  *      differently
 635  */
 636
 637 static void siimage_pre_reset (ide_drive_t *drive)
 638 {
 639         if (drive->media != ide_disk)
 640                 return;
 641
 642         if (is_sata(HWIF(drive)))
 643         {
 644                 drive->special.b.set_geometry = 0;
 645                 drive->special.b.recalibrate = 0;
 646         }
 647 }
 648
 649 /**
 650  *      siimage_reset   -       reset a device on an siimage controller
 651  *      @drive: drive to reset
 652  *
 653  *      Perform a controller level reset fo the device. For
 654  *      SATA we must also check the PHY.
 655  */
 656
 657 static void siimage_reset (ide_drive_t *drive)
 658 {
 659         ide_hwif_t *hwif        = HWIF(drive);
 660         u8 reset                = 0;
 661         unsigned long addr      = siimage_selreg(hwif, 0);
 662
 663         if (hwif->mmio) {
 664                 reset = hwif->INB(addr);
 665                 hwif->OUTB((reset|0x03), addr);
 666                 /* FIXME:posting */
 667                 udelay(25);
 668                 hwif->OUTB(reset, addr);
 669                 (void) hwif->INB(addr);
 670         } else {
 671                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 672                 pci_write_config_byte(hwif->pci_dev, addr, reset|0x03);
 673                 udelay(25);
 674                 pci_write_config_byte(hwif->pci_dev, addr, reset);
 675                 pci_read_config_byte(hwif->pci_dev, addr, &reset);
 676         }
 677
 678         if (SATA_STATUS_REG) {
 679                 u32 sata_stat = hwif->INL(SATA_STATUS_REG);
 680                 printk(KERN_WARNING "%s: reset phy, status=0x%08x, %s\n",
 681                         hwif->name, sata_stat, __FUNCTION__);
 682                 if (!(sata_stat)) {
 683                         printk(KERN_WARNING "%s: reset phy dead, status=0x%08x\n",
 684                                 hwif->name, sata_stat);
 685                         drive->failures++;
 686                 }
 687         }
 688
 689 }
 690
 691 /**
 692  *      proc_reports_siimage            -       add siimage controller to proc
 693  *      @dev: PCI device
 694  *      @clocking: SCSC value
 695  *      @name: controller name
 696  *
 697  *      Report the clocking mode of the controller and add it to
 698  *      the /proc interface layer
 699  */
 700
 701 static void proc_reports_siimage (struct pci_dev *dev, u8 clocking, const char *name)
 702 {
 703         if (!pdev_is_sata(dev)) {
 704                 printk(KERN_INFO "%s: BASE CLOCK ", name);
 705                 clocking &= 0x03;
 706                 switch (clocking) {
 707                         case 0x03: printk("DISABLED!\n"); break;
 708                         case 0x02: printk("== 2X PCI\n"); break;
 709                         case 0x01: printk("== 133\n"); break;
 710                         case 0x00: printk("== 100\n"); break;
 711                 }
 712         }
 713 }
 714
 715 /**
 716  *      setup_mmio_siimage      -       switch an SI controller into MMIO
 717  *      @dev: PCI device we are configuring
 718  *      @name: device name
 719  *
 720  *      Attempt to put the device into mmio mode. There are some slight
 721  *      complications here with certain systems where the mmio bar isnt
 722  *      mapped so we have to be sure we can fall back to I/O.
 723  */
 724
 725 static unsigned int setup_mmio_siimage (struct pci_dev *dev, const char *name)
 726 {
 727         unsigned long bar5      = pci_resource_start(dev, 5);
 728         unsigned long barsize   = pci_resource_len(dev, 5);
 729         u8 tmpbyte      = 0;
 730         void __iomem *ioaddr;
 731
 732         /*
 733          *      Drop back to PIO if we can't map the mmio. Some
 734          *      systems seem to get terminally confused in the PCI
 735          *      spaces.
 736          */
 737
 738         if(!request_mem_region(bar5, barsize, name))
 739         {
 740                 printk(KERN_WARNING "siimage: IDE controller MMIO ports not available.\n");
 741                 return 0;
 742         }
 743
 744         ioaddr = ioremap(bar5, barsize);
 745
 746         if (ioaddr == NULL)
 747         {
 748                 release_mem_region(bar5, barsize);
 749                 return 0;
 750         }
 751
 752         pci_set_master(dev);
 753         pci_set_drvdata(dev, (void *) ioaddr);
 754
 755         if (pdev_is_sata(dev)) {
 756                 writel(0, ioaddr + 0x148);
 757                 writel(0, ioaddr + 0x1C8);
 758         }
 759
 760         writeb(0, ioaddr + 0xB4);
 761         writeb(0, ioaddr + 0xF4);
 762         tmpbyte = readb(ioaddr + 0x4A);
 763
 764         switch(tmpbyte & 0x30) {
 765                 case 0x00:
 766                         /* In 100 MHz clocking, try and switch to 133 */
 767                         writeb(tmpbyte|0x10, ioaddr + 0x4A);
 768                         break;
 769                 case 0x10:
 770                         /* On 133Mhz clocking */
 771                         break;
 772                 case 0x20:
 773                         /* On PCIx2 clocking */
 774                         break;
 775                 case 0x30:
 776                         /* Clocking is disabled */
 777                         /* 133 clock attempt to force it on */
 778                         writeb(tmpbyte & ~0x20, ioaddr + 0x4A);
 779                         break;
 780         }
 781
 782         writeb(      0x72, ioaddr + 0xA1);
 783         writew(    0x328A, ioaddr + 0xA2);
 784         writel(0x62DD62DD, ioaddr + 0xA4);
 785         writel(0x43924392, ioaddr + 0xA8);
 786         writel(0x40094009, ioaddr + 0xAC);
 787         writeb(      0x72, ioaddr + 0xE1);
 788         writew(    0x328A, ioaddr + 0xE2);
 789         writel(0x62DD62DD, ioaddr + 0xE4);
 790         writel(0x43924392, ioaddr + 0xE8);
 791         writel(0x40094009, ioaddr + 0xEC);
 792
 793         if (pdev_is_sata(dev)) {
 794                 writel(0xFFFF0000, ioaddr + 0x108);
 795                 writel(0xFFFF0000, ioaddr + 0x188);
 796                 writel(0x00680000, ioaddr + 0x148);
 797                 writel(0x00680000, ioaddr + 0x1C8);
 798         }
 799
 800         tmpbyte = readb(ioaddr + 0x4A);
 801
 802         proc_reports_siimage(dev, (tmpbyte>>4), name);
 803         return 1;
 804 }
 805
 806 /**
 807  *      init_chipset_siimage    -       set up an SI device
 808  *      @dev: PCI device
 809  *      @name: device name
 810  *
 811  *      Perform the initial PCI set up for this device. Attempt to switch
 812  *      to 133MHz clocking if the system isn't already set up to do it.
 813  */
 814
 815 static unsigned int __devinit init_chipset_siimage(struct pci_dev *dev, const char *name)
 816 {
 817         u32 class_rev   = 0;
 818         u8 tmpbyte      = 0;
 819         u8 BA5_EN       = 0;
 820
 821         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
 822         class_rev &= 0xff;
 823         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (class_rev) ? 1 : 255);
 824
 825         pci_read_config_byte(dev, 0x8A, &BA5_EN);
 826         if ((BA5_EN & 0x01) || (pci_resource_start(dev, 5))) {
 827                 if (setup_mmio_siimage(dev, name)) {
 828                         return 0;
 829                 }
 830         }
 831
 832         pci_write_config_byte(dev, 0x80, 0x00);
 833         pci_write_config_byte(dev, 0x84, 0x00);
 834         pci_read_config_byte(dev, 0x8A, &tmpbyte);
 835         switch(tmpbyte & 0x30) {
 836                 case 0x00:
 837                         /* 133 clock attempt to force it on */
 838                         pci_write_config_byte(dev, 0x8A, tmpbyte|0x10);
 839                 case 0x30:
 840                         /* if clocking is disabled */
 841                         /* 133 clock attempt to force it on */
 842                         pci_write_config_byte(dev, 0x8A, tmpbyte & ~0x20);
 843                 case 0x10:
 844                         /* 133 already */
 845                         break;
 846                 case 0x20:
 847                         /* BIOS set PCI x2 clocking */
 848                         break;
 849         }
 850
 851         pci_read_config_byte(dev,   0x8A, &tmpbyte);
 852
 853         pci_write_config_byte(dev,  0xA1, 0x72);
 854         pci_write_config_word(dev,  0xA2, 0x328A);
 855         pci_write_config_dword(dev, 0xA4, 0x62DD62DD);
 856         pci_write_config_dword(dev, 0xA8, 0x43924392);
 857         pci_write_config_dword(dev, 0xAC, 0x40094009);
 858         pci_write_config_byte(dev,  0xB1, 0x72);
 859         pci_write_config_word(dev,  0xB2, 0x328A);
 860         pci_write_config_dword(dev, 0xB4, 0x62DD62DD);
 861         pci_write_config_dword(dev, 0xB8, 0x43924392);
 862         pci_write_config_dword(dev, 0xBC, 0x40094009);
 863
 864         proc_reports_siimage(dev, (tmpbyte>>4), name);
 865         return 0;
 866 }
 867
 868 /**
 869  *      init_mmio_iops_siimage  -       set up the iops for MMIO
 870  *      @hwif: interface to set up
 871  *
 872  *      The basic setup here is fairly simple, we can use standard MMIO
 873  *      operations. However we do have to set the taskfile register offsets
 874  *      by hand as there isnt a standard defined layout for them this
 875  *      time.
 876  *
 877  *      The hardware supports buffered taskfiles and also some rather nice
 878  *      extended PRD tables. Unfortunately right now we don't.
 879  */
 880
 881 static void __devinit init_mmio_iops_siimage(ide_hwif_t *hwif)
 882 {
 883         struct pci_dev *dev     = hwif->pci_dev;
 884         void *addr              = pci_get_drvdata(dev);
 885         u8 ch                   = hwif->channel;
 886         hw_regs_t               hw;
 887         unsigned long           base;
 888
 889         /*
 890          *      Fill in the basic HWIF bits
 891          */
 892
 893         default_hwif_mmiops(hwif);
 894         hwif->hwif_data                 = addr;
 895
 896         /*
 897          *      Now set up the hw. We have to do this ourselves as
 898          *      the MMIO layout isnt the same as the the standard port
 899          *      based I/O
 900          */
 901
 902         memset(&hw, 0, sizeof(hw_regs_t));
 903         hw.priv                         = addr;
 904
 905         base                            = (unsigned long)addr;
 906         if(ch)
 907                 base += 0xC0;
 908         else
 909                 base += 0x80;
 910
 911         /*
 912          *      The buffered task file doesn't have status/control
 913          *      so we can't currently use it sanely since we want to
 914          *      use LBA48 mode.
 915          */
 916 //      base += 0x10;
 917 //      hwif->no_lba48 = 1;
 918
 919         hw.io_ports[IDE_DATA_OFFSET]    = base;
 920         hw.io_ports[IDE_ERROR_OFFSET]   = base + 1;
 921         hw.io_ports[IDE_NSECTOR_OFFSET] = base + 2;
 922         hw.io_ports[IDE_SECTOR_OFFSET]  = base + 3;
 923         hw.io_ports[IDE_LCYL_OFFSET]    = base + 4;
 924         hw.io_ports[IDE_HCYL_OFFSET]    = base + 5;
 925         hw.io_ports[IDE_SELECT_OFFSET]  = base + 6;
 926         hw.io_ports[IDE_STATUS_OFFSET]  = base + 7;
 927         hw.io_ports[IDE_CONTROL_OFFSET] = base + 10;
 928
 929         hw.io_ports[IDE_IRQ_OFFSET]     = 0;
 930
 931         if (pdev_is_sata(dev)) {
 932                 base = (unsigned long) addr;
 933                 if(ch)
 934                         base += 0x80;
 935                 hw.sata_scr[SATA_STATUS_OFFSET] = base + 0x104;
 936                 hw.sata_scr[SATA_ERROR_OFFSET]  = base + 0x108;
 937                 hw.sata_scr[SATA_CONTROL_OFFSET]= base + 0x100;
 938                 hw.sata_misc[SATA_MISC_OFFSET]  = base + 0x140;
 939                 hw.sata_misc[SATA_PHY_OFFSET]   = base + 0x144;
 940                 hw.sata_misc[SATA_IEN_OFFSET]   = base + 0x148;
 941         }
 942
 943         hw.irq                          = hwif->pci_dev->irq;
 944
 945         memcpy(&hwif->hw, &hw, sizeof(hw));
 946         memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->hw.io_ports));
 947
 948         if (is_sata(hwif)) {
 949                 memcpy(hwif->sata_scr, hwif->hw.sata_scr, sizeof(hwif->hw.sata_scr));
 950                 memcpy(hwif->sata_misc, hwif->hw.sata_misc, sizeof(hwif->hw.sata_misc));
 951         }
 952
 953         hwif->irq                       = hw.irq;
 954
 955         base = (unsigned long) addr;
 956
 957 #ifdef SIIMAGE_LARGE_DMA
 958 /* Watch the brackets - even Ken and Dennis get some language design wrong */
 959         hwif->dma_base                  = base + (ch ? 0x18 : 0x10);
 960         hwif->dma_base2                 = base + (ch ? 0x08 : 0x00);
 961         hwif->dma_prdtable              = hwif->dma_base2 + 4;
 962 #else /* ! SIIMAGE_LARGE_DMA */
 963         hwif->dma_base                  = base + (ch ? 0x08 : 0x00);
 964         hwif->dma_base2                 = base + (ch ? 0x18 : 0x10);
 965 #endif /* SIIMAGE_LARGE_DMA */
 966         hwif->mmio                      = 2;
 967 }
 968
 969 static int is_dev_seagate_sata(ide_drive_t *drive)
 970 {
 971         const char *s = &drive->id->model[0];
 972         unsigned len;
 973
 974         if (!drive->present)
 975                 return 0;
 976
 977         len = strnlen(s, sizeof(drive->id->model));
 978
 979         if ((len > 4) && (!memcmp(s, "ST", 2))) {
 980                 if ((!memcmp(s + len - 2, "AS", 2)) ||
 981                     (!memcmp(s + len - 3, "ASL", 3))) {
 982                         printk(KERN_INFO "%s: applying pessimistic Seagate "
 983                                          "errata fix\n", drive->name);
 984                         return 1;
 985                 }
 986         }
 987         return 0;
 988 }
 989
 990 /**
 991  *      init_iops_siimage       -       set up iops
 992  *      @hwif: interface to set up
 993  *
 994  *      Do the basic setup for the SIIMAGE hardware interface
 995  *      and then do the MMIO setup if we can. This is the first
 996  *      look in we get for setting up the hwif so that we
 997  *      can get the iops right before using them.
 998  */
 999
1000 static void __devinit init_iops_siimage(ide_hwif_t *hwif)
1001 {
1002         struct pci_dev *dev     = hwif->pci_dev;
1003         u32 class_rev           = 0;
1004
1005         pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1006         class_rev &= 0xff;
1007
1008         hwif->hwif_data = NULL;
1009
1010         hwif->rqsize = 128;
1011         if (is_sata(hwif) && is_dev_seagate_sata(&hwif->drives[0]))
1012                 hwif->rqsize = 15;
1013
1014         if (pci_get_drvdata(dev) == NULL)
1015                 return;
1016         init_mmio_iops_siimage(hwif);
1017 }
1018
1019 /**
1020  *      ata66_siimage   -       check for 80 pin cable
1021  *      @hwif: interface to check
1022  *
1023  *      Check for the presence of an ATA66 capable cable on the
1024  *      interface.
1025  */
1026
1027 static unsigned int __devinit ata66_siimage(ide_hwif_t *hwif)
1028 {
1029         unsigned long addr = siimage_selreg(hwif, 0);
1030         if (pci_get_drvdata(hwif->pci_dev) == NULL) {
1031                 u8 ata66 = 0;
1032                 pci_read_config_byte(hwif->pci_dev, addr, &ata66);
1033                 return (ata66 & 0x01) ? 1 : 0;
1034         }
1035
1036         return (hwif->INB(addr) & 0x01) ? 1 : 0;
1037 }
1038
1039 /**
1040  *      init_hwif_siimage       -       set up hwif structs
1041  *      @hwif: interface to set up
1042  *
1043  *      We do the basic set up of the interface structure. The SIIMAGE
1044  *      requires several custom handlers so we override the default
1045  *      ide DMA handlers appropriately
1046  */
1047
1048 static void __devinit init_hwif_siimage(ide_hwif_t *hwif)
1049 {
1050         hwif->autodma = 0;
1051
1052         hwif->resetproc = &siimage_reset;
1053         hwif->speedproc = &siimage_tune_chipset;
1054         hwif->tuneproc  = &siimage_tuneproc;
1055         hwif->reset_poll = &siimage_reset_poll;
1056         hwif->pre_reset = &siimage_pre_reset;
1057
1058         if(is_sata(hwif))
1059                 hwif->busproc   = &siimage_busproc;
1060
1061         if (!hwif->dma_base) {
1062                 hwif->drives[0].autotune = 1;
1063                 hwif->drives[1].autotune = 1;
1064                 return;
1065         }
1066
1067         hwif->ultra_mask = 0x7f;
1068         hwif->mwdma_mask = 0x07;
1069         hwif->swdma_mask = 0x07;
1070
1071         if (!is_sata(hwif))
1072                 hwif->atapi_dma = 1;
1073
1074         hwif->ide_dma_check = &siimage_config_drive_for_dma;
1075         if (!(hwif->udma_four))
1076                 hwif->udma_four = ata66_siimage(hwif);
1077
1078         if (hwif->mmio) {
1079                 hwif->ide_dma_test_irq = &siimage_mmio_ide_dma_test_irq;
1080                 hwif->ide_dma_verbose = &siimage_mmio_ide_dma_verbose;
1081         } else {
1082                 hwif->ide_dma_test_irq = & siimage_io_ide_dma_test_irq;
1083         }
1084
1085         /*
1086          *      The BIOS often doesn't set up DMA on this controller
1087          *      so we always do it.
1088          */
1089
1090         hwif->autodma = 1;
1091         hwif->drives[0].autodma = hwif->autodma;
1092         hwif->drives[1].autodma = hwif->autodma;
1093 }
1094
1095 #define DECLARE_SII_DEV(name_str)                       \
1096         {                                               \
1097                 .name           = name_str,             \
1098                 .init_chipset   = init_chipset_siimage, \
1099                 .init_iops      = init_iops_siimage,    \
1100                 .init_hwif      = init_hwif_siimage,    \
1101                 .channels       = 2,                    \
1102                 .autodma        = AUTODMA,              \
1103                 .bootable       = ON_BOARD,             \
1104         }
1105
1106 static ide_pci_device_t siimage_chipsets[] __devinitdata = {
1107         /* 0 */ DECLARE_SII_DEV("SiI680"),
1108         /* 1 */ DECLARE_SII_DEV("SiI3112 Serial ATA"),
1109         /* 2 */ DECLARE_SII_DEV("Adaptec AAR-1210SA")
1110 };
1111
1112 /**
1113  *      siimage_init_one        -       pci layer discovery entry
1114  *      @dev: PCI device
1115  *      @id: ident table entry
1116  *
1117  *      Called by the PCI code when it finds an SI680 or SI3112 controller.
1118  *      We then use the IDE PCI generic helper to do most of the work.
1119  */
1120
1121 static int __devinit siimage_init_one(struct pci_dev *dev, const struct pci_device_id *id)
1122 {
1123         ide_setup_pci_device(dev, &siimage_chipsets[id->driver_data]);
1124         return 0;
1125 }
1126
1127 static struct pci_device_id siimage_pci_tbl[] = {
1128         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680,  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1129 #ifdef CONFIG_BLK_DEV_IDE_SATA
1130         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_3112, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
1131         { PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_1210SA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
1132 #endif
1133         { 0, },
1134 };
1135 MODULE_DEVICE_TABLE(pci, siimage_pci_tbl);
1136
1137 static struct pci_driver driver = {
1138         .name           = "SiI_IDE",
1139         .id_table       = siimage_pci_tbl,
1140         .probe          = siimage_init_one,
1141 };
1142
1143 static int siimage_ide_init(void)
1144 {
1145         return ide_pci_register_driver(&driver);
1146 }
1147
1148 module_init(siimage_ide_init);
1149
1150 MODULE_AUTHOR("Andre Hedrick, Alan Cox");
1151 MODULE_DESCRIPTION("PCI driver module for SiI IDE");
1152 MODULE_LICENSE("GPL");