drivers/char/drm/radeon_irq.c

   1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*-
   2  *
   3  * Copyright (C) The Weather Channel, Inc.  2002.  All Rights Reserved.
   4  *
   5  * The Weather Channel (TM) funded Tungsten Graphics to develop the
   6  * initial release of the Radeon 8500 driver under the XFree86 license.
   7  * This notice must be preserved.
   8  *
   9  * Permission is hereby granted, free of charge, to any person obtaining a
  10  * copy of this software and associated documentation files (the "Software"),
  11  * to deal in the Software without restriction, including without limitation
  12  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  13  * and/or sell copies of the Software, and to permit persons to whom the
  14  * Software is furnished to do so, subject to the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the next
  17  * paragraph) shall be included in all copies or substantial portions of the
  18  * Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  23  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  24  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  25  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  26  * DEALINGS IN THE SOFTWARE.
  27  *
  28  * Authors:
  29  *    Keith Whitwell <keith@tungstengraphics.com>
  30  *    Michel Dänzer <michel@daenzer.net>
  31  */
  32
  33 #include "radeon.h"
  34 #include "drmP.h"
  35 #include "drm.h"
  36 #include "radeon_drm.h"
  37 #include "radeon_drv.h"
  38
  39 /* Interrupts - Used for device synchronization and flushing in the
  40  * following circumstances:
  41  *
  42  * - Exclusive FB access with hw idle:
  43  *    - Wait for GUI Idle (?) interrupt, then do normal flush.
  44  *
  45  * - Frame throttling, NV_fence:
  46  *    - Drop marker irq's into command stream ahead of time.
  47  *    - Wait on irq's with lock *not held*
  48  *    - Check each for termination condition
  49  *
  50  * - Internally in cp_getbuffer, etc:
  51  *    - as above, but wait with lock held???
  52  *
  53  * NOTE: These functions are misleadingly named -- the irq's aren't
  54  * tied to dma at all, this is just a hangover from dri prehistory.
  55  */
  56
  57 irqreturn_t radeon_driver_irq_handler( DRM_IRQ_ARGS )
  58 {
  59         drm_device_t *dev = (drm_device_t *) arg;
  60         drm_radeon_private_t *dev_priv =
  61            (drm_radeon_private_t *)dev->dev_private;
  62         u32 stat;
  63
  64         /* Only consider the bits we're interested in - others could be used
  65          * outside the DRM
  66          */
  67         stat = RADEON_READ(RADEON_GEN_INT_STATUS)
  68              & (RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT);
  69         if (!stat)
  70                 return IRQ_NONE;
  71
  72         /* SW interrupt */
  73         if (stat & RADEON_SW_INT_TEST) {
  74                 DRM_WAKEUP( &dev_priv->swi_queue );
  75         }
  76
  77         /* VBLANK interrupt */
  78         if (stat & RADEON_CRTC_VBLANK_STAT) {
  79                 atomic_inc(&dev->vbl_received);
  80                 DRM_WAKEUP(&dev->vbl_queue);
  81                 DRM(vbl_send_signals)( dev );
  82         }
  83
  84         /* Acknowledge interrupts we handle */
  85         RADEON_WRITE(RADEON_GEN_INT_STATUS, stat);
  86         return IRQ_HANDLED;
  87 }
  88
  89 static __inline__ void radeon_acknowledge_irqs(drm_radeon_private_t *dev_priv)
  90 {
  91         u32 tmp = RADEON_READ( RADEON_GEN_INT_STATUS )
  92                 & (RADEON_SW_INT_TEST_ACK | RADEON_CRTC_VBLANK_STAT);
  93         if (tmp)
  94                 RADEON_WRITE( RADEON_GEN_INT_STATUS, tmp );
  95 }
  96
  97 int radeon_emit_irq(drm_device_t *dev)
  98 {
  99         drm_radeon_private_t *dev_priv = dev->dev_private;
 100         unsigned int ret;
 101         RING_LOCALS;
 102
 103         atomic_inc(&dev_priv->swi_emitted);
 104         ret = atomic_read(&dev_priv->swi_emitted);
 105
 106         BEGIN_RING( 4 );
 107         OUT_RING_REG( RADEON_LAST_SWI_REG, ret );
 108         OUT_RING_REG( RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE );
 109         ADVANCE_RING();
 110         COMMIT_RING();
 111
 112         return ret;
 113 }
 114
 115
 116 int radeon_wait_irq(drm_device_t *dev, int swi_nr)
 117 {
 118         drm_radeon_private_t *dev_priv =
 119            (drm_radeon_private_t *)dev->dev_private;
 120         int ret = 0;
 121
 122         if (RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr)
 123                 return 0;
 124
 125         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 126
 127         /* This is a hack to work around mysterious freezes on certain
 128          * systems:
 129          */
 130         radeon_acknowledge_irqs( dev_priv );
 131
 132         DRM_WAIT_ON( ret, dev_priv->swi_queue, 3 * DRM_HZ,
 133                      RADEON_READ( RADEON_LAST_SWI_REG ) >= swi_nr );
 134
 135         return ret;
 136 }
 137
 138 int radeon_emit_and_wait_irq(drm_device_t *dev)
 139 {
 140         return radeon_wait_irq( dev, radeon_emit_irq(dev) );
 141 }
 142
 143
 144 int radeon_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence)
 145 {
 146         drm_radeon_private_t *dev_priv =
 147            (drm_radeon_private_t *)dev->dev_private;
 148         unsigned int cur_vblank;
 149         int ret = 0;
 150
 151         if ( !dev_priv ) {
 152                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
 153                 return DRM_ERR(EINVAL);
 154         }
 155
 156         radeon_acknowledge_irqs( dev_priv );
 157
 158         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 159
 160         /* Assume that the user has missed the current sequence number
 161          * by about a day rather than she wants to wait for years
 162          * using vertical blanks...
 163          */
 164         DRM_WAIT_ON( ret, dev->vbl_queue, 3*DRM_HZ,
 165                      ( ( ( cur_vblank = atomic_read(&dev->vbl_received ) )
 166                          - *sequence ) <= (1<<23) ) );
 167
 168         *sequence = cur_vblank;
 169
 170         return ret;
 171 }
 172
 173
 174 /* Needs the lock as it touches the ring.
 175  */
 176 int radeon_irq_emit( DRM_IOCTL_ARGS )
 177 {
 178         DRM_DEVICE;
 179         drm_radeon_private_t *dev_priv = dev->dev_private;
 180         drm_radeon_irq_emit_t emit;
 181         int result;
 182
 183         LOCK_TEST_WITH_RETURN( dev, filp );
 184
 185         if ( !dev_priv ) {
 186                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
 187                 return DRM_ERR(EINVAL);
 188         }
 189
 190         DRM_COPY_FROM_USER_IOCTL( emit, (drm_radeon_irq_emit_t __user *)data,
 191                                   sizeof(emit) );
 192
 193         result = radeon_emit_irq( dev );
 194
 195         if ( DRM_COPY_TO_USER( emit.irq_seq, &result, sizeof(int) ) ) {
 196                 DRM_ERROR( "copy_to_user\n" );
 197                 return DRM_ERR(EFAULT);
 198         }
 199
 200         return 0;
 201 }
 202
 203
 204 /* Doesn't need the hardware lock.
 205  */
 206 int radeon_irq_wait( DRM_IOCTL_ARGS )
 207 {
 208         DRM_DEVICE;
 209         drm_radeon_private_t *dev_priv = dev->dev_private;
 210         drm_radeon_irq_wait_t irqwait;
 211
 212         if ( !dev_priv ) {
 213                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
 214                 return DRM_ERR(EINVAL);
 215         }
 216
 217         DRM_COPY_FROM_USER_IOCTL( irqwait, (drm_radeon_irq_wait_t __user*)data,
 218                                   sizeof(irqwait) );
 219
 220         return radeon_wait_irq( dev, irqwait.irq_seq );
 221 }
 222
 223
 224 /* drm_dma.h hooks
 225 */
 226 void DRM(driver_irq_preinstall)( drm_device_t *dev ) {
 227         drm_radeon_private_t *dev_priv =
 228                 (drm_radeon_private_t *)dev->dev_private;
 229
 230         /* Disable *all* interrupts */
 231         RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
 232
 233         /* Clear bits if they're already high */
 234         radeon_acknowledge_irqs( dev_priv );
 235 }
 236
 237 void DRM(driver_irq_postinstall)( drm_device_t *dev ) {
 238         drm_radeon_private_t *dev_priv =
 239                 (drm_radeon_private_t *)dev->dev_private;
 240
 241         atomic_set(&dev_priv->swi_emitted, 0);
 242         DRM_INIT_WAITQUEUE( &dev_priv->swi_queue );
 243
 244         /* Turn on SW and VBL ints */
 245         RADEON_WRITE( RADEON_GEN_INT_CNTL,
 246                       RADEON_CRTC_VBLANK_MASK |
 247                       RADEON_SW_INT_ENABLE );
 248 }
 249
 250 void DRM(driver_irq_uninstall)( drm_device_t *dev ) {
 251         drm_radeon_private_t *dev_priv =
 252                 (drm_radeon_private_t *)dev->dev_private;
 253         if (!dev_priv)
 254                 return;
 255
 256         /* Disable *all* interrupts */
 257         RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
 258 }