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initial commit with v2.6.9
[linux-2.6.9-moxart.git] / arch / sparc64 / kernel / time.c
blobb50e16d4922771f076e0ca4ec4b3a2b65e37c427
1 /* $Id: time.c,v 1.42 2002/01/23 14:33:55 davem Exp $
2 * time.c: UltraSparc timer and TOD clock support.
3 *
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
6 *
7 * Based largely on code which is:
8 *
9 * Copyright (C) 1996 Thomas K. Dyas (tdyas@eden.rutgers.edu)
10 */
11
12 #include <linux/config.h>
13 #include <linux/errno.h>
14 #include <linux/module.h>
15 #include <linux/sched.h>
16 #include <linux/kernel.h>
17 #include <linux/param.h>
18 #include <linux/string.h>
19 #include <linux/mm.h>
20 #include <linux/interrupt.h>
21 #include <linux/time.h>
22 #include <linux/timex.h>
23 #include <linux/init.h>
24 #include <linux/ioport.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/delay.h>
27 #include <linux/profile.h>
28 #include <linux/bcd.h>
29 #include <linux/jiffies.h>
30 #include <linux/cpufreq.h>
31 #include <linux/percpu.h>
32 #include <linux/profile.h>
33
34 #include <asm/oplib.h>
35 #include <asm/mostek.h>
36 #include <asm/timer.h>
37 #include <asm/irq.h>
38 #include <asm/io.h>
39 #include <asm/sbus.h>
40 #include <asm/fhc.h>
41 #include <asm/pbm.h>
42 #include <asm/ebus.h>
43 #include <asm/isa.h>
44 #include <asm/starfire.h>
45 #include <asm/smp.h>
46 #include <asm/sections.h>
47 #include <asm/cpudata.h>
48
49 spinlock_t mostek_lock = SPIN_LOCK_UNLOCKED;
50 spinlock_t rtc_lock = SPIN_LOCK_UNLOCKED;
51 unsigned long mstk48t02_regs = 0UL;
52 #ifdef CONFIG_PCI
53 unsigned long ds1287_regs = 0UL;
54 #endif
55
56 extern unsigned long wall_jiffies;
57
58 u64 jiffies_64 = INITIAL_JIFFIES;
59
60 EXPORT_SYMBOL(jiffies_64);
61
62 static unsigned long mstk48t08_regs = 0UL;
63 static unsigned long mstk48t59_regs = 0UL;
64
65 static int set_rtc_mmss(unsigned long);
66
67 struct sparc64_tick_ops *tick_ops;
68
69 #define TICK_PRIV_BIT (1UL << 63)
70
71 #ifdef CONFIG_SMP
72 unsigned long profile_pc(struct pt_regs *regs)
73 {
74 unsigned long pc = instruction_pointer(regs);
75
76 if (in_lock_functions(pc))
77 return regs->u_regs[UREG_RETPC];
78 return pc;
79 }
80 EXPORT_SYMBOL(profile_pc);
81 #endif
82
83 static void tick_disable_protection(void)
84 {
85 /* Set things up so user can access tick register for profiling
86 * purposes. Also workaround BB_ERRATA_1 by doing a dummy
87 * read back of %tick after writing it.
88 */
89 __asm__ __volatile__(
90 " ba,pt %%xcc, 1f\n"
91 " nop\n"
92 " .align 64\n"
93 "1: rd %%tick, %%g2\n"
94 " add %%g2, 6, %%g2\n"
95 " andn %%g2, %0, %%g2\n"
96 " wrpr %%g2, 0, %%tick\n"
97 " rdpr %%tick, %%g0"
98 : /* no outputs */
99 : "r" (TICK_PRIV_BIT)
100 : "g2");
101 }
102
103 static void tick_init_tick(unsigned long offset)
104 {
105 tick_disable_protection();
106
107 __asm__ __volatile__(
108 " rd %%tick, %%g1\n"
109 " andn %%g1, %1, %%g1\n"
110 " ba,pt %%xcc, 1f\n"
111 " add %%g1, %0, %%g1\n"
112 " .align 64\n"
113 "1: wr %%g1, 0x0, %%tick_cmpr\n"
114 " rd %%tick_cmpr, %%g0"
115 : /* no outputs */
116 : "r" (offset), "r" (TICK_PRIV_BIT)
117 : "g1");
118 }
119
120 static unsigned long tick_get_tick(void)
121 {
122 unsigned long ret;
123
124 __asm__ __volatile__("rd %%tick, %0\n\t"
125 "mov %0, %0"
126 : "=r" (ret));
127
128 return ret & ~TICK_PRIV_BIT;
129 }
130
131 static unsigned long tick_get_compare(void)
132 {
133 unsigned long ret;
134
135 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
136 "mov %0, %0"
137 : "=r" (ret));
138
139 return ret;
140 }
141
142 static unsigned long tick_add_compare(unsigned long adj)
143 {
144 unsigned long new_compare;
145
146 /* Workaround for Spitfire Errata (#54 I think??), I discovered
147 * this via Sun BugID 4008234, mentioned in Solaris-2.5.1 patch
148 * number 103640.
149 *
150 * On Blackbird writes to %tick_cmpr can fail, the
151 * workaround seems to be to execute the wr instruction
152 * at the start of an I-cache line, and perform a dummy
153 * read back from %tick_cmpr right after writing to it. -DaveM
154 */
155 __asm__ __volatile__("rd %%tick_cmpr, %0\n\t"
156 "ba,pt %%xcc, 1f\n\t"
157 " add %0, %1, %0\n\t"
158 ".align 64\n"
159 "1:\n\t"
160 "wr %0, 0, %%tick_cmpr\n\t"
161 "rd %%tick_cmpr, %%g0"
162 : "=&r" (new_compare)
163 : "r" (adj));
164
165 return new_compare;
166 }
167
168 static unsigned long tick_add_tick(unsigned long adj, unsigned long offset)
169 {
170 unsigned long new_tick, tmp;
171
172 /* Also need to handle Blackbird bug here too. */
173 __asm__ __volatile__("rd %%tick, %0\n\t"
174 "add %0, %2, %0\n\t"
175 "wrpr %0, 0, %%tick\n\t"
176 "andn %0, %4, %1\n\t"
177 "ba,pt %%xcc, 1f\n\t"
178 " add %1, %3, %1\n\t"
179 ".align 64\n"
180 "1:\n\t"
181 "wr %1, 0, %%tick_cmpr\n\t"
182 "rd %%tick_cmpr, %%g0"
183 : "=&r" (new_tick), "=&r" (tmp)
184 : "r" (adj), "r" (offset), "r" (TICK_PRIV_BIT));
185
186 return new_tick;
187 }
188
189 static struct sparc64_tick_ops tick_operations = {
190 .init_tick = tick_init_tick,
191 .get_tick = tick_get_tick,
192 .get_compare = tick_get_compare,
193 .add_tick = tick_add_tick,
194 .add_compare = tick_add_compare,
195 .softint_mask = 1UL << 0,
196 };
197
198 static void stick_init_tick(unsigned long offset)
199 {
200 tick_disable_protection();
201
202 /* Let the user get at STICK too. */
203 __asm__ __volatile__(
204 " rd %%asr24, %%g2\n"
205 " andn %%g2, %0, %%g2\n"
206 " wr %%g2, 0, %%asr24"
207 : /* no outputs */
208 : "r" (TICK_PRIV_BIT)
209 : "g1", "g2");
210
211 __asm__ __volatile__(
212 " rd %%asr24, %%g1\n"
213 " andn %%g1, %1, %%g1\n"
214 " add %%g1, %0, %%g1\n"
215 " wr %%g1, 0x0, %%asr25"
216 : /* no outputs */
217 : "r" (offset), "r" (TICK_PRIV_BIT)
218 : "g1");
219 }
220
221 static unsigned long stick_get_tick(void)
222 {
223 unsigned long ret;
224
225 __asm__ __volatile__("rd %%asr24, %0"
226 : "=r" (ret));
227
228 return ret & ~TICK_PRIV_BIT;
229 }
230
231 static unsigned long stick_get_compare(void)
232 {
233 unsigned long ret;
234
235 __asm__ __volatile__("rd %%asr25, %0"
236 : "=r" (ret));
237
238 return ret;
239 }
240
241 static unsigned long stick_add_tick(unsigned long adj, unsigned long offset)
242 {
243 unsigned long new_tick, tmp;
244
245 __asm__ __volatile__("rd %%asr24, %0\n\t"
246 "add %0, %2, %0\n\t"
247 "wr %0, 0, %%asr24\n\t"
248 "andn %0, %4, %1\n\t"
249 "add %1, %3, %1\n\t"
250 "wr %1, 0, %%asr25"
251 : "=&r" (new_tick), "=&r" (tmp)
252 : "r" (adj), "r" (offset), "r" (TICK_PRIV_BIT));
253
254 return new_tick;
255 }
256
257 static unsigned long stick_add_compare(unsigned long adj)
258 {
259 unsigned long new_compare;
260
261 __asm__ __volatile__("rd %%asr25, %0\n\t"
262 "add %0, %1, %0\n\t"
263 "wr %0, 0, %%asr25"
264 : "=&r" (new_compare)
265 : "r" (adj));
266
267 return new_compare;
268 }
269
270 static struct sparc64_tick_ops stick_operations = {
271 .init_tick = stick_init_tick,
272 .get_tick = stick_get_tick,
273 .get_compare = stick_get_compare,
274 .add_tick = stick_add_tick,
275 .add_compare = stick_add_compare,
276 .softint_mask = 1UL << 16,
277 };
278
279 /* On Hummingbird the STICK/STICK_CMPR register is implemented
280 * in I/O space. There are two 64-bit registers each, the
281 * first holds the low 32-bits of the value and the second holds
282 * the high 32-bits.
283 *
284 * Since STICK is constantly updating, we have to access it carefully.
285 *
286 * The sequence we use to read is:
287 * 1) read low
288 * 2) read high
289 * 3) read low again, if it rolled over increment high by 1
290 *
291 * Writing STICK safely is also tricky:
292 * 1) write low to zero
293 * 2) write high
294 * 3) write low
295 */
296 #define HBIRD_STICKCMP_ADDR 0x1fe0000f060UL
297 #define HBIRD_STICK_ADDR 0x1fe0000f070UL
298
299 static unsigned long __hbird_read_stick(void)
300 {
301 unsigned long ret, tmp1, tmp2, tmp3;
302 unsigned long addr = HBIRD_STICK_ADDR;
303
304 __asm__ __volatile__("ldxa [%1] %5, %2\n\t"
305 "add %1, 0x8, %1\n\t"
306 "ldxa [%1] %5, %3\n\t"
307 "sub %1, 0x8, %1\n\t"
308 "ldxa [%1] %5, %4\n\t"
309 "cmp %4, %2\n\t"
310 "blu,a,pn %%xcc, 1f\n\t"
311 " add %3, 1, %3\n"
312 "1:\n\t"
313 "sllx %3, 32, %3\n\t"
314 "or %3, %4, %0\n\t"
315 : "=&r" (ret), "=&r" (addr),
316 "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3)
317 : "i" (ASI_PHYS_BYPASS_EC_E), "1" (addr));
318
319 return ret;
320 }
321
322 static unsigned long __hbird_read_compare(void)
323 {
324 unsigned long low, high;
325 unsigned long addr = HBIRD_STICKCMP_ADDR;
326
327 __asm__ __volatile__("ldxa [%2] %3, %0\n\t"
328 "add %2, 0x8, %2\n\t"
329 "ldxa [%2] %3, %1"
330 : "=&r" (low), "=&r" (high), "=&r" (addr)
331 : "i" (ASI_PHYS_BYPASS_EC_E), "2" (addr));
332
333 return (high << 32UL) | low;
334 }
335
336 static void __hbird_write_stick(unsigned long val)
337 {
338 unsigned long low = (val & 0xffffffffUL);
339 unsigned long high = (val >> 32UL);
340 unsigned long addr = HBIRD_STICK_ADDR;
341
342 __asm__ __volatile__("stxa %%g0, [%0] %4\n\t"
343 "add %0, 0x8, %0\n\t"
344 "stxa %3, [%0] %4\n\t"
345 "sub %0, 0x8, %0\n\t"
346 "stxa %2, [%0] %4"
347 : "=&r" (addr)
348 : "0" (addr), "r" (low), "r" (high),
349 "i" (ASI_PHYS_BYPASS_EC_E));
350 }
351
352 static void __hbird_write_compare(unsigned long val)
353 {
354 unsigned long low = (val & 0xffffffffUL);
355 unsigned long high = (val >> 32UL);
356 unsigned long addr = HBIRD_STICKCMP_ADDR + 0x8UL;
357
358 __asm__ __volatile__("stxa %3, [%0] %4\n\t"
359 "sub %0, 0x8, %0\n\t"
360 "stxa %2, [%0] %4"
361 : "=&r" (addr)
362 : "0" (addr), "r" (low), "r" (high),
363 "i" (ASI_PHYS_BYPASS_EC_E));
364 }
365
366 static void hbtick_init_tick(unsigned long offset)
367 {
368 unsigned long val;
369
370 tick_disable_protection();
371
372 /* XXX This seems to be necessary to 'jumpstart' Hummingbird
373 * XXX into actually sending STICK interrupts. I think because
374 * XXX of how we store %tick_cmpr in head.S this somehow resets the
375 * XXX {TICK + STICK} interrupt mux. -DaveM
376 */
377 __hbird_write_stick(__hbird_read_stick());
378
379 val = __hbird_read_stick() & ~TICK_PRIV_BIT;
380 __hbird_write_compare(val + offset);
381 }
382
383 static unsigned long hbtick_get_tick(void)
384 {
385 return __hbird_read_stick() & ~TICK_PRIV_BIT;
386 }
387
388 static unsigned long hbtick_get_compare(void)
389 {
390 return __hbird_read_compare();
391 }
392
393 static unsigned long hbtick_add_tick(unsigned long adj, unsigned long offset)
394 {
395 unsigned long val;
396
397 val = __hbird_read_stick() + adj;
398 __hbird_write_stick(val);
399
400 val &= ~TICK_PRIV_BIT;
401 __hbird_write_compare(val + offset);
402
403 return val;
404 }
405
406 static unsigned long hbtick_add_compare(unsigned long adj)
407 {
408 unsigned long val = __hbird_read_compare() + adj;
409
410 val &= ~TICK_PRIV_BIT;
411 __hbird_write_compare(val);
412
413 return val;
414 }
415
416 static struct sparc64_tick_ops hbtick_operations = {
417 .init_tick = hbtick_init_tick,
418 .get_tick = hbtick_get_tick,
419 .get_compare = hbtick_get_compare,
420 .add_tick = hbtick_add_tick,
421 .add_compare = hbtick_add_compare,
422 .softint_mask = 1UL << 0,
423 };
424
425 /* timer_interrupt() needs to keep up the real-time clock,
426 * as well as call the "do_timer()" routine every clocktick
427 *
428 * NOTE: On SUN5 systems the ticker interrupt comes in using 2
429 * interrupts, one at level14 and one with softint bit 0.
430 */
431 unsigned long timer_tick_offset;
432 unsigned long timer_tick_compare;
433
434 static unsigned long timer_ticks_per_nsec_quotient;
435
436 #define TICK_SIZE (tick_nsec / 1000)
437
438 static inline void timer_check_rtc(void)
439 {
440 /* last time the cmos clock got updated */
441 static long last_rtc_update;
442
443 /* Determine when to update the Mostek clock. */
444 if ((time_status & STA_UNSYNC) == 0 &&
445 xtime.tv_sec > last_rtc_update + 660 &&
446 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
447 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
448 if (set_rtc_mmss(xtime.tv_sec) == 0)
449 last_rtc_update = xtime.tv_sec;
450 else
451 last_rtc_update = xtime.tv_sec - 600;
452 /* do it again in 60 s */
453 }
454 }
455
456 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs * regs)
457 {
458 unsigned long ticks, pstate;
459
460 write_seqlock(&xtime_lock);
461
462 do {
463 #ifndef CONFIG_SMP
464 profile_tick(CPU_PROFILING, regs);
465 #endif
466 do_timer(regs);
467
468 /* Guarantee that the following sequences execute
469 * uninterrupted.
470 */
471 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
472 "wrpr %0, %1, %%pstate"
473 : "=r" (pstate)
474 : "i" (PSTATE_IE));
475
476 timer_tick_compare = tick_ops->add_compare(timer_tick_offset);
477 ticks = tick_ops->get_tick();
478
479 /* Restore PSTATE_IE. */
480 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
481 : /* no outputs */
482 : "r" (pstate));
483 } while (time_after_eq(ticks, timer_tick_compare));
484
485 timer_check_rtc();
486
487 write_sequnlock(&xtime_lock);
488
489 return IRQ_HANDLED;
490 }
491
492 #ifdef CONFIG_SMP
493 void timer_tick_interrupt(struct pt_regs *regs)
494 {
495 write_seqlock(&xtime_lock);
496
497 do_timer(regs);
498
499 /*
500 * Only keep timer_tick_offset uptodate, but don't set TICK_CMPR.
501 */
502 timer_tick_compare = tick_ops->get_compare() + timer_tick_offset;
503
504 timer_check_rtc();
505
506 write_sequnlock(&xtime_lock);
507 }
508 #endif
509
510 /* Kick start a stopped clock (procedure from the Sun NVRAM/hostid FAQ). */
511 static void __init kick_start_clock(void)
512 {
513 unsigned long regs = mstk48t02_regs;
514 u8 sec, tmp;
515 int i, count;
516
517 prom_printf("CLOCK: Clock was stopped. Kick start ");
518
519 spin_lock_irq(&mostek_lock);
520
521 /* Turn on the kick start bit to start the oscillator. */
522 tmp = mostek_read(regs + MOSTEK_CREG);
523 tmp |= MSTK_CREG_WRITE;
524 mostek_write(regs + MOSTEK_CREG, tmp);
525 tmp = mostek_read(regs + MOSTEK_SEC);
526 tmp &= ~MSTK_STOP;
527 mostek_write(regs + MOSTEK_SEC, tmp);
528 tmp = mostek_read(regs + MOSTEK_HOUR);
529 tmp |= MSTK_KICK_START;
530 mostek_write(regs + MOSTEK_HOUR, tmp);
531 tmp = mostek_read(regs + MOSTEK_CREG);
532 tmp &= ~MSTK_CREG_WRITE;
533 mostek_write(regs + MOSTEK_CREG, tmp);
534
535 spin_unlock_irq(&mostek_lock);
536
537 /* Delay to allow the clock oscillator to start. */
538 sec = MSTK_REG_SEC(regs);
539 for (i = 0; i < 3; i++) {
540 while (sec == MSTK_REG_SEC(regs))
541 for (count = 0; count < 100000; count++)
542 /* nothing */ ;
543 prom_printf(".");
544 sec = MSTK_REG_SEC(regs);
545 }
546 prom_printf("\n");
547
548 spin_lock_irq(&mostek_lock);
549
550 /* Turn off kick start and set a "valid" time and date. */
551 tmp = mostek_read(regs + MOSTEK_CREG);
552 tmp |= MSTK_CREG_WRITE;
553 mostek_write(regs + MOSTEK_CREG, tmp);
554 tmp = mostek_read(regs + MOSTEK_HOUR);
555 tmp &= ~MSTK_KICK_START;
556 mostek_write(regs + MOSTEK_HOUR, tmp);
557 MSTK_SET_REG_SEC(regs,0);
558 MSTK_SET_REG_MIN(regs,0);
559 MSTK_SET_REG_HOUR(regs,0);
560 MSTK_SET_REG_DOW(regs,5);
561 MSTK_SET_REG_DOM(regs,1);
562 MSTK_SET_REG_MONTH(regs,8);
563 MSTK_SET_REG_YEAR(regs,1996 - MSTK_YEAR_ZERO);
564 tmp = mostek_read(regs + MOSTEK_CREG);
565 tmp &= ~MSTK_CREG_WRITE;
566 mostek_write(regs + MOSTEK_CREG, tmp);
567
568 spin_unlock_irq(&mostek_lock);
569
570 /* Ensure the kick start bit is off. If it isn't, turn it off. */
571 while (mostek_read(regs + MOSTEK_HOUR) & MSTK_KICK_START) {
572 prom_printf("CLOCK: Kick start still on!\n");
573
574 spin_lock_irq(&mostek_lock);
575
576 tmp = mostek_read(regs + MOSTEK_CREG);
577 tmp |= MSTK_CREG_WRITE;
578 mostek_write(regs + MOSTEK_CREG, tmp);
579
580 tmp = mostek_read(regs + MOSTEK_HOUR);
581 tmp &= ~MSTK_KICK_START;
582 mostek_write(regs + MOSTEK_HOUR, tmp);
583
584 tmp = mostek_read(regs + MOSTEK_CREG);
585 tmp &= ~MSTK_CREG_WRITE;
586 mostek_write(regs + MOSTEK_CREG, tmp);
587
588 spin_unlock_irq(&mostek_lock);
589 }
590
591 prom_printf("CLOCK: Kick start procedure successful.\n");
592 }
593
594 /* Return nonzero if the clock chip battery is low. */
595 static int __init has_low_battery(void)
596 {
597 unsigned long regs = mstk48t02_regs;
598 u8 data1, data2;
599
600 spin_lock_irq(&mostek_lock);
601
602 data1 = mostek_read(regs + MOSTEK_EEPROM); /* Read some data. */
603 mostek_write(regs + MOSTEK_EEPROM, ~data1); /* Write back the complement. */
604 data2 = mostek_read(regs + MOSTEK_EEPROM); /* Read back the complement. */
605 mostek_write(regs + MOSTEK_EEPROM, data1); /* Restore original value. */
606
607 spin_unlock_irq(&mostek_lock);
608
609 return (data1 == data2); /* Was the write blocked? */
610 }
611
612 /* Probe for the real time clock chip. */
613 static void __init set_system_time(void)
614 {
615 unsigned int year, mon, day, hour, min, sec;
616 unsigned long mregs = mstk48t02_regs;
617 #ifdef CONFIG_PCI
618 unsigned long dregs = ds1287_regs;
619 #else
620 unsigned long dregs = 0UL;
621 #endif
622 u8 tmp;
623
624 if (!mregs && !dregs) {
625 prom_printf("Something wrong, clock regs not mapped yet.\n");
626 prom_halt();
627 }
628
629 if (mregs) {
630 spin_lock_irq(&mostek_lock);
631
632 /* Traditional Mostek chip. */
633 tmp = mostek_read(mregs + MOSTEK_CREG);
634 tmp |= MSTK_CREG_READ;
635 mostek_write(mregs + MOSTEK_CREG, tmp);
636
637 sec = MSTK_REG_SEC(mregs);
638 min = MSTK_REG_MIN(mregs);
639 hour = MSTK_REG_HOUR(mregs);
640 day = MSTK_REG_DOM(mregs);
641 mon = MSTK_REG_MONTH(mregs);
642 year = MSTK_CVT_YEAR( MSTK_REG_YEAR(mregs) );
643 } else {
644 int i;
645
646 /* Dallas 12887 RTC chip. */
647
648 /* Stolen from arch/i386/kernel/time.c, see there for
649 * credits and descriptive comments.
650 */
651 for (i = 0; i < 1000000; i++) {
652 if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
653 break;
654 udelay(10);
655 }
656 for (i = 0; i < 1000000; i++) {
657 if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
658 break;
659 udelay(10);
660 }
661 do {
662 sec = CMOS_READ(RTC_SECONDS);
663 min = CMOS_READ(RTC_MINUTES);
664 hour = CMOS_READ(RTC_HOURS);
665 day = CMOS_READ(RTC_DAY_OF_MONTH);
666 mon = CMOS_READ(RTC_MONTH);
667 year = CMOS_READ(RTC_YEAR);
668 } while (sec != CMOS_READ(RTC_SECONDS));
669 if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
670 BCD_TO_BIN(sec);
671 BCD_TO_BIN(min);
672 BCD_TO_BIN(hour);
673 BCD_TO_BIN(day);
674 BCD_TO_BIN(mon);
675 BCD_TO_BIN(year);
676 }
677 if ((year += 1900) < 1970)
678 year += 100;
679 }
680
681 xtime.tv_sec = mktime(year, mon, day, hour, min, sec);
682 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
683 set_normalized_timespec(&wall_to_monotonic,
684 -xtime.tv_sec, -xtime.tv_nsec);
685
686 if (mregs) {
687 tmp = mostek_read(mregs + MOSTEK_CREG);
688 tmp &= ~MSTK_CREG_READ;
689 mostek_write(mregs + MOSTEK_CREG, tmp);
690
691 spin_unlock_irq(&mostek_lock);
692 }
693 }
694
695 void __init clock_probe(void)
696 {
697 struct linux_prom_registers clk_reg[2];
698 char model[128];
699 int node, busnd = -1, err;
700 unsigned long flags;
701 struct linux_central *cbus;
702 #ifdef CONFIG_PCI
703 struct linux_ebus *ebus = NULL;
704 struct sparc_isa_bridge *isa_br = NULL;
705 #endif
706 static int invoked;
707
708 if (invoked)
709 return;
710 invoked = 1;
711
712
713 if (this_is_starfire) {
714 /* davem suggests we keep this within the 4M locked kernel image */
715 static char obp_gettod[256];
716 static u32 unix_tod;
717
718 sprintf(obp_gettod, "h# %08x unix-gettod",
719 (unsigned int) (long) &unix_tod);
720 prom_feval(obp_gettod);
721 xtime.tv_sec = unix_tod;
722 xtime.tv_nsec = (INITIAL_JIFFIES % HZ) * (NSEC_PER_SEC / HZ);
723 set_normalized_timespec(&wall_to_monotonic,
724 -xtime.tv_sec, -xtime.tv_nsec);
725 return;
726 }
727
728 local_irq_save(flags);
729
730 cbus = central_bus;
731 if (cbus != NULL)
732 busnd = central_bus->child->prom_node;
733
734 /* Check FHC Central then EBUSs then ISA bridges then SBUSs.
735 * That way we handle the presence of multiple properly.
736 *
737 * As a special case, machines with Central must provide the
738 * timer chip there.
739 */
740 #ifdef CONFIG_PCI
741 if (ebus_chain != NULL) {
742 ebus = ebus_chain;
743 if (busnd == -1)
744 busnd = ebus->prom_node;
745 }
746 if (isa_chain != NULL) {
747 isa_br = isa_chain;
748 if (busnd == -1)
749 busnd = isa_br->prom_node;
750 }
751 #endif
752 if (sbus_root != NULL && busnd == -1)
753 busnd = sbus_root->prom_node;
754
755 if (busnd == -1) {
756 prom_printf("clock_probe: problem, cannot find bus to search.\n");
757 prom_halt();
758 }
759
760 node = prom_getchild(busnd);
761
762 while (1) {
763 if (!node)
764 model[0] = 0;
765 else
766 prom_getstring(node, "model", model, sizeof(model));
767 if (strcmp(model, "mk48t02") &&
768 strcmp(model, "mk48t08") &&
769 strcmp(model, "mk48t59") &&
770 strcmp(model, "m5819") &&
771 strcmp(model, "m5819p") &&
772 strcmp(model, "ds1287")) {
773 if (cbus != NULL) {
774 prom_printf("clock_probe: Central bus lacks timer chip.\n");
775 prom_halt();
776 }
777
778 if (node != 0)
779 node = prom_getsibling(node);
780 #ifdef CONFIG_PCI
781 while ((node == 0) && ebus != NULL) {
782 ebus = ebus->next;
783 if (ebus != NULL) {
784 busnd = ebus->prom_node;
785 node = prom_getchild(busnd);
786 }
787 }
788 while ((node == 0) && isa_br != NULL) {
789 isa_br = isa_br->next;
790 if (isa_br != NULL) {
791 busnd = isa_br->prom_node;
792 node = prom_getchild(busnd);
793 }
794 }
795 #endif
796 if (node == 0) {
797 prom_printf("clock_probe: Cannot find timer chip\n");
798 prom_halt();
799 }
800 continue;
801 }
802
803 err = prom_getproperty(node, "reg", (char *)clk_reg,
804 sizeof(clk_reg));
805 if(err == -1) {
806 prom_printf("clock_probe: Cannot get Mostek reg property\n");
807 prom_halt();
808 }
809
810 if (cbus != NULL) {
811 apply_fhc_ranges(central_bus->child, clk_reg, 1);
812 apply_central_ranges(central_bus, clk_reg, 1);
813 }
814 #ifdef CONFIG_PCI
815 else if (ebus != NULL) {
816 struct linux_ebus_device *edev;
817
818 for_each_ebusdev(edev, ebus)
819 if (edev->prom_node == node)
820 break;
821 if (edev == NULL) {
822 if (isa_chain != NULL)
823 goto try_isa_clock;
824 prom_printf("%s: Mostek not probed by EBUS\n",
825 __FUNCTION__);
826 prom_halt();
827 }
828
829 if (!strcmp(model, "ds1287") ||
830 !strcmp(model, "m5819") ||
831 !strcmp(model, "m5819p")) {
832 ds1287_regs = edev->resource[0].start;
833 } else {
834 mstk48t59_regs = edev->resource[0].start;
835 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
836 }
837 break;
838 }
839 else if (isa_br != NULL) {
840 struct sparc_isa_device *isadev;
841
842 try_isa_clock:
843 for_each_isadev(isadev, isa_br)
844 if (isadev->prom_node == node)
845 break;
846 if (isadev == NULL) {
847 prom_printf("%s: Mostek not probed by ISA\n");
848 prom_halt();
849 }
850 if (!strcmp(model, "ds1287") ||
851 !strcmp(model, "m5819") ||
852 !strcmp(model, "m5819p")) {
853 ds1287_regs = isadev->resource.start;
854 } else {
855 mstk48t59_regs = isadev->resource.start;
856 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
857 }
858 break;
859 }
860 #endif
861 else {
862 if (sbus_root->num_sbus_ranges) {
863 int nranges = sbus_root->num_sbus_ranges;
864 int rngc;
865
866 for (rngc = 0; rngc < nranges; rngc++)
867 if (clk_reg[0].which_io ==
868 sbus_root->sbus_ranges[rngc].ot_child_space)
869 break;
870 if (rngc == nranges) {
871 prom_printf("clock_probe: Cannot find ranges for "
872 "clock regs.\n");
873 prom_halt();
874 }
875 clk_reg[0].which_io =
876 sbus_root->sbus_ranges[rngc].ot_parent_space;
877 clk_reg[0].phys_addr +=
878 sbus_root->sbus_ranges[rngc].ot_parent_base;
879 }
880 }
881
882 if(model[5] == '0' && model[6] == '2') {
883 mstk48t02_regs = (((u64)clk_reg[0].phys_addr) |
884 (((u64)clk_reg[0].which_io)<<32UL));
885 } else if(model[5] == '0' && model[6] == '8') {
886 mstk48t08_regs = (((u64)clk_reg[0].phys_addr) |
887 (((u64)clk_reg[0].which_io)<<32UL));
888 mstk48t02_regs = mstk48t08_regs + MOSTEK_48T08_48T02;
889 } else {
890 mstk48t59_regs = (((u64)clk_reg[0].phys_addr) |
891 (((u64)clk_reg[0].which_io)<<32UL));
892 mstk48t02_regs = mstk48t59_regs + MOSTEK_48T59_48T02;
893 }
894 break;
895 }
896
897 if (mstk48t02_regs != 0UL) {
898 /* Report a low battery voltage condition. */
899 if (has_low_battery())
900 prom_printf("NVRAM: Low battery voltage!\n");
901
902 /* Kick start the clock if it is completely stopped. */
903 if (mostek_read(mstk48t02_regs + MOSTEK_SEC) & MSTK_STOP)
904 kick_start_clock();
905 }
906
907 set_system_time();
908
909 local_irq_restore(flags);
910 }
911
912 /* This is gets the master TICK_INT timer going. */
913 static unsigned long sparc64_init_timers(void)
914 {
915 unsigned long clock;
916 int node;
917 #ifdef CONFIG_SMP
918 extern void smp_tick_init(void);
919 #endif
920
921 if (tlb_type == spitfire) {
922 unsigned long ver, manuf, impl;
923
924 __asm__ __volatile__ ("rdpr %%ver, %0"
925 : "=&r" (ver));
926 manuf = ((ver >> 48) & 0xffff);
927 impl = ((ver >> 32) & 0xffff);
928 if (manuf == 0x17 && impl == 0x13) {
929 /* Hummingbird, aka Ultra-IIe */
930 tick_ops = &hbtick_operations;
931 node = prom_root_node;
932 clock = prom_getint(node, "stick-frequency");
933 } else {
934 tick_ops = &tick_operations;
935 cpu_find_by_instance(0, &node, NULL);
936 clock = prom_getint(node, "clock-frequency");
937 }
938 } else {
939 tick_ops = &stick_operations;
940 node = prom_root_node;
941 clock = prom_getint(node, "stick-frequency");
942 }
943 timer_tick_offset = clock / HZ;
944
945 #ifdef CONFIG_SMP
946 smp_tick_init();
947 #endif
948
949 return clock;
950 }
951
952 static void sparc64_start_timers(irqreturn_t (*cfunc)(int, void *, struct pt_regs *))
953 {
954 unsigned long pstate;
955 int err;
956
957 /* Register IRQ handler. */
958 err = request_irq(build_irq(0, 0, 0UL, 0UL), cfunc, SA_STATIC_ALLOC,
959 "timer", NULL);
960
961 if (err) {
962 prom_printf("Serious problem, cannot register TICK_INT\n");
963 prom_halt();
964 }
965
966 /* Guarantee that the following sequences execute
967 * uninterrupted.
968 */
969 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
970 "wrpr %0, %1, %%pstate"
971 : "=r" (pstate)
972 : "i" (PSTATE_IE));
973
974 tick_ops->init_tick(timer_tick_offset);
975
976 /* Restore PSTATE_IE. */
977 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
978 : /* no outputs */
979 : "r" (pstate));
980
981 local_irq_enable();
982 }
983
984 struct freq_table {
985 unsigned long udelay_val_ref;
986 unsigned long clock_tick_ref;
987 unsigned int ref_freq;
988 };
989 static DEFINE_PER_CPU(struct freq_table, sparc64_freq_table) = { 0, 0, 0 };
990
991 unsigned long sparc64_get_clock_tick(unsigned int cpu)
992 {
993 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
994
995 if (ft->clock_tick_ref)
996 return ft->clock_tick_ref;
997 return cpu_data(cpu).clock_tick;
998 }
999
1000 #ifdef CONFIG_CPU_FREQ
1001
1002 static int sparc64_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
1003 void *data)
1004 {
1005 struct cpufreq_freqs *freq = data;
1006 unsigned int cpu = freq->cpu;
1007 struct freq_table *ft = &per_cpu(sparc64_freq_table, cpu);
1008
1009 if (!ft->ref_freq) {
1010 ft->ref_freq = freq->old;
1011 ft->udelay_val_ref = cpu_data(cpu).udelay_val;
1012 ft->clock_tick_ref = cpu_data(cpu).clock_tick;
1013 }
1014 if ((val == CPUFREQ_PRECHANGE && freq->old < freq->new) ||
1015 (val == CPUFREQ_POSTCHANGE && freq->old > freq->new) ||
1016 (val == CPUFREQ_RESUMECHANGE)) {
1017 cpu_data(cpu).udelay_val =
1018 cpufreq_scale(ft->udelay_val_ref,
1019 ft->ref_freq,
1020 freq->new);
1021 cpu_data(cpu).clock_tick =
1022 cpufreq_scale(ft->clock_tick_ref,
1023 ft->ref_freq,
1024 freq->new);
1025 }
1026
1027 return 0;
1028 }
1029
1030 static struct notifier_block sparc64_cpufreq_notifier_block = {
1031 .notifier_call = sparc64_cpufreq_notifier
1032 };
1033
1034 #endif /* CONFIG_CPU_FREQ */
1035
1036 static struct time_interpolator sparc64_cpu_interpolator = {
1037 .source = TIME_SOURCE_CPU,
1038 .shift = 16,
1039 };
1040
1041 /* The quotient formula is taken from the IA64 port. */
1042 #define SPARC64_NSEC_PER_CYC_SHIFT 30UL
1043 void __init time_init(void)
1044 {
1045 unsigned long clock = sparc64_init_timers();
1046
1047 sparc64_cpu_interpolator.frequency = clock;
1048 register_time_interpolator(&sparc64_cpu_interpolator);
1049
1050 /* Now that the interpolator is registered, it is
1051 * safe to start the timer ticking.
1052 */
1053 sparc64_start_timers(timer_interrupt);
1054
1055 timer_ticks_per_nsec_quotient =
1056 (((NSEC_PER_SEC << SPARC64_NSEC_PER_CYC_SHIFT) +
1057 (clock / 2)) / clock);
1058
1059 #ifdef CONFIG_CPU_FREQ
1060 cpufreq_register_notifier(&sparc64_cpufreq_notifier_block,
1061 CPUFREQ_TRANSITION_NOTIFIER);
1062 #endif
1063 }
1064
1065 unsigned long long sched_clock(void)
1066 {
1067 unsigned long ticks = tick_ops->get_tick();
1068
1069 return (ticks * timer_ticks_per_nsec_quotient)
1070 >> SPARC64_NSEC_PER_CYC_SHIFT;
1071 }
1072
1073 static int set_rtc_mmss(unsigned long nowtime)
1074 {
1075 int real_seconds, real_minutes, chip_minutes;
1076 unsigned long mregs = mstk48t02_regs;
1077 #ifdef CONFIG_PCI
1078 unsigned long dregs = ds1287_regs;
1079 #else
1080 unsigned long dregs = 0UL;
1081 #endif
1082 unsigned long flags;
1083 u8 tmp;
1084
1085 /*
1086 * Not having a register set can lead to trouble.
1087 * Also starfire doesn't have a tod clock.
1088 */
1089 if (!mregs && !dregs)
1090 return -1;
1091
1092 if (mregs) {
1093 spin_lock_irqsave(&mostek_lock, flags);
1094
1095 /* Read the current RTC minutes. */
1096 tmp = mostek_read(mregs + MOSTEK_CREG);
1097 tmp |= MSTK_CREG_READ;
1098 mostek_write(mregs + MOSTEK_CREG, tmp);
1099
1100 chip_minutes = MSTK_REG_MIN(mregs);
1101
1102 tmp = mostek_read(mregs + MOSTEK_CREG);
1103 tmp &= ~MSTK_CREG_READ;
1104 mostek_write(mregs + MOSTEK_CREG, tmp);
1105
1106 /*
1107 * since we're only adjusting minutes and seconds,
1108 * don't interfere with hour overflow. This avoids
1109 * messing with unknown time zones but requires your
1110 * RTC not to be off by more than 15 minutes
1111 */
1112 real_seconds = nowtime % 60;
1113 real_minutes = nowtime / 60;
1114 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1115 real_minutes += 30; /* correct for half hour time zone */
1116 real_minutes %= 60;
1117
1118 if (abs(real_minutes - chip_minutes) < 30) {
1119 tmp = mostek_read(mregs + MOSTEK_CREG);
1120 tmp |= MSTK_CREG_WRITE;
1121 mostek_write(mregs + MOSTEK_CREG, tmp);
1122
1123 MSTK_SET_REG_SEC(mregs,real_seconds);
1124 MSTK_SET_REG_MIN(mregs,real_minutes);
1125
1126 tmp = mostek_read(mregs + MOSTEK_CREG);
1127 tmp &= ~MSTK_CREG_WRITE;
1128 mostek_write(mregs + MOSTEK_CREG, tmp);
1129
1130 spin_unlock_irqrestore(&mostek_lock, flags);
1131
1132 return 0;
1133 } else {
1134 spin_unlock_irqrestore(&mostek_lock, flags);
1135
1136 return -1;
1137 }
1138 } else {
1139 int retval = 0;
1140 unsigned char save_control, save_freq_select;
1141
1142 /* Stolen from arch/i386/kernel/time.c, see there for
1143 * credits and descriptive comments.
1144 */
1145 spin_lock_irqsave(&rtc_lock, flags);
1146 save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
1147 CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
1148
1149 save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
1150 CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
1151
1152 chip_minutes = CMOS_READ(RTC_MINUTES);
1153 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
1154 BCD_TO_BIN(chip_minutes);
1155 real_seconds = nowtime % 60;
1156 real_minutes = nowtime / 60;
1157 if (((abs(real_minutes - chip_minutes) + 15)/30) & 1)
1158 real_minutes += 30;
1159 real_minutes %= 60;
1160
1161 if (abs(real_minutes - chip_minutes) < 30) {
1162 if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
1163 BIN_TO_BCD(real_seconds);
1164 BIN_TO_BCD(real_minutes);
1165 }
1166 CMOS_WRITE(real_seconds,RTC_SECONDS);
1167 CMOS_WRITE(real_minutes,RTC_MINUTES);
1168 } else {
1169 printk(KERN_WARNING
1170 "set_rtc_mmss: can't update from %d to %d\n",
1171 chip_minutes, real_minutes);
1172 retval = -1;
1173 }
1174
1175 CMOS_WRITE(save_control, RTC_CONTROL);
1176 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1177 spin_unlock_irqrestore(&rtc_lock, flags);
1178
1179 return retval;
1180 }
1181 }
MOXA 2.6.9 from sdlinux-moxaart.tgz