2 * arch/ppc64/kernel/head.S
5 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
8 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Adapted for Power Macintosh by Paul Mackerras.
10 * Low-level exception handlers and MMU support
11 * rewritten by Paul Mackerras.
12 * Copyright (C) 1996 Paul Mackerras.
14 * Adapted for 64bit PowerPC by Dave Engebretsen, Peter Bergner, and
15 * Mike Corrigan {engebret|bergner|mikejc}@us.ibm.com
17 * This file contains the low-level support and setup for the
18 * PowerPC-64 platform, including trap and interrupt dispatch.
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License
22 * as published by the Free Software Foundation; either version
23 * 2 of the License, or (at your option) any later version.
26 #define SECONDARY_PROCESSORS
28 #include <linux/config.h>
29 #include <asm/processor.h>
33 #include <asm/systemcfg.h>
34 #include <asm/ppc_asm.h>
35 #include <asm/offsets.h>
37 #include <asm/cputable.h>
38 #include <asm/setup.h>
40 #ifdef CONFIG_PPC_ISERIES
41 #define DO_SOFT_DISABLE
45 * hcall interface to pSeries LPAR
47 #define HVSC .long 0x44000022
48 #define H_SET_ASR 0x30
51 * We layout physical memory as follows:
52 * 0x0000 - 0x00ff : Secondary processor spin code
53 * 0x0100 - 0x2fff : pSeries Interrupt prologs
54 * 0x3000 - 0x3fff : Interrupt support
55 * 0x4000 - 0x4fff : NACA
56 * 0x5000 - 0x5fff : SystemCfg
57 * 0x6000 : iSeries and common interrupt prologs
58 * 0x9000 - 0x9fff : Initial segment table
66 * SPRG0 reserved for hypervisor
67 * SPRG1 temp - used to save gpr
68 * SPRG2 temp - used to save gpr
69 * SPRG3 virt addr of paca
73 * Entering into this code we make the following assumptions:
75 * 1. The MMU is off & open firmware is running in real mode.
76 * 2. The kernel is entered at __start
79 * 1. The MMU is on (as it always is for iSeries)
80 * 2. The kernel is entered at SystemReset_Iseries
86 #ifdef CONFIG_PPC_MULTIPLATFORM
88 /* NOP this out unconditionally */
90 b .__start_initialization_multiplatform
92 #endif /* CONFIG_PPC_MULTIPLATFORM */
94 /* Catch branch to 0 in real mode */
96 #ifdef CONFIG_PPC_ISERIES
98 * At offset 0x20, there is a pointer to iSeries LPAR data.
99 * This is required by the hypervisor
102 .llong hvReleaseData-KERNELBASE
105 * At offset 0x28 and 0x30 are offsets to the msChunks
106 * array (used by the iSeries LPAR debugger to do translation
107 * between physical addresses and absolute addresses) and
108 * to the pidhash table (also used by the debugger)
110 .llong msChunks-KERNELBASE
111 .llong 0 /* pidhash-KERNELBASE SFRXXX */
113 /* Offset 0x38 - Pointer to start of embedded System.map */
114 .globl embedded_sysmap_start
115 embedded_sysmap_start:
117 /* Offset 0x40 - Pointer to end of embedded System.map */
118 .globl embedded_sysmap_end
122 #else /* CONFIG_PPC_ISERIES */
124 /* Secondary processors spin on this value until it goes to 1. */
125 .globl __secondary_hold_spinloop
126 __secondary_hold_spinloop:
129 /* Secondary processors write this value with their cpu # */
130 /* after they enter the spin loop immediately below. */
131 .globl __secondary_hold_acknowledge
132 __secondary_hold_acknowledge:
137 * The following code is used on pSeries to hold secondary processors
138 * in a spin loop after they have been freed from OpenFirmware, but
139 * before the bulk of the kernel has been relocated. This code
140 * is relocated to physical address 0x60 before prom_init is run.
141 * All of it must fit below the first exception vector at 0x100.
143 _GLOBAL(__secondary_hold)
146 mtmsrd r24 /* RI on */
148 /* Grab our linux cpu number */
151 /* Tell the master cpu we're here */
152 /* Relocation is off & we are located at an address less */
153 /* than 0x100, so only need to grab low order offset. */
154 std r24,__secondary_hold_acknowledge@l(0)
157 /* All secondary cpu's wait here until told to start. */
158 100: ld r4,__secondary_hold_spinloop@l(0)
167 b .pseries_secondary_smp_init
174 /* This value is used to mark exception frames on the stack. */
177 .tc ID_72656773_68657265[TC],0x7265677368657265
181 * The following macros define the code that appears as
182 * the prologue to each of the exception handlers. They
183 * are split into two parts to allow a single kernel binary
184 * to be used for pSeries and iSeries.
185 * LOL. One day... - paulus
189 * We make as much of the exception code common between native
190 * exception handlers (including pSeries LPAR) and iSeries LPAR
191 * implementations as possible.
195 * This is the start of the interrupt handlers for pSeries
196 * This code runs with relocation off.
204 #define EX_R3 40 /* SLB miss saves R3, but not SRR0 */
206 #define EX_LR 48 /* SLB miss saves LR, but not DAR */
210 #define EXCEPTION_PROLOG_PSERIES(area, label) \
211 mfspr r13,SPRG3; /* get paca address into r13 */ \
212 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
213 std r10,area+EX_R10(r13); \
214 std r11,area+EX_R11(r13); \
215 std r12,area+EX_R12(r13); \
217 std r9,area+EX_R13(r13); \
219 clrrdi r12,r13,32; /* get high part of &label */ \
221 mfspr r11,SRR0; /* save SRR0 */ \
222 ori r12,r12,(label)@l; /* virt addr of handler */ \
223 ori r10,r10,MSR_IR|MSR_DR|MSR_RI; \
225 mfspr r12,SRR1; /* and SRR1 */ \
228 b . /* prevent speculative execution */
231 * This is the start of the interrupt handlers for iSeries
232 * This code runs with relocation on.
234 #define EXCEPTION_PROLOG_ISERIES_1(area) \
235 mfspr r13,SPRG3; /* get paca address into r13 */ \
236 std r9,area+EX_R9(r13); /* save r9 - r12 */ \
237 std r10,area+EX_R10(r13); \
238 std r11,area+EX_R11(r13); \
239 std r12,area+EX_R12(r13); \
241 std r9,area+EX_R13(r13); \
244 #define EXCEPTION_PROLOG_ISERIES_2 \
246 ld r11,PACALPPACA+LPPACASRR0(r13); \
247 ld r12,PACALPPACA+LPPACASRR1(r13); \
248 ori r10,r10,MSR_RI; \
252 * The common exception prolog is used for all except a few exceptions
253 * such as a segment miss on a kernel address. We have to be prepared
254 * to take another exception from the point where we first touch the
255 * kernel stack onwards.
257 * On entry r13 points to the paca, r9-r13 are saved in the paca,
258 * r9 contains the saved CR, r11 and r12 contain the saved SRR0 and
259 * SRR1, and relocation is on.
261 #define EXCEPTION_PROLOG_COMMON(n, area) \
262 andi. r10,r12,MSR_PR; /* See if coming from user */ \
263 mr r10,r1; /* Save r1 */ \
264 subi r1,r1,INT_FRAME_SIZE; /* alloc frame on kernel stack */ \
266 ld r1,PACAKSAVE(r13); /* kernel stack to use */ \
267 1: cmpdi cr1,r1,0; /* check if r1 is in userspace */ \
268 bge- cr1,bad_stack; /* abort if it is */ \
269 std r9,_CCR(r1); /* save CR in stackframe */ \
270 std r11,_NIP(r1); /* save SRR0 in stackframe */ \
271 std r12,_MSR(r1); /* save SRR1 in stackframe */ \
272 std r10,0(r1); /* make stack chain pointer */ \
273 std r0,GPR0(r1); /* save r0 in stackframe */ \
274 std r10,GPR1(r1); /* save r1 in stackframe */ \
275 std r2,GPR2(r1); /* save r2 in stackframe */ \
276 SAVE_4GPRS(3, r1); /* save r3 - r6 in stackframe */ \
277 SAVE_2GPRS(7, r1); /* save r7, r8 in stackframe */ \
278 ld r9,area+EX_R9(r13); /* move r9, r10 to stackframe */ \
279 ld r10,area+EX_R10(r13); \
282 ld r9,area+EX_R11(r13); /* move r11 - r13 to stackframe */ \
283 ld r10,area+EX_R12(r13); \
284 ld r11,area+EX_R13(r13); \
288 ld r2,PACATOC(r13); /* get kernel TOC into r2 */ \
289 mflr r9; /* save LR in stackframe */ \
291 mfctr r10; /* save CTR in stackframe */ \
293 mfspr r11,XER; /* save XER in stackframe */ \
296 std r9,_TRAP(r1); /* set trap number */ \
298 ld r11,exception_marker@toc(r2); \
299 std r10,RESULT(r1); /* clear regs->result */ \
300 std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
305 #define STD_EXCEPTION_PSERIES(n, label) \
307 .globl label##_Pseries; \
310 mtspr SPRG1,r13; /* save r13 */ \
311 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, label##_common)
313 #define STD_EXCEPTION_ISERIES(n, label, area) \
314 .globl label##_Iseries; \
317 mtspr SPRG1,r13; /* save r13 */ \
318 EXCEPTION_PROLOG_ISERIES_1(area); \
319 EXCEPTION_PROLOG_ISERIES_2; \
322 #define MASKABLE_EXCEPTION_ISERIES(n, label) \
323 .globl label##_Iseries; \
326 mtspr SPRG1,r13; /* save r13 */ \
327 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN); \
328 lbz r10,PACAPROCENABLED(r13); \
330 beq- label##_Iseries_masked; \
331 EXCEPTION_PROLOG_ISERIES_2; \
334 #ifdef DO_SOFT_DISABLE
335 #define DISABLE_INTS \
336 lbz r10,PACAPROCENABLED(r13); \
340 stb r11,PACAPROCENABLED(r13); \
341 ori r10,r10,MSR_EE; \
344 #define ENABLE_INTS \
345 lbz r10,PACAPROCENABLED(r13); \
348 ori r11,r11,MSR_EE; \
351 #else /* hard enable/disable interrupts */
354 #define ENABLE_INTS \
357 rlwimi r11,r12,0,MSR_EE; \
362 #define STD_EXCEPTION_COMMON(trap, label, hdlr) \
364 .globl label##_common; \
366 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
369 addi r3,r1,STACK_FRAME_OVERHEAD; \
373 #define STD_EXCEPTION_COMMON_LITE(trap, label, hdlr) \
375 .globl label##_common; \
377 EXCEPTION_PROLOG_COMMON(trap, PACA_EXGEN); \
379 addi r3,r1,STACK_FRAME_OVERHEAD; \
381 b .ret_from_except_lite
384 * Start of pSeries system interrupt routines
387 .globl __start_interrupts
390 STD_EXCEPTION_PSERIES(0x100, SystemReset)
393 _MachineCheckPseries:
395 mtspr SPRG1,r13 /* save r13 */
396 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
399 .globl DataAccess_Pseries
408 rlwimi r13,r12,16,0x20
411 beq .do_stab_bolted_Pseries
414 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
415 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, DataAccess_common)
418 .globl DataAccessSLB_Pseries
419 DataAccessSLB_Pseries:
422 mfspr r13,SPRG3 /* get paca address into r13 */
423 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
424 std r10,PACA_EXSLB+EX_R10(r13)
425 std r11,PACA_EXSLB+EX_R11(r13)
426 std r12,PACA_EXSLB+EX_R12(r13)
427 std r3,PACA_EXSLB+EX_R3(r13)
429 std r9,PACA_EXSLB+EX_R13(r13)
431 mfspr r12,SRR1 /* and SRR1 */
433 b .do_slb_miss /* Rel. branch works in real mode */
435 STD_EXCEPTION_PSERIES(0x400, InstructionAccess)
438 .globl InstructionAccessSLB_Pseries
439 InstructionAccessSLB_Pseries:
442 mfspr r13,SPRG3 /* get paca address into r13 */
443 std r9,PACA_EXSLB+EX_R9(r13) /* save r9 - r12 */
444 std r10,PACA_EXSLB+EX_R10(r13)
445 std r11,PACA_EXSLB+EX_R11(r13)
446 std r12,PACA_EXSLB+EX_R12(r13)
447 std r3,PACA_EXSLB+EX_R3(r13)
449 std r9,PACA_EXSLB+EX_R13(r13)
451 mfspr r12,SRR1 /* and SRR1 */
452 mfspr r3,SRR0 /* SRR0 is faulting address */
453 b .do_slb_miss /* Rel. branch works in real mode */
455 STD_EXCEPTION_PSERIES(0x500, HardwareInterrupt)
456 STD_EXCEPTION_PSERIES(0x600, Alignment)
457 STD_EXCEPTION_PSERIES(0x700, ProgramCheck)
458 STD_EXCEPTION_PSERIES(0x800, FPUnavailable)
459 STD_EXCEPTION_PSERIES(0x900, Decrementer)
460 STD_EXCEPTION_PSERIES(0xa00, Trap_0a)
461 STD_EXCEPTION_PSERIES(0xb00, Trap_0b)
464 .globl SystemCall_Pseries
472 oris r12,r12,SystemCall_common@h
473 ori r12,r12,SystemCall_common@l
475 ori r10,r10,MSR_IR|MSR_DR|MSR_RI
479 b . /* prevent speculative execution */
481 STD_EXCEPTION_PSERIES(0xd00, SingleStep)
482 STD_EXCEPTION_PSERIES(0xe00, Trap_0e)
484 /* We need to deal with the Altivec unavailable exception
485 * here which is at 0xf20, thus in the middle of the
486 * prolog code of the PerformanceMonitor one. A little
487 * trickery is thus necessary
490 b PerformanceMonitor_Pseries
492 STD_EXCEPTION_PSERIES(0xf20, AltivecUnavailable)
494 STD_EXCEPTION_PSERIES(0x1300, InstructionBreakpoint)
495 STD_EXCEPTION_PSERIES(0x1700, AltivecAssist)
497 /* moved from 0xf00 */
498 STD_EXCEPTION_PSERIES(0x3000, PerformanceMonitor)
501 _GLOBAL(do_stab_bolted_Pseries)
504 EXCEPTION_PROLOG_PSERIES(PACA_EXSLB, .do_stab_bolted)
507 /* Space for the naca. Architected to be located at real address
508 * NACA_PHYS_ADDR. Various tools rely on this location being fixed.
509 * The first dword of the naca is required by iSeries LPAR to
510 * point to itVpdAreas. On pSeries native, this value is not used.
513 .globl __end_interrupts
517 #ifdef CONFIG_PPC_ISERIES
526 . = SYSTEMCFG_PHYS_ADDR
528 .globl __start_systemcfg
531 . = (SYSTEMCFG_PHYS_ADDR + PAGE_SIZE)
532 .globl __end_systemcfg
535 #ifdef CONFIG_PPC_ISERIES
537 * The iSeries LPAR map is at this fixed address
538 * so that the HvReleaseData structure can address
539 * it with a 32-bit offset.
541 * The VSID values below are dependent on the
542 * VSID generation algorithm. See include/asm/mmu_context.h.
545 .llong 2 /* # ESIDs to be mapped by hypervisor */
546 .llong 1 /* # memory ranges to be mapped by hypervisor */
547 .llong STAB0_PAGE /* Page # of segment table within load area */
548 .llong 0 /* Reserved */
549 .llong 0 /* Reserved */
550 .llong 0 /* Reserved */
551 .llong 0 /* Reserved */
552 .llong 0 /* Reserved */
553 .llong (KERNELBASE>>SID_SHIFT)
554 .llong 0x408f92c94 /* KERNELBASE VSID */
555 /* We have to list the bolted VMALLOC segment here, too, so that it
556 * will be restored on shared processor switch */
557 .llong (VMALLOCBASE>>SID_SHIFT)
558 .llong 0xf09b89af5 /* VMALLOCBASE VSID */
559 .llong 8192 /* # pages to map (32 MB) */
560 .llong 0 /* Offset from start of loadarea to start of map */
561 .llong 0x408f92c940000 /* VPN of first page to map */
565 /*** ISeries-LPAR interrupt handlers ***/
567 STD_EXCEPTION_ISERIES(0x200, MachineCheck, PACA_EXMC)
569 .globl DataAccess_Iseries
577 rlwimi r13,r12,16,0x20
580 beq .do_stab_bolted_Iseries
583 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
584 EXCEPTION_PROLOG_ISERIES_1(PACA_EXGEN)
585 EXCEPTION_PROLOG_ISERIES_2
588 .do_stab_bolted_Iseries:
591 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
592 EXCEPTION_PROLOG_ISERIES_2
595 .globl DataAccessSLB_Iseries
596 DataAccessSLB_Iseries:
597 mtspr SPRG1,r13 /* save r13 */
598 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
599 std r3,PACA_EXSLB+EX_R3(r13)
600 ld r12,PACALPPACA+LPPACASRR1(r13)
604 STD_EXCEPTION_ISERIES(0x400, InstructionAccess, PACA_EXGEN)
606 .globl InstructionAccessSLB_Iseries
607 InstructionAccessSLB_Iseries:
608 mtspr SPRG1,r13 /* save r13 */
609 EXCEPTION_PROLOG_ISERIES_1(PACA_EXSLB)
610 std r3,PACA_EXSLB+EX_R3(r13)
611 ld r12,PACALPPACA+LPPACASRR1(r13)
612 ld r3,PACALPPACA+LPPACASRR0(r13)
615 MASKABLE_EXCEPTION_ISERIES(0x500, HardwareInterrupt)
616 STD_EXCEPTION_ISERIES(0x600, Alignment, PACA_EXGEN)
617 STD_EXCEPTION_ISERIES(0x700, ProgramCheck, PACA_EXGEN)
618 STD_EXCEPTION_ISERIES(0x800, FPUnavailable, PACA_EXGEN)
619 MASKABLE_EXCEPTION_ISERIES(0x900, Decrementer)
620 STD_EXCEPTION_ISERIES(0xa00, Trap_0a, PACA_EXGEN)
621 STD_EXCEPTION_ISERIES(0xb00, Trap_0b, PACA_EXGEN)
623 .globl SystemCall_Iseries
627 EXCEPTION_PROLOG_ISERIES_2
630 STD_EXCEPTION_ISERIES( 0xd00, SingleStep, PACA_EXGEN)
631 STD_EXCEPTION_ISERIES( 0xe00, Trap_0e, PACA_EXGEN)
632 STD_EXCEPTION_ISERIES( 0xf00, PerformanceMonitor, PACA_EXGEN)
634 .globl SystemReset_Iseries
636 mfspr r13,SPRG3 /* Get paca address */
639 mtmsrd r24 /* RI on */
640 lhz r24,PACAPACAINDEX(r13) /* Get processor # */
641 cmpwi 0,r24,0 /* Are we processor 0? */
642 beq .__start_initialization_iSeries /* Start up the first processor */
644 li r5,RUNLATCH /* Turn off the run light */
651 lbz r23,PACAPROCSTART(r13) /* Test if this processor
654 LOADADDR(r3,current_set)
655 sldi r28,r24,3 /* get current_set[cpu#] */
657 addi r1,r3,THREAD_SIZE
658 subi r1,r1,STACK_FRAME_OVERHEAD
661 beq iseries_secondary_smp_loop /* Loop until told to go */
662 #ifdef SECONDARY_PROCESSORS
663 bne .__secondary_start /* Loop until told to go */
665 iseries_secondary_smp_loop:
666 /* Let the Hypervisor know we are alive */
667 /* 8002 is a call to HvCallCfg::getLps, a harmless Hypervisor function */
669 rldicr r3,r3,32,15 /* r0 = (r3 << 32) & 0xffff000000000000 */
670 #else /* CONFIG_SMP */
671 /* Yield the processor. This is required for non-SMP kernels
672 which are running on multi-threaded machines. */
674 rldicr r3,r3,32,15 /* r3 = (r3 << 32) & 0xffff000000000000 */
675 addi r3,r3,18 /* r3 = 0x8000000000000012 which is "yield" */
676 li r4,0 /* "yield timed" */
677 li r5,-1 /* "yield forever" */
678 #endif /* CONFIG_SMP */
679 li r0,-1 /* r0=-1 indicates a Hypervisor call */
680 sc /* Invoke the hypervisor via a system call */
681 mfspr r13,SPRG3 /* Put r13 back ???? */
682 b 1b /* If SMP not configured, secondaries
685 .globl Decrementer_Iseries_masked
686 Decrementer_Iseries_masked:
688 stb r11,PACALPPACA+LPPACADECRINT(r13)
689 lwz r12,PACADEFAULTDECR(r13)
693 .globl HardwareInterrupt_Iseries_masked
694 HardwareInterrupt_Iseries_masked:
695 mtcrf 0x80,r9 /* Restore regs */
696 ld r11,PACALPPACA+LPPACASRR0(r13)
697 ld r12,PACALPPACA+LPPACASRR1(r13)
700 ld r9,PACA_EXGEN+EX_R9(r13)
701 ld r10,PACA_EXGEN+EX_R10(r13)
702 ld r11,PACA_EXGEN+EX_R11(r13)
703 ld r12,PACA_EXGEN+EX_R12(r13)
704 ld r13,PACA_EXGEN+EX_R13(r13)
706 b . /* prevent speculative execution */
710 * Data area reserved for FWNMI option.
713 .globl fwnmi_data_area
717 * Vectors for the FWNMI option. Share common code.
720 .globl SystemReset_FWNMI
723 mtspr SPRG1,r13 /* save r13 */
724 EXCEPTION_PROLOG_PSERIES(PACA_EXGEN, SystemReset_common)
725 .globl MachineCheck_FWNMI
728 mtspr SPRG1,r13 /* save r13 */
729 EXCEPTION_PROLOG_PSERIES(PACA_EXMC, MachineCheck_common)
732 * Space for the initial segment table
733 * For LPAR, the hypervisor must fill in at least one entry
734 * before we get control (with relocate on)
740 . = (STAB0_PHYS_ADDR + PAGE_SIZE)
745 /*** Common interrupt handlers ***/
747 STD_EXCEPTION_COMMON(0x100, SystemReset, .SystemResetException)
750 * Machine check is different because we use a different
751 * save area: PACA_EXMC instead of PACA_EXGEN.
754 .globl MachineCheck_common
756 EXCEPTION_PROLOG_COMMON(0x200, PACA_EXMC)
759 addi r3,r1,STACK_FRAME_OVERHEAD
760 bl .MachineCheckException
763 STD_EXCEPTION_COMMON_LITE(0x900, Decrementer, .timer_interrupt)
764 STD_EXCEPTION_COMMON(0xa00, Trap_0a, .UnknownException)
765 STD_EXCEPTION_COMMON(0xb00, Trap_0b, .UnknownException)
766 STD_EXCEPTION_COMMON(0xd00, SingleStep, .SingleStepException)
767 STD_EXCEPTION_COMMON(0xe00, Trap_0e, .UnknownException)
768 STD_EXCEPTION_COMMON(0xf00, PerformanceMonitor, .PerformanceMonitorException)
769 STD_EXCEPTION_COMMON(0x1300, InstructionBreakpoint, .InstructionBreakpointException)
770 #ifdef CONFIG_ALTIVEC
771 STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .AltivecAssistException)
773 STD_EXCEPTION_COMMON(0x1700, AltivecAssist, .UnknownException)
777 * Here we have detected that the kernel stack pointer is bad.
778 * R9 contains the saved CR, r13 points to the paca,
779 * r10 contains the (bad) kernel stack pointer,
780 * r11 and r12 contain the saved SRR0 and SRR1.
781 * We switch to using the paca guard page as an emergency stack,
782 * save the registers there, and call kernel_bad_stack(), which panics.
785 ld r1,PACAEMERGSP(r13)
786 subi r1,r1,64+INT_FRAME_SIZE
807 addi r11,r1,INT_FRAME_SIZE
812 1: addi r3,r1,STACK_FRAME_OVERHEAD
817 * Return from an exception with minimal checks.
818 * The caller is assumed to have done EXCEPTION_PROLOG_COMMON.
819 * If interrupts have been enabled, or anything has been
820 * done that might have changed the scheduling status of
821 * any task or sent any task a signal, you should use
822 * ret_from_except or ret_from_except_lite instead of this.
824 fast_exception_return:
827 andi. r3,r12,MSR_RI /* check if RI is set */
841 clrrdi r10,r10,2 /* clear RI (LE is 0 already) */
849 b . /* prevent speculative execution */
853 1: addi r3,r1,STACK_FRAME_OVERHEAD
854 bl .unrecoverable_exception
858 * Here r13 points to the paca, r9 contains the saved CR,
859 * SRR0 and SRR1 are saved in r11 and r12,
860 * r9 - r13 are saved in paca->exgen.
863 .globl DataAccess_common
866 std r10,PACA_EXGEN+EX_DAR(r13)
868 stw r10,PACA_EXGEN+EX_DSISR(r13)
869 EXCEPTION_PROLOG_COMMON(0x300, PACA_EXGEN)
870 ld r3,PACA_EXGEN+EX_DAR(r13)
871 lwz r4,PACA_EXGEN+EX_DSISR(r13)
873 b .do_hash_page /* Try to handle as hpte fault */
876 .globl InstructionAccess_common
877 InstructionAccess_common:
878 EXCEPTION_PROLOG_COMMON(0x400, PACA_EXGEN)
882 b .do_hash_page /* Try to handle as hpte fault */
885 .globl HardwareInterrupt_common
886 .globl HardwareInterrupt_entry
887 HardwareInterrupt_common:
888 EXCEPTION_PROLOG_COMMON(0x500, PACA_EXGEN)
889 HardwareInterrupt_entry:
891 addi r3,r1,STACK_FRAME_OVERHEAD
893 b .ret_from_except_lite
896 .globl Alignment_common
899 std r10,PACA_EXGEN+EX_DAR(r13)
901 stw r10,PACA_EXGEN+EX_DSISR(r13)
902 EXCEPTION_PROLOG_COMMON(0x600, PACA_EXGEN)
903 ld r3,PACA_EXGEN+EX_DAR(r13)
904 lwz r4,PACA_EXGEN+EX_DSISR(r13)
908 addi r3,r1,STACK_FRAME_OVERHEAD
910 bl .AlignmentException
914 .globl ProgramCheck_common
916 EXCEPTION_PROLOG_COMMON(0x700, PACA_EXGEN)
918 addi r3,r1,STACK_FRAME_OVERHEAD
920 bl .ProgramCheckException
924 .globl FPUnavailable_common
925 FPUnavailable_common:
926 EXCEPTION_PROLOG_COMMON(0x800, PACA_EXGEN)
927 bne .load_up_fpu /* if from user, just load it up */
929 addi r3,r1,STACK_FRAME_OVERHEAD
931 bl .KernelFPUnavailableException
935 .globl AltivecUnavailable_common
936 AltivecUnavailable_common:
937 EXCEPTION_PROLOG_COMMON(0xf20, PACA_EXGEN)
938 #ifdef CONFIG_ALTIVEC
939 bne .load_up_altivec /* if from user, just load it up */
942 addi r3,r1,STACK_FRAME_OVERHEAD
944 bl .AltivecUnavailableException
951 _GLOBAL(do_hash_page)
955 andis. r0,r4,0xa450 /* weird error? */
956 bne- .handle_page_fault /* if not, try to insert a HPTE */
958 andis. r0,r4,0x0020 /* Is it a segment table fault? */
959 bne- .do_ste_alloc /* If so handle it */
960 END_FTR_SECTION_IFCLR(CPU_FTR_SLB)
963 * We need to set the _PAGE_USER bit if MSR_PR is set or if we are
964 * accessing a userspace segment (even from the kernel). We assume
965 * kernel addresses always have the high bit set.
967 rlwinm r4,r4,32-23,29,29 /* DSISR_STORE -> _PAGE_RW */
968 rotldi r0,r3,15 /* Move high bit into MSR_PR posn */
969 orc r0,r12,r0 /* MSR_PR | ~high_bit */
970 rlwimi r4,r0,32-13,30,30 /* becomes _PAGE_USER access bit */
971 ori r4,r4,1 /* add _PAGE_PRESENT */
974 * On iSeries, we soft-disable interrupts here, then
975 * hard-enable interrupts so that the hash_page code can spin on
976 * the hash_table_lock without problems on a shared processor.
981 * r3 contains the faulting address
982 * r4 contains the required access permissions
983 * r5 contains the trap number
985 * at return r3 = 0 for success
987 bl .hash_page /* build HPTE if possible */
988 cmpdi r3,0 /* see if hash_page succeeded */
990 #ifdef DO_SOFT_DISABLE
992 * If we had interrupts soft-enabled at the point where the
993 * DSI/ISI occurred, and an interrupt came in during hash_page,
995 * We jump to ret_from_except_lite rather than fast_exception_return
996 * because ret_from_except_lite will check for and handle pending
997 * interrupts if necessary.
999 beq .ret_from_except_lite
1000 /* For a hash failure, we don't bother re-enabling interrupts */
1004 * hash_page couldn't handle it, set soft interrupt enable back
1005 * to what it was before the trap. Note that .local_irq_restore
1006 * handles any interrupts pending at this point.
1009 bl .local_irq_restore
1012 beq fast_exception_return /* Return from exception on success */
1013 ble- 12f /* Failure return from hash_page */
1018 /* Here we have a page fault that hash_page can't handle. */
1019 _GLOBAL(handle_page_fault)
1023 addi r3,r1,STACK_FRAME_OVERHEAD
1026 beq+ .ret_from_except_lite
1029 addi r3,r1,STACK_FRAME_OVERHEAD
1034 /* We have a page fault that hash_page could handle but HV refused
1038 addi r3,r1,STACK_FRAME_OVERHEAD
1043 /* here we have a segment miss */
1044 _GLOBAL(do_ste_alloc)
1045 bl .ste_allocate /* try to insert stab entry */
1047 beq+ fast_exception_return
1048 b .handle_page_fault
1051 * r13 points to the PACA, r9 contains the saved CR,
1052 * r11 and r12 contain the saved SRR0 and SRR1.
1053 * r9 - r13 are saved in paca->exslb.
1054 * We assume we aren't going to take any exceptions during this procedure.
1055 * We assume (DAR >> 60) == 0xc.
1058 _GLOBAL(do_stab_bolted)
1059 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1060 std r11,PACA_EXSLB+EX_SRR0(r13) /* save SRR0 in exc. frame */
1062 /* Hash to the primary group */
1063 ld r10,PACASTABVIRT(r13)
1066 rldimi r10,r11,7,52 /* r10 = first ste of the group */
1068 /* Calculate VSID */
1069 /* This is a kernel address, so protovsid = ESID */
1070 ASM_VSID_SCRAMBLE(r11, r9)
1071 rldic r9,r11,12,16 /* r9 = vsid << 12 */
1073 /* Search the primary group for a free entry */
1074 1: ld r11,0(r10) /* Test valid bit of the current ste */
1081 /* Stick for only searching the primary group for now. */
1082 /* At least for now, we use a very simple random castout scheme */
1083 /* Use the TB as a random number ; OR in 1 to avoid entry 0 */
1085 rldic r11,r11,4,57 /* r11 = (r11 << 4) & 0x70 */
1088 /* r10 currently points to an ste one past the group of interest */
1089 /* make it point to the randomly selected entry */
1091 or r10,r10,r11 /* r10 is the entry to invalidate */
1093 isync /* mark the entry invalid */
1095 rldicl r11,r11,56,1 /* clear the valid bit */
1100 clrrdi r11,r11,28 /* Get the esid part of the ste */
1103 2: std r9,8(r10) /* Store the vsid part of the ste */
1106 mfspr r11,DAR /* Get the new esid */
1107 clrrdi r11,r11,28 /* Permits a full 32b of ESID */
1108 ori r11,r11,0x90 /* Turn on valid and kp */
1109 std r11,0(r10) /* Put new entry back into the stab */
1113 /* All done -- return from exception. */
1114 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1115 ld r11,PACA_EXSLB+EX_SRR0(r13) /* get saved SRR0 */
1117 andi. r10,r12,MSR_RI
1120 mtcrf 0x80,r9 /* restore CR */
1128 ld r9,PACA_EXSLB+EX_R9(r13)
1129 ld r10,PACA_EXSLB+EX_R10(r13)
1130 ld r11,PACA_EXSLB+EX_R11(r13)
1131 ld r12,PACA_EXSLB+EX_R12(r13)
1132 ld r13,PACA_EXSLB+EX_R13(r13)
1134 b . /* prevent speculative execution */
1137 * r13 points to the PACA, r9 contains the saved CR,
1138 * r11 and r12 contain the saved SRR0 and SRR1.
1139 * r3 has the faulting address
1140 * r9 - r13 are saved in paca->exslb.
1141 * r3 is saved in paca->slb_r3
1142 * We assume we aren't going to take any exceptions during this procedure.
1144 _GLOBAL(do_slb_miss)
1147 stw r9,PACA_EXSLB+EX_CCR(r13) /* save CR in exc. frame */
1148 std r10,PACA_EXSLB+EX_LR(r13) /* save LR */
1150 bl .slb_allocate /* handle it */
1152 /* All done -- return from exception. */
1154 ld r10,PACA_EXSLB+EX_LR(r13)
1155 ld r3,PACA_EXSLB+EX_R3(r13)
1156 lwz r9,PACA_EXSLB+EX_CCR(r13) /* get saved CR */
1157 #ifdef CONFIG_PPC_ISERIES
1158 ld r11,PACALPPACA+LPPACASRR0(r13) /* get SRR0 value */
1159 #endif /* CONFIG_PPC_ISERIES */
1163 andi. r10,r12,MSR_RI /* check for unrecoverable exception */
1169 mtcrf 0x01,r9 /* slb_allocate uses cr0 and cr7 */
1172 #ifdef CONFIG_PPC_ISERIES
1175 #endif /* CONFIG_PPC_ISERIES */
1176 ld r9,PACA_EXSLB+EX_R9(r13)
1177 ld r10,PACA_EXSLB+EX_R10(r13)
1178 ld r11,PACA_EXSLB+EX_R11(r13)
1179 ld r12,PACA_EXSLB+EX_R12(r13)
1180 ld r13,PACA_EXSLB+EX_R13(r13)
1182 b . /* prevent speculative execution */
1185 EXCEPTION_PROLOG_COMMON(0x4100, PACA_EXSLB)
1188 1: addi r3,r1,STACK_FRAME_OVERHEAD
1189 bl .unrecoverable_exception
1194 * On pSeries, secondary processors spin in the following code.
1195 * At entry, r3 = this processor's number (in Linux terms, not hardware).
1197 _GLOBAL(pseries_secondary_smp_init)
1198 /* turn on 64-bit mode */
1202 /* Set up a paca value for this processor. */
1203 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1204 mulli r13,r3,PACA_SIZE /* Calculate vaddr of right paca */
1205 add r13,r13,r24 /* for this processor. */
1207 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1208 mr r24,r3 /* __secondary_start needs cpu# */
1212 lbz r23,PACAPROCSTART(r13) /* Test if this processor should */
1216 /* Create a temp kernel stack for use before relocation is on. */
1217 ld r1,PACAEMERGSP(r13)
1218 subi r1,r1,STACK_FRAME_OVERHEAD
1222 #ifdef SECONDARY_PROCESSORS
1223 bne .__secondary_start
1226 b 1b /* Loop until told to go */
1227 #ifdef CONFIG_PPC_ISERIES
1228 _STATIC(__start_initialization_iSeries)
1229 /* Clear out the BSS */
1230 LOADADDR(r11,__bss_stop)
1231 LOADADDR(r8,__bss_start)
1232 sub r11,r11,r8 /* bss size */
1233 addi r11,r11,7 /* round up to an even double word */
1234 rldicl. r11,r11,61,3 /* shift right by 3 */
1238 mtctr r11 /* zero this many doublewords */
1242 LOADADDR(r1,init_thread_union)
1243 addi r1,r1,THREAD_SIZE
1245 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1247 LOADADDR(r3,cpu_specs)
1248 LOADADDR(r4,cur_cpu_spec)
1252 LOADADDR(r2,__toc_start)
1256 LOADADDR(r9,systemcfg)
1257 SET_REG_TO_CONST(r4, SYSTEMCFG_VIRT_ADDR)
1258 std r4,0(r9) /* set the systemcfg pointer */
1261 SET_REG_TO_CONST(r4, NACA_VIRT_ADDR)
1262 std r4,0(r9) /* set the naca pointer */
1264 /* Get the pointer to the segment table */
1265 ld r6,PACA(r4) /* Get the base paca pointer */
1266 ld r4,PACASTABVIRT(r6)
1268 bl .iSeries_early_setup
1270 /* relocation is on at this point */
1272 b .start_here_common
1273 #endif /* CONFIG_PPC_ISERIES */
1275 #ifdef CONFIG_PPC_MULTIPLATFORM
1279 andi. r0,r3,MSR_IR|MSR_DR
1286 b . /* prevent speculative execution */
1290 * Here is our main kernel entry point. We support currently 2 kind of entries
1291 * depending on the value of r5.
1293 * r5 != NULL -> OF entry, we go to prom_init, "legacy" parameter content
1296 * r5 == NULL -> kexec style entry. r3 is a physical pointer to the
1297 * DT block, r4 is a physical pointer to the kernel itself
1300 _GLOBAL(__start_initialization_multiplatform)
1302 * Are we booted from a PROM Of-type client-interface ?
1305 bne .__boot_from_prom /* yes -> prom */
1307 /* Save parameters */
1311 /* Make sure we are running in 64 bits mode */
1314 /* Setup some critical 970 SPRs before switching MMU off */
1315 bl .__970_cpu_preinit
1320 /* Switch off MMU if not already */
1321 LOADADDR(r4, .__after_prom_start - KERNELBASE)
1324 b .__after_prom_start
1326 _STATIC(__boot_from_prom)
1327 /* Save parameters */
1334 /* Make sure we are running in 64 bits mode */
1337 /* put a relocation offset into r3 */
1340 LOADADDR(r2,__toc_start)
1344 /* Relocate the TOC from a virt addr to a real addr */
1347 /* Restore parameters */
1354 /* Do all of the interaction with OF client interface */
1356 /* We never return */
1360 * At this point, r3 contains the physical address we are running at,
1361 * returned by prom_init()
1363 _STATIC(__after_prom_start)
1366 * We need to run with __start at physical address 0.
1367 * This will leave some code in the first 256B of
1368 * real memory, which are reserved for software use.
1369 * The remainder of the first page is loaded with the fixed
1370 * interrupt vectors. The next two pages are filled with
1371 * unknown exception placeholders.
1373 * Note: This process overwrites the OF exception vectors.
1374 * r26 == relocation offset
1379 SET_REG_TO_CONST(r27,KERNELBASE)
1381 li r3,0 /* target addr */
1383 // XXX FIXME: Use phys returned by OF (r30)
1384 sub r4,r27,r26 /* source addr */
1385 /* current address of _start */
1386 /* i.e. where we are running */
1387 /* the source addr */
1389 LOADADDR(r5,copy_to_here) /* # bytes of memory to copy */
1392 li r6,0x100 /* Start offset, the first 0x100 */
1393 /* bytes were copied earlier. */
1395 bl .copy_and_flush /* copy the first n bytes */
1396 /* this includes the code being */
1397 /* executed here. */
1399 LOADADDR(r0, 4f) /* Jump to the copy of this code */
1400 mtctr r0 /* that we just made/relocated */
1403 4: LOADADDR(r5,klimit)
1405 ld r5,0(r5) /* get the value of klimit */
1407 bl .copy_and_flush /* copy the rest */
1408 b .start_here_multiplatform
1410 #endif /* CONFIG_PPC_MULTIPLATFORM */
1413 * Copy routine used to copy the kernel to start at physical address 0
1414 * and flush and invalidate the caches as needed.
1415 * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
1416 * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
1418 * Note: this routine *only* clobbers r0, r6 and lr
1420 _GLOBAL(copy_and_flush)
1423 4: li r0,16 /* Use the least common */
1424 /* denominator cache line */
1425 /* size. This results in */
1426 /* extra cache line flushes */
1427 /* but operation is correct. */
1428 /* Can't get cache line size */
1429 /* from NACA as it is being */
1432 mtctr r0 /* put # words/line in ctr */
1433 3: addi r6,r6,8 /* copy a cache line */
1437 dcbst r6,r3 /* write it to memory */
1439 icbi r6,r3 /* flush the icache line */
1451 * load_up_fpu(unused, unused, tsk)
1452 * Disable FP for the task which had the FPU previously,
1453 * and save its floating-point registers in its thread_struct.
1454 * Enables the FPU for use in the kernel on return.
1455 * On SMP we know the fpu is free, since we give it up every
1456 * switch (ie, no lazy save of the FP registers).
1457 * On entry: r13 == 'current' && last_task_used_math != 'current'
1459 _STATIC(load_up_fpu)
1460 mfmsr r5 /* grab the current MSR */
1462 mtmsrd r5 /* enable use of fpu now */
1465 * For SMP, we don't do lazy FPU switching because it just gets too
1466 * horrendously complex, especially when a task switches from one CPU
1467 * to another. Instead we call giveup_fpu in switch_to.
1471 ld r3,last_task_used_math@got(r2)
1475 /* Save FP state to last_task_used_math's THREAD struct */
1479 stfd fr0,THREAD_FPSCR(r4)
1480 /* Disable FP for last_task_used_math */
1482 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1483 li r6,MSR_FP|MSR_FE0|MSR_FE1
1485 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1487 #endif /* CONFIG_SMP */
1488 /* enable use of FP after return */
1489 ld r4,PACACURRENT(r13)
1490 addi r5,r4,THREAD /* Get THREAD */
1491 ld r4,THREAD_FPEXC_MODE(r5)
1495 lfd fr0,THREAD_FPSCR(r5)
1499 /* Update last_task_used_math to 'current' */
1500 subi r4,r5,THREAD /* Back to 'current' */
1502 #endif /* CONFIG_SMP */
1503 /* restore registers and return */
1504 b fast_exception_return
1507 * disable_kernel_fp()
1510 _GLOBAL(disable_kernel_fp)
1512 rldicl r0,r3,(63-MSR_FP_LG),1
1513 rldicl r3,r0,(MSR_FP_LG+1),0
1514 mtmsrd r3 /* disable use of fpu now */
1520 * Disable FP for the task given as the argument,
1521 * and save the floating-point registers in its thread_struct.
1522 * Enables the FPU for use in the kernel on return.
1527 mtmsrd r5 /* enable use of fpu now */
1530 beqlr- /* if no previous owner, done */
1531 addi r3,r3,THREAD /* want THREAD of task */
1536 stfd fr0,THREAD_FPSCR(r3)
1538 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1539 li r3,MSR_FP|MSR_FE0|MSR_FE1
1540 andc r4,r4,r3 /* disable FP for previous task */
1541 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1545 ld r4,last_task_used_math@got(r2)
1547 #endif /* CONFIG_SMP */
1551 #ifdef CONFIG_ALTIVEC
1554 * load_up_altivec(unused, unused, tsk)
1555 * Disable VMX for the task which had it previously,
1556 * and save its vector registers in its thread_struct.
1557 * Enables the VMX for use in the kernel on return.
1558 * On SMP we know the VMX is free, since we give it up every
1559 * switch (ie, no lazy save of the vector registers).
1560 * On entry: r13 == 'current' && last_task_used_altivec != 'current'
1562 _STATIC(load_up_altivec)
1563 mfmsr r5 /* grab the current MSR */
1564 oris r5,r5,MSR_VEC@h
1565 mtmsrd r5 /* enable use of VMX now */
1569 * For SMP, we don't do lazy VMX switching because it just gets too
1570 * horrendously complex, especially when a task switches from one CPU
1571 * to another. Instead we call giveup_altvec in switch_to.
1572 * VRSAVE isn't dealt with here, that is done in the normal context
1573 * switch code. Note that we could rely on vrsave value to eventually
1574 * avoid saving all of the VREGs here...
1577 ld r3,last_task_used_altivec@got(r2)
1581 /* Save VMX state to last_task_used_altivec's THREAD struct */
1587 /* Disable VMX for last_task_used_altivec */
1589 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1592 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1594 #endif /* CONFIG_SMP */
1595 /* Hack: if we get an altivec unavailable trap with VRSAVE
1596 * set to all zeros, we assume this is a broken application
1597 * that fails to set it properly, and thus we switch it to
1600 mfspr r4,SPRN_VRSAVE
1604 mtspr SPRN_VRSAVE,r4
1606 /* enable use of VMX after return */
1607 ld r4,PACACURRENT(r13)
1608 addi r5,r4,THREAD /* Get THREAD */
1609 oris r12,r12,MSR_VEC@h
1613 stw r4,THREAD_USED_VR(r5)
1618 /* Update last_task_used_math to 'current' */
1619 subi r4,r5,THREAD /* Back to 'current' */
1621 #endif /* CONFIG_SMP */
1622 /* restore registers and return */
1623 b fast_exception_return
1626 * disable_kernel_altivec()
1629 _GLOBAL(disable_kernel_altivec)
1631 rldicl r0,r3,(63-MSR_VEC_LG),1
1632 rldicl r3,r0,(MSR_VEC_LG+1),0
1633 mtmsrd r3 /* disable use of VMX now */
1638 * giveup_altivec(tsk)
1639 * Disable VMX for the task given as the argument,
1640 * and save the vector registers in its thread_struct.
1641 * Enables the VMX for use in the kernel on return.
1643 _GLOBAL(giveup_altivec)
1645 oris r5,r5,MSR_VEC@h
1646 mtmsrd r5 /* enable use of VMX now */
1649 beqlr- /* if no previous owner, done */
1650 addi r3,r3,THREAD /* want THREAD of task */
1658 ld r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1660 andc r4,r4,r3 /* disable FP for previous task */
1661 std r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1665 ld r4,last_task_used_altivec@got(r2)
1667 #endif /* CONFIG_SMP */
1670 #endif /* CONFIG_ALTIVEC */
1673 #ifdef CONFIG_PPC_PMAC
1675 * On PowerMac, secondary processors starts from the reset vector, which
1676 * is temporarily turned into a call to one of the functions below.
1681 .globl pmac_secondary_start_1
1682 pmac_secondary_start_1:
1684 b .pmac_secondary_start
1686 .globl pmac_secondary_start_2
1687 pmac_secondary_start_2:
1689 b .pmac_secondary_start
1691 .globl pmac_secondary_start_3
1692 pmac_secondary_start_3:
1694 b .pmac_secondary_start
1696 _GLOBAL(pmac_secondary_start)
1697 /* turn on 64-bit mode */
1701 /* Copy some CPU settings from CPU 0 */
1702 bl .__restore_cpu_setup
1704 /* pSeries do that early though I don't think we really need it */
1707 mtmsrd r3 /* RI on */
1709 /* Set up a paca value for this processor. */
1710 LOADADDR(r4, paca) /* Get base vaddr of paca array */
1711 mulli r13,r24,PACA_SIZE /* Calculate vaddr of right paca */
1712 add r13,r13,r4 /* for this processor. */
1713 mtspr SPRG3,r13 /* Save vaddr of paca in SPRG3 */
1715 /* Create a temp kernel stack for use before relocation is on. */
1716 ld r1,PACAEMERGSP(r13)
1717 subi r1,r1,STACK_FRAME_OVERHEAD
1719 b .__secondary_start
1721 #endif /* CONFIG_PPC_PMAC */
1724 * This function is called after the master CPU has released the
1725 * secondary processors. The execution environment is relocation off.
1726 * The paca for this processor has the following fields initialized at
1728 * 1. Processor number
1729 * 2. Segment table pointer (virtual address)
1730 * On entry the following are set:
1731 * r1 = stack pointer. vaddr for iSeries, raddr (temp stack) for pSeries
1732 * r24 = cpu# (in Linux terms)
1733 * r13 = paca virtual address
1734 * SPRG3 = paca virtual address
1736 _GLOBAL(__secondary_start)
1738 HMT_MEDIUM /* Set thread priority to MEDIUM */
1742 stb r6,PACAPROCENABLED(r13)
1744 #ifndef CONFIG_PPC_ISERIES
1745 /* Initialize the page table pointer register. */
1747 ld r6,0(r6) /* get the value of _SDR1 */
1748 mtspr SDR1,r6 /* set the htab location */
1750 /* Initialize the first segment table (or SLB) entry */
1751 ld r3,PACASTABVIRT(r13) /* get addr of segment table */
1754 /* Initialize the kernel stack. Just a repeat for iSeries. */
1755 LOADADDR(r3,current_set)
1756 sldi r28,r24,3 /* get current_set[cpu#] */
1758 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1759 std r1,PACAKSAVE(r13)
1761 ld r3,PACASTABREAL(r13) /* get raddr of segment table */
1762 ori r4,r3,1 /* turn on valid bit */
1764 #ifdef CONFIG_PPC_ISERIES
1765 li r0,-1 /* hypervisor call */
1767 sldi r3,r3,63 /* 0x8000000000000000 */
1768 ori r3,r3,4 /* 0x8000000000000004 */
1769 sc /* HvCall_setASR */
1772 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1773 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1774 cmpldi r3,PLATFORM_PSERIES_LPAR
1778 cmpwi r3,0x37 /* SStar */
1780 cmpwi r3,0x36 /* IStar */
1782 cmpwi r3,0x34 /* Pulsar */
1784 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1785 HVSC /* Invoking hcall */
1787 98: /* !(rpa hypervisor) || !(star) */
1788 mtasr r4 /* set the stab location */
1794 /* enable MMU and jump to start_secondary */
1795 LOADADDR(r3,.start_secondary_prolog)
1796 SET_REG_TO_CONST(r4, MSR_KERNEL)
1797 #ifdef DO_SOFT_DISABLE
1803 b . /* prevent speculative execution */
1806 * Running with relocation on at this point. All we want to do is
1807 * zero the stack back-chain pointer before going into C code.
1809 _GLOBAL(start_secondary_prolog)
1811 std r3,0(r1) /* Zero the stack frame pointer */
1816 * This subroutine clobbers r11 and r12
1818 _GLOBAL(enable_64b_mode)
1819 mfmsr r11 /* grab the current MSR */
1821 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
1824 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
1830 #ifdef CONFIG_PPC_MULTIPLATFORM
1832 * This is where the main kernel code starts.
1834 _STATIC(start_here_multiplatform)
1835 /* get a new offset, now that the kernel has moved. */
1839 /* Clear out the BSS. It may have been done in prom_init,
1840 * already but that's irrelevant since prom_init will soon
1841 * be detached from the kernel completely. Besides, we need
1842 * to clear it now for kexec-style entry.
1844 LOADADDR(r11,__bss_stop)
1845 LOADADDR(r8,__bss_start)
1846 sub r11,r11,r8 /* bss size */
1847 addi r11,r11,7 /* round up to an even double word */
1848 rldicl. r11,r11,61,3 /* shift right by 3 */
1852 mtctr r11 /* zero this many doublewords */
1859 mtmsrd r6 /* RI on */
1861 /* setup the systemcfg pointer which is needed by *tab_initialize */
1862 LOADADDR(r6,systemcfg)
1863 sub r6,r6,r26 /* addr of the variable systemcfg */
1864 li r27,SYSTEMCFG_PHYS_ADDR
1865 std r27,0(r6) /* set the value of systemcfg */
1867 /* setup the naca pointer which is needed by *tab_initialize */
1869 sub r6,r6,r26 /* addr of the variable naca */
1870 li r27,NACA_PHYS_ADDR
1871 std r27,0(r6) /* set the value of naca */
1874 /* Start up the second thread on cpu 0 */
1877 cmpwi r3,0x34 /* Pulsar */
1879 cmpwi r3,0x36 /* Icestar */
1881 cmpwi r3,0x37 /* SStar */
1883 b 91f /* HMT not supported */
1885 bl .hmt_start_secondary
1890 /* All secondary cpus are now spinning on a common
1891 * spinloop, release them all now so they can start
1892 * to spin on their individual paca spinloops.
1893 * For non SMP kernels, the secondary cpus never
1894 * get out of the common spinloop.
1897 LOADADDR(r5,__secondary_hold_spinloop)
1902 /* The following gets the stack and TOC set up with the regs */
1903 /* pointing to the real addr of the kernel stack. This is */
1904 /* all done to support the C function call below which sets */
1905 /* up the htab. This is done because we have relocated the */
1906 /* kernel but are still running in real mode. */
1908 LOADADDR(r3,init_thread_union)
1911 /* set up a stack pointer (physical address) */
1912 addi r1,r3,THREAD_SIZE
1914 stdu r0,-STACK_FRAME_OVERHEAD(r1)
1916 /* set up the TOC (physical address) */
1917 LOADADDR(r2,__toc_start)
1922 LOADADDR(r3,cpu_specs)
1924 LOADADDR(r4,cur_cpu_spec)
1929 /* Setup a valid physical PACA pointer in SPRG3 for early_setup
1930 * note that boot_cpuid can always be 0 nowadays since there is
1931 * nowhere it can be initialized differently before we reach this
1934 LOADADDR(r27, boot_cpuid)
1938 LOADADDR(r24, paca) /* Get base vaddr of paca array */
1939 mulli r13,r27,PACA_SIZE /* Calculate vaddr of right paca */
1940 add r13,r13,r24 /* for this processor. */
1941 sub r13,r13,r26 /* convert to physical addr */
1942 mtspr SPRG3,r13 /* PPPBBB: Temp... -Peter */
1944 /* Do very early kernel initializations, including initial hash table,
1945 * stab and slb setup before we turn on relocation. */
1947 /* Restore parameters passed from prom_init/kexec */
1952 ld r3,PACASTABREAL(r13)
1953 ori r4,r3,1 /* turn on valid bit */
1954 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1955 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1956 cmpldi r3,PLATFORM_PSERIES_LPAR
1960 cmpwi r3,0x37 /* SStar */
1962 cmpwi r3,0x36 /* IStar */
1964 cmpwi r3,0x34 /* Pulsar */
1966 97: li r3,H_SET_ASR /* hcall = H_SET_ASR */
1967 HVSC /* Invoking hcall */
1969 98: /* !(rpa hypervisor) || !(star) */
1970 mtasr r4 /* set the stab location */
1972 /* Set SDR1 (hash table pointer) */
1973 li r3,SYSTEMCFG_PHYS_ADDR /* r3 = ptr to systemcfg */
1974 lwz r3,PLATFORM(r3) /* r3 = platform flags */
1975 /* Test if bit 0 is set (LPAR bit) */
1978 LOADADDR(r6,_SDR1) /* Only if NOT LPAR */
1980 ld r6,0(r6) /* get the value of _SDR1 */
1981 mtspr SDR1,r6 /* set the htab location */
1983 LOADADDR(r3,.start_here_common)
1984 SET_REG_TO_CONST(r4, MSR_KERNEL)
1988 b . /* prevent speculative execution */
1989 #endif /* CONFIG_PPC_MULTIPLATFORM */
1991 /* This is where all platforms converge execution */
1992 _STATIC(start_here_common)
1993 /* relocation is on at this point */
1995 /* The following code sets up the SP and TOC now that we are */
1996 /* running with translation enabled. */
1998 LOADADDR(r3,init_thread_union)
2000 /* set up the stack */
2001 addi r1,r3,THREAD_SIZE
2003 stdu r0,-STACK_FRAME_OVERHEAD(r1)
2005 /* Apply the CPUs-specific fixups (nop out sections not relevant
2009 bl .do_cpu_ftr_fixups
2011 /* setup the systemcfg pointer */
2012 LOADADDR(r9,systemcfg)
2013 SET_REG_TO_CONST(r8, SYSTEMCFG_VIRT_ADDR)
2016 /* setup the naca pointer */
2018 SET_REG_TO_CONST(r8, NACA_VIRT_ADDR)
2019 std r8,0(r9) /* set the value of the naca ptr */
2021 LOADADDR(r26, boot_cpuid)
2024 LOADADDR(r24, paca) /* Get base vaddr of paca array */
2025 mulli r13,r26,PACA_SIZE /* Calculate vaddr of right paca */
2026 add r13,r13,r24 /* for this processor. */
2029 /* ptr to current */
2030 LOADADDR(r4,init_task)
2031 std r4,PACACURRENT(r13)
2035 std r1,PACAKSAVE(r13)
2039 /* Load up the kernel context */
2041 #ifdef DO_SOFT_DISABLE
2043 stb r5,PACAPROCENABLED(r13) /* Soft Disabled */
2045 ori r5,r5,MSR_EE /* Hard Enabled */
2051 _GLOBAL(__setup_cpu_power3)
2056 LOADADDR(r5, hmt_thread_data)
2059 cmpwi r7,0x34 /* Pulsar */
2061 cmpwi r7,0x36 /* Icestar */
2063 cmpwi r7,0x37 /* SStar */
2073 bl .hmt_start_secondary
2076 __hmt_secondary_hold:
2077 LOADADDR(r5, hmt_thread_data)
2087 93: andi. r6,r6,0x3f
2101 b .pseries_secondary_smp_init
2104 _GLOBAL(hmt_start_secondary)
2105 LOADADDR(r4,__hmt_secondary_hold)
2127 * We put a few things here that have to be page-aligned.
2128 * This stuff goes at the beginning of the data segment,
2129 * which is page-aligned.
2135 .globl empty_zero_page
2139 .globl swapper_pg_dir
2147 /* 1 page segment table per cpu (max 48, cpu0 allocated at STAB0_PHYS_ADDR) */
2153 * This space gets a copy of optional info passed to us by the bootstrap
2154 * Used to pass parameters into the kernel like root=/dev/sda1, etc.
2158 .space COMMAND_LINE_SIZE