2 * arch/ppc/syslib/mpc10x_common.c
4 * Common routines for the Motorola SPS MPC106, MPC107 and MPC8240 Host bridge,
7 * Author: Mark A. Greer
10 * 2001 (c) MontaVista, Software, Inc. This file is licensed under
11 * the terms of the GNU General Public License version 2. This program
12 * is licensed "as is" without any warranty of any kind, whether express
17 * *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/slab.h>
25 #include <asm/byteorder.h>
28 #include <asm/uaccess.h>
29 #include <asm/machdep.h>
30 #include <asm/pci-bridge.h>
31 #include <asm/open_pic.h>
32 #include <asm/mpc10x.h>
35 /* The OCP structure is fixed by code below, before OCP initialises.
36 paddr depends on where the board places the EUMB.
37 - fixed in mpc10x_bridge_init().
38 irq depends on two things:
39 > does the board use the EPIC at all? (PCORE does not).
40 > is the EPIC in serial or parallel mode?
41 - fixed in mpc10x_set_openpic().
44 #ifdef CONFIG_MPC10X_OPENPIC
45 #ifdef CONFIG_EPIC_SERIAL_MODE
46 #define EPIC_IRQ_BASE 16
48 #define EPIC_IRQ_BASE 5
50 #define MPC10X_I2C_IRQ (EPIC_IRQ_BASE + NUM_8259_INTERRUPTS)
51 #define MPC10X_DMA0_IRQ (EPIC_IRQ_BASE + 1 + NUM_8259_INTERRUPTS)
52 #define MPC10X_DMA1_IRQ (EPIC_IRQ_BASE + 2 + NUM_8259_INTERRUPTS)
54 #define MPC10X_I2C_IRQ OCP_IRQ_NA
55 #define MPC10X_DMA0_IRQ OCP_IRQ_NA
56 #define MPC10X_DMA1_IRQ OCP_IRQ_NA
60 struct ocp_def core_ocp
[] = {
61 { .vendor
= OCP_VENDOR_INVALID
65 static struct ocp_fs_i2c_data mpc10x_i2c_data
= {
68 static struct ocp_def mpc10x_i2c_ocp
= {
69 .vendor
= OCP_VENDOR_MOTOROLA
,
70 .function
= OCP_FUNC_IIC
,
72 .irq
= MPC10X_I2C_IRQ
,
73 .additions
= &mpc10x_i2c_data
76 static struct ocp_def mpc10x_dma_ocp
[2] = {
77 { .vendor
= OCP_VENDOR_MOTOROLA
,
78 .function
= OCP_FUNC_DMA
,
80 .irq
= MPC10X_DMA0_IRQ
82 { .vendor
= OCP_VENDOR_MOTOROLA
,
83 .function
= OCP_FUNC_DMA
,
85 .irq
= MPC10X_DMA1_IRQ
}
88 /* Set resources to match bridge memory map */
90 mpc10x_bridge_set_resources(int map
, struct pci_controller
*hose
)
94 case MPC10X_MEM_MAP_A
:
95 pci_init_resource(&hose
->io_resource
,
101 pci_init_resource (&hose
->mem_resources
[0],
107 case MPC10X_MEM_MAP_B
:
108 pci_init_resource(&hose
->io_resource
,
114 pci_init_resource (&hose
->mem_resources
[0],
121 printk("mpc10x_bridge_set_resources: "
122 "Invalid map specified\n");
124 ppc_md
.progress("mpc10x:exit1", 0x100);
128 * Do some initialization and put the EUMB registers at the specified address
129 * (also map the EPIC registers into virtual space--OpenPIC_Addr will be set).
131 * The EPIC is not on the 106, only the 8240 and 107.
134 mpc10x_bridge_init(struct pci_controller
*hose
,
139 int host_bridge
, picr1
, picr1_bit
;
140 ulong pci_config_addr
, pci_config_data
;
143 if (ppc_md
.progress
) ppc_md
.progress("mpc10x:enter", 0x100);
145 /* Set up for current map so we can get at config regs */
146 switch (current_map
) {
147 case MPC10X_MEM_MAP_A
:
148 setup_indirect_pci(hose
,
149 MPC10X_MAPA_CNFG_ADDR
,
150 MPC10X_MAPA_CNFG_DATA
);
152 case MPC10X_MEM_MAP_B
:
153 setup_indirect_pci(hose
,
154 MPC10X_MAPB_CNFG_ADDR
,
155 MPC10X_MAPB_CNFG_DATA
);
158 printk("mpc10x_bridge_init: %s\n",
159 "Invalid current map specified");
161 ppc_md
.progress("mpc10x:exit1", 0x100);
165 /* Make sure it's a supported bridge */
166 early_read_config_dword(hose
,
172 switch (host_bridge
) {
173 case MPC10X_BRIDGE_106
:
174 case MPC10X_BRIDGE_8240
:
175 case MPC10X_BRIDGE_107
:
176 case MPC10X_BRIDGE_8245
:
180 ppc_md
.progress("mpc10x:exit2", 0x100);
185 case MPC10X_MEM_MAP_A
:
186 MPC10X_SETUP_HOSE(hose
, A
);
187 pci_config_addr
= MPC10X_MAPA_CNFG_ADDR
;
188 pci_config_data
= MPC10X_MAPA_CNFG_DATA
;
189 picr1_bit
= MPC10X_CFG_PICR1_ADDR_MAP_A
;
191 case MPC10X_MEM_MAP_B
:
192 MPC10X_SETUP_HOSE(hose
, B
);
193 pci_config_addr
= MPC10X_MAPB_CNFG_ADDR
;
194 pci_config_data
= MPC10X_MAPB_CNFG_DATA
;
195 picr1_bit
= MPC10X_CFG_PICR1_ADDR_MAP_B
;
198 printk("mpc10x_bridge_init: %s\n",
199 "Invalid new map specified");
201 ppc_md
.progress("mpc10x:exit3", 0x100);
205 /* Make bridge use the 'new_map', if not already usng it */
206 if (current_map
!= new_map
) {
207 early_read_config_dword(hose
,
210 MPC10X_CFG_PICR1_REG
,
213 picr1
= (picr1
& ~MPC10X_CFG_PICR1_ADDR_MAP_MASK
) |
216 early_write_config_dword(hose
,
219 MPC10X_CFG_PICR1_REG
,
222 asm volatile("sync");
224 /* Undo old mappings & map in new cfg data/addr regs */
225 iounmap((void *)hose
->cfg_addr
);
226 iounmap((void *)hose
->cfg_data
);
228 setup_indirect_pci(hose
,
233 /* Setup resources to match map */
234 mpc10x_bridge_set_resources(new_map
, hose
);
237 * Want processor accesses of 0xFDxxxxxx to be mapped
238 * to PCI memory space at 0x00000000. Do not want
239 * host bridge to respond to PCI memory accesses of
240 * 0xFDxxxxxx. Do not want host bridge to respond
241 * to PCI memory addresses 0xFD000000-0xFDFFFFFF;
242 * want processor accesses from 0x000A0000-0x000BFFFF
243 * to be forwarded to system memory.
245 * Only valid if not in agent mode and using MAP B.
247 if (new_map
== MPC10X_MEM_MAP_B
) {
248 early_read_config_byte(hose
,
251 MPC10X_CFG_MAPB_OPTIONS_REG
,
254 byte
&= ~(MPC10X_CFG_MAPB_OPTIONS_PFAE
|
255 MPC10X_CFG_MAPB_OPTIONS_PCICH
|
256 MPC10X_CFG_MAPB_OPTIONS_PROCCH
);
258 if (host_bridge
!= MPC10X_BRIDGE_106
) {
259 byte
|= MPC10X_CFG_MAPB_OPTIONS_CFAE
;
262 early_write_config_byte(hose
,
265 MPC10X_CFG_MAPB_OPTIONS_REG
,
269 if (host_bridge
!= MPC10X_BRIDGE_106
) {
270 early_read_config_byte(hose
,
276 if (pir
!= MPC10X_CFG_PIR_HOST_BRIDGE
) {
277 printk("Host bridge in Agent mode\n");
278 /* Read or Set LMBAR & PCSRBAR? */
281 /* Set base addr of the 8240/107 EUMB. */
282 early_write_config_dword(hose
,
287 #ifdef CONFIG_MPC10X_OPENPIC
288 /* Map EPIC register part of EUMB into vitual memory - PCORE
289 uses an i8259 instead of EPIC. */
291 ioremap(phys_eumb_base
+ MPC10X_EUMB_EPIC_OFFSET
,
292 MPC10X_EUMB_EPIC_SIZE
);
294 mpc10x_i2c_ocp
.paddr
= phys_eumb_base
+ MPC10X_EUMB_I2C_OFFSET
;
295 ocp_add_one_device(&mpc10x_i2c_ocp
);
296 mpc10x_dma_ocp
[0].paddr
= phys_eumb_base
+
297 MPC10X_EUMB_DMA_OFFSET
+ 0x100;
298 ocp_add_one_device(&mpc10x_dma_ocp
[0]);
299 mpc10x_dma_ocp
[1].paddr
= phys_eumb_base
+
300 MPC10X_EUMB_DMA_OFFSET
+ 0x200;
301 ocp_add_one_device(&mpc10x_dma_ocp
[1]);
304 #ifdef CONFIG_MPC10X_STORE_GATHERING
305 mpc10x_enable_store_gathering(hose
);
307 mpc10x_disable_store_gathering(hose
);
310 if (ppc_md
.progress
) ppc_md
.progress("mpc10x:exit", 0x100);
315 * Need to make our own PCI config space access macros because
316 * mpc10x_get_mem_size() is called before the data structures are set up for
317 * the 'early_xxx' and 'indirect_xxx' routines to work.
320 #define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr))
321 #define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val))
323 #define MPC10X_PCI_OP(rw, size, type, op, mask) \
325 mpc10x_##rw##_config_##size(uint *cfg_addr, uint *cfg_data, int devfn, int offset, type val) \
328 ((offset & 0xfc) << 24) | (devfn << 16) \
329 | (0 << 8) | 0x80); \
330 MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \
334 MPC10X_PCI_OP(read
, byte
, u8
*, in_8
, 3)
335 MPC10X_PCI_OP(read
, dword
, u32
*, in_le32
, 0)
337 MPC10X_PCI_OP(write
, byte
, u8
, out_8
, 3)
338 MPC10X_PCI_OP(read
, word
, u16
*, in_le16
, 2)
339 MPC10X_PCI_OP(write
, word
, u16
, out_le16
, 2)
340 MPC10X_PCI_OP(write
, dword
, u32
, out_le32
, 0)
344 * Read the memory controller registers to determine the amount of memory in
345 * the system. This assumes that the firmware has correctly set up the memory
346 * controller registers.
349 mpc10x_get_mem_size(uint mem_map
)
351 uint
*config_addr
, *config_data
, val
;
352 ulong start
, end
, total
, offset
;
357 case MPC10X_MEM_MAP_A
:
358 config_addr
= (uint
*)MPC10X_MAPA_CNFG_ADDR
;
359 config_data
= (uint
*)MPC10X_MAPA_CNFG_DATA
;
361 case MPC10X_MEM_MAP_B
:
362 config_addr
= (uint
*)MPC10X_MAPB_CNFG_ADDR
;
363 config_data
= (uint
*)MPC10X_MAPB_CNFG_DATA
;
369 mpc10x_read_config_byte(config_addr
,
372 MPC10X_MCTLR_MEM_BANK_ENABLES
,
377 for (i
=0; i
<8; i
++) {
378 if (bank_enables
& (1 << i
)) {
379 offset
= MPC10X_MCTLR_MEM_START_1
+ ((i
> 3) ? 4 : 0);
380 mpc10x_read_config_dword(config_addr
,
385 start
= (val
>> ((i
& 3) << 3)) & 0xff;
387 offset
= MPC10X_MCTLR_EXT_MEM_START_1
+ ((i
>3) ? 4 : 0);
388 mpc10x_read_config_dword(config_addr
,
393 val
= (val
>> ((i
& 3) << 3)) & 0x03;
394 start
= (val
<< 28) | (start
<< 20);
396 offset
= MPC10X_MCTLR_MEM_END_1
+ ((i
> 3) ? 4 : 0);
397 mpc10x_read_config_dword(config_addr
,
402 end
= (val
>> ((i
& 3) << 3)) & 0xff;
404 offset
= MPC10X_MCTLR_EXT_MEM_END_1
+ ((i
> 3) ? 4 : 0);
405 mpc10x_read_config_dword(config_addr
,
410 val
= (val
>> ((i
& 3) << 3)) & 0x03;
411 end
= (val
<< 28) | (end
<< 20) | 0xfffff;
413 total
+= (end
- start
+ 1);
421 mpc10x_enable_store_gathering(struct pci_controller
*hose
)
425 early_read_config_dword(hose
,
428 MPC10X_CFG_PICR1_REG
,
431 picr1
|= MPC10X_CFG_PICR1_ST_GATH_EN
;
433 early_write_config_dword(hose
,
436 MPC10X_CFG_PICR1_REG
,
443 mpc10x_disable_store_gathering(struct pci_controller
*hose
)
447 early_read_config_dword(hose
,
450 MPC10X_CFG_PICR1_REG
,
453 picr1
&= ~MPC10X_CFG_PICR1_ST_GATH_EN
;
455 early_write_config_dword(hose
,
458 MPC10X_CFG_PICR1_REG
,
464 #ifdef CONFIG_MPC10X_OPENPIC
465 void __init
mpc10x_set_openpic(void)
467 /* Map external IRQs */
468 openpic_set_sources(0, EPIC_IRQ_BASE
, OpenPIC_Addr
+ 0x10200);
469 /* Skip reserved space and map i2c and DMA Ch[01] */
470 openpic_set_sources(EPIC_IRQ_BASE
, 3, OpenPIC_Addr
+ 0x11020);
471 /* Skip reserved space and map Message Unit Interrupt (I2O) */
472 openpic_set_sources(EPIC_IRQ_BASE
+ 3, 1, OpenPIC_Addr
+ 0x110C0);
474 openpic_init(NUM_8259_INTERRUPTS
);