2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
7 * Copyright (C) 1997 Paul Mackerras (paulus@cs.anu.edu.au)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/bootmem.h>
22 #include <asm/sections.h>
25 #include <asm/pci-bridge.h>
26 #include <asm/machdep.h>
27 #include <asm/pmac_feature.h>
33 extern void xmon_printf(const char *fmt
, ...);
34 #define DBG(x...) xmon_printf(x)
36 #define DBG(x...) printk(x)
42 static int add_bridge(struct device_node
*dev
);
43 extern void pmac_check_ht_link(void);
45 /* XXX Could be per-controller, but I don't think we risk anything by
46 * assuming we won't have both UniNorth and Bandit */
47 static int has_uninorth
;
49 static struct pci_controller
*u3_agp
;
50 #endif /* CONFIG_POWER4 */
52 extern u8 pci_cache_line_size
;
53 extern int pcibios_assign_bus_offset
;
55 struct pci_dev
*k2_skiplist
[2];
58 * Magic constants for enabling cache coherency in the bandit/PSX bridge.
60 #define BANDIT_DEVID_2 8
61 #define BANDIT_REVID 3
63 #define BANDIT_DEVNUM 11
64 #define BANDIT_MAGIC 0x50
65 #define BANDIT_COHERENT 0x40
68 fixup_one_level_bus_range(struct device_node
*node
, int higher
)
70 for (; node
!= 0;node
= node
->sibling
) {
72 unsigned int *class_code
;
75 /* For PCI<->PCI bridges or CardBus bridges, we go down */
76 class_code
= (unsigned int *) get_property(node
, "class-code", NULL
);
77 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
78 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
80 bus_range
= (int *) get_property(node
, "bus-range", &len
);
81 if (bus_range
!= NULL
&& len
> 2 * sizeof(int)) {
82 if (bus_range
[1] > higher
)
83 higher
= bus_range
[1];
85 higher
= fixup_one_level_bus_range(node
->child
, higher
);
90 /* This routine fixes the "bus-range" property of all bridges in the
91 * system since they tend to have their "last" member wrong on macs
93 * Note that the bus numbers manipulated here are OF bus numbers, they
94 * are not Linux bus numbers.
97 fixup_bus_range(struct device_node
*bridge
)
102 /* Lookup the "bus-range" property for the hose */
103 bus_range
= (int *) get_property(bridge
, "bus-range", &len
);
104 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
105 printk(KERN_WARNING
"Can't get bus-range for %s\n",
109 bus_range
[1] = fixup_one_level_bus_range(bridge
->child
, bus_range
[1]);
113 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
115 * The "Bandit" version is present in all early PCI PowerMacs,
116 * and up to the first ones using Grackle. Some machines may
117 * have 2 bandit controllers (2 PCI busses).
119 * "Chaos" is used in some "Bandit"-type machines as a bridge
120 * for the separate display bus. It is accessed the same
121 * way as bandit, but cannot be probed for devices. It therefore
122 * has its own config access functions.
124 * The "UniNorth" version is present in all Core99 machines
125 * (iBook, G4, new IMacs, and all the recent Apple machines).
126 * It contains 3 controllers in one ASIC.
128 * The U3 is the bridge used on G5 machines. It contains an
129 * AGP bus which is dealt with the old UniNorth access routines
130 * and a HyperTransport bus which uses its own set of access
134 #define MACRISC_CFA0(devfn, off) \
135 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
136 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
137 | (((unsigned long)(off)) & 0xFCUL))
139 #define MACRISC_CFA1(bus, devfn, off) \
140 ((((unsigned long)(bus)) << 16) \
141 |(((unsigned long)(devfn)) << 8) \
142 |(((unsigned long)(off)) & 0xFCUL) \
145 static unsigned int __pmac
146 macrisc_cfg_access(struct pci_controller
* hose
, u8 bus
, u8 dev_fn
, u8 offset
)
150 if (bus
== hose
->first_busno
) {
151 if (dev_fn
< (11 << 3))
153 caddr
= MACRISC_CFA0(dev_fn
, offset
);
155 caddr
= MACRISC_CFA1(bus
, dev_fn
, offset
);
157 /* Uninorth will return garbage if we don't read back the value ! */
159 out_le32(hose
->cfg_addr
, caddr
);
160 } while (in_le32(hose
->cfg_addr
) != caddr
);
162 offset
&= has_uninorth
? 0x07 : 0x03;
163 return (unsigned int)(hose
->cfg_data
) + (unsigned int)offset
;
167 macrisc_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
170 struct pci_controller
*hose
= bus
->sysdata
;
173 addr
= macrisc_cfg_access(hose
, bus
->number
, devfn
, offset
);
175 return PCIBIOS_DEVICE_NOT_FOUND
;
177 * Note: the caller has already checked that offset is
178 * suitably aligned and that len is 1, 2 or 4.
182 *val
= in_8((u8
*)addr
);
185 *val
= in_le16((u16
*)addr
);
188 *val
= in_le32((u32
*)addr
);
191 return PCIBIOS_SUCCESSFUL
;
195 macrisc_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
198 struct pci_controller
*hose
= bus
->sysdata
;
201 addr
= macrisc_cfg_access(hose
, bus
->number
, devfn
, offset
);
203 return PCIBIOS_DEVICE_NOT_FOUND
;
205 * Note: the caller has already checked that offset is
206 * suitably aligned and that len is 1, 2 or 4.
210 out_8((u8
*)addr
, val
);
211 (void) in_8((u8
*)addr
);
214 out_le16((u16
*)addr
, val
);
215 (void) in_le16((u16
*)addr
);
218 out_le32((u32
*)addr
, val
);
219 (void) in_le32((u32
*)addr
);
222 return PCIBIOS_SUCCESSFUL
;
225 static struct pci_ops macrisc_pci_ops
=
232 * Verifiy that a specific (bus, dev_fn) exists on chaos
235 chaos_validate_dev(struct pci_bus
*bus
, int devfn
, int offset
)
237 struct device_node
*np
;
238 u32
*vendor
, *device
;
240 np
= pci_busdev_to_OF_node(bus
, devfn
);
242 return PCIBIOS_DEVICE_NOT_FOUND
;
244 vendor
= (u32
*)get_property(np
, "vendor-id", NULL
);
245 device
= (u32
*)get_property(np
, "device-id", NULL
);
246 if (vendor
== NULL
|| device
== NULL
)
247 return PCIBIOS_DEVICE_NOT_FOUND
;
249 if ((*vendor
== 0x106b) && (*device
== 3) && (offset
>= 0x10)
250 && (offset
!= 0x14) && (offset
!= 0x18) && (offset
<= 0x24))
251 return PCIBIOS_BAD_REGISTER_NUMBER
;
253 return PCIBIOS_SUCCESSFUL
;
257 chaos_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
260 int result
= chaos_validate_dev(bus
, devfn
, offset
);
261 if (result
== PCIBIOS_BAD_REGISTER_NUMBER
)
263 if (result
!= PCIBIOS_SUCCESSFUL
)
265 return macrisc_read_config(bus
, devfn
, offset
, len
, val
);
269 chaos_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
272 int result
= chaos_validate_dev(bus
, devfn
, offset
);
273 if (result
!= PCIBIOS_SUCCESSFUL
)
275 return macrisc_write_config(bus
, devfn
, offset
, len
, val
);
278 static struct pci_ops chaos_pci_ops
=
287 * These versions of U3 HyperTransport config space access ops do not
288 * implement self-view of the HT host yet
291 #define U3_HT_CFA0(devfn, off) \
292 ((((unsigned long)devfn) << 8) | offset)
293 #define U3_HT_CFA1(bus, devfn, off) \
294 (U3_HT_CFA0(devfn, off) \
295 + (((unsigned long)bus) << 16) \
298 static unsigned long __pmac
299 u3_ht_cfg_access(struct pci_controller
* hose
, u8 bus
, u8 devfn
, u8 offset
)
301 if (bus
== hose
->first_busno
) {
302 /* For now, we don't self probe U3 HT bridge */
303 if (PCI_FUNC(devfn
) != 0 || PCI_SLOT(devfn
) > 7 ||
306 return ((unsigned long)hose
->cfg_data
) + U3_HT_CFA0(devfn
, offset
);
308 return ((unsigned long)hose
->cfg_data
) + U3_HT_CFA1(bus
, devfn
, offset
);
312 u3_ht_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
315 struct pci_controller
*hose
= bus
->sysdata
;
319 struct device_node
*np
= pci_busdev_to_OF_node(bus
, devfn
);
321 return PCIBIOS_DEVICE_NOT_FOUND
;
324 * When a device in K2 is powered down, we die on config
325 * cycle accesses. Fix that here.
328 if (k2_skiplist
[i
] && k2_skiplist
[i
]->bus
== bus
&&
329 k2_skiplist
[i
]->devfn
== devfn
) {
334 *val
= 0xffff; break;
336 *val
= 0xfffffffful
; break;
338 return PCIBIOS_SUCCESSFUL
;
341 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
343 return PCIBIOS_DEVICE_NOT_FOUND
;
345 * Note: the caller has already checked that offset is
346 * suitably aligned and that len is 1, 2 or 4.
350 *val
= in_8((u8
*)addr
);
353 *val
= in_le16((u16
*)addr
);
356 *val
= in_le32((u32
*)addr
);
359 return PCIBIOS_SUCCESSFUL
;
363 u3_ht_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
366 struct pci_controller
*hose
= bus
->sysdata
;
370 struct device_node
*np
= pci_busdev_to_OF_node(bus
, devfn
);
372 return PCIBIOS_DEVICE_NOT_FOUND
;
374 * When a device in K2 is powered down, we die on config
375 * cycle accesses. Fix that here.
378 if (k2_skiplist
[i
] && k2_skiplist
[i
]->bus
== bus
&&
379 k2_skiplist
[i
]->devfn
== devfn
)
380 return PCIBIOS_SUCCESSFUL
;
382 addr
= u3_ht_cfg_access(hose
, bus
->number
, devfn
, offset
);
384 return PCIBIOS_DEVICE_NOT_FOUND
;
386 * Note: the caller has already checked that offset is
387 * suitably aligned and that len is 1, 2 or 4.
391 out_8((u8
*)addr
, val
);
392 (void) in_8((u8
*)addr
);
395 out_le16((u16
*)addr
, val
);
396 (void) in_le16((u16
*)addr
);
399 out_le32((u32
*)addr
, val
);
400 (void) in_le32((u32
*)addr
);
403 return PCIBIOS_SUCCESSFUL
;
406 static struct pci_ops u3_ht_pci_ops
=
412 #endif /* CONFIG_POWER4 */
415 * For a bandit bridge, turn on cache coherency if necessary.
416 * N.B. we could clean this up using the hose ops directly.
419 init_bandit(struct pci_controller
*bp
)
421 unsigned int vendev
, magic
;
424 /* read the word at offset 0 in config space for device 11 */
425 out_le32(bp
->cfg_addr
, (1UL << BANDIT_DEVNUM
) + PCI_VENDOR_ID
);
427 vendev
= in_le32((volatile unsigned int *)bp
->cfg_data
);
428 if (vendev
== (PCI_DEVICE_ID_APPLE_BANDIT
<< 16) +
429 PCI_VENDOR_ID_APPLE
) {
430 /* read the revision id */
431 out_le32(bp
->cfg_addr
,
432 (1UL << BANDIT_DEVNUM
) + PCI_REVISION_ID
);
434 rev
= in_8(bp
->cfg_data
);
435 if (rev
!= BANDIT_REVID
)
437 "Unknown revision %d for bandit\n", rev
);
438 } else if (vendev
!= (BANDIT_DEVID_2
<< 16) + PCI_VENDOR_ID_APPLE
) {
439 printk(KERN_WARNING
"bandit isn't? (%x)\n", vendev
);
443 /* read the word at offset 0x50 */
444 out_le32(bp
->cfg_addr
, (1UL << BANDIT_DEVNUM
) + BANDIT_MAGIC
);
446 magic
= in_le32((volatile unsigned int *)bp
->cfg_data
);
447 if ((magic
& BANDIT_COHERENT
) != 0)
449 magic
|= BANDIT_COHERENT
;
451 out_le32((volatile unsigned int *)bp
->cfg_data
, magic
);
452 printk(KERN_INFO
"Cache coherency enabled for bandit/PSX\n");
457 * Tweak the PCI-PCI bridge chip on the blue & white G3s.
462 struct device_node
*p2pbridge
;
463 struct pci_controller
* hose
;
467 /* XXX it would be better here to identify the specific
468 PCI-PCI bridge chip we have. */
469 if ((p2pbridge
= find_devices("pci-bridge")) == 0
470 || p2pbridge
->parent
== NULL
471 || strcmp(p2pbridge
->parent
->name
, "pci") != 0)
473 if (pci_device_from_OF_node(p2pbridge
, &bus
, &devfn
) < 0) {
474 DBG("Can't find PCI infos for PCI<->PCI bridge\n");
477 /* Warning: At this point, we have not yet renumbered all busses.
478 * So we must use OF walking to find out hose
480 hose
= pci_find_hose_for_OF_device(p2pbridge
);
482 DBG("Can't find hose for PCI<->PCI bridge\n");
485 if (early_read_config_word(hose
, bus
, devfn
,
486 PCI_BRIDGE_CONTROL
, &val
) < 0) {
487 printk(KERN_ERR
"init_p2pbridge: couldn't read bridge control\n");
490 val
&= ~PCI_BRIDGE_CTL_MASTER_ABORT
;
491 early_write_config_word(hose
, bus
, devfn
, PCI_BRIDGE_CONTROL
, val
);
495 * Some Apple desktop machines have a NEC PD720100A USB2 controller
496 * on the motherboard. Open Firmware, on these, will disable the
497 * EHCI part of it so it behaves like a pair of OHCI's. This fixup
498 * code re-enables it ;)
503 struct device_node
*nec
;
505 for (nec
= NULL
; (nec
= of_find_node_by_name(nec
, "usb")) != NULL
;) {
506 struct pci_controller
*hose
;
510 prop
= (u32
*)get_property(nec
, "vendor-id", NULL
);
515 prop
= (u32
*)get_property(nec
, "device-id", NULL
);
520 prop
= (u32
*)get_property(nec
, "reg", NULL
);
523 devfn
= (prop
[0] >> 8) & 0xff;
524 bus
= (prop
[0] >> 16) & 0xff;
525 if (PCI_FUNC(devfn
) != 0)
527 hose
= pci_find_hose_for_OF_device(nec
);
530 early_read_config_dword(hose
, bus
, devfn
, 0xe4, &data
);
532 printk("Found NEC PD720100A USB2 chip with disabled EHCI, fixing up...\n");
534 early_write_config_dword(hose
, bus
, devfn
, 0xe4, data
);
535 early_write_config_byte(hose
, bus
, devfn
| 2, PCI_INTERRUPT_LINE
,
542 pmac_find_bridges(void)
544 struct device_node
*np
, *root
;
545 struct device_node
*ht
= NULL
;
547 root
= of_find_node_by_path("/");
549 printk(KERN_CRIT
"pmac_find_bridges: can't find root of device tree\n");
552 for (np
= NULL
; (np
= of_get_next_child(root
, np
)) != NULL
;) {
553 if (np
->name
== NULL
)
555 if (strcmp(np
->name
, "bandit") == 0
556 || strcmp(np
->name
, "chaos") == 0
557 || strcmp(np
->name
, "pci") == 0) {
558 if (add_bridge(np
) == 0)
561 if (strcmp(np
->name
, "ht") == 0) {
568 /* Probe HT last as it relies on the agp resources to be already
571 if (ht
&& add_bridge(ht
) != 0)
577 /* We are still having some issues with the Xserve G4, enabling
578 * some offset between bus number and domains for now when we
579 * assign all busses should help for now
581 if (pci_assign_all_busses
)
582 pcibios_assign_bus_offset
= 0x10;
585 /* There is something wrong with DMA on U3/HT. I haven't figured out
586 * the details yet, but if I set the cache line size to 128 bytes like
587 * it should, I'm getting memory corruption caused by devices like
588 * sungem (even without the MWI bit set, but maybe sungem doesn't
589 * care). Right now, it appears that setting up a 64 bytes line size
590 * works properly, 64 bytes beeing the max transfer size of HT, I
591 * suppose this is related the way HT/PCI are hooked together. I still
592 * need to dive into more specs though to be really sure of what's
595 * Ok, apparently, it's just that HT can't do more than 64 bytes
596 * transactions. MWI seem to be meaningless there as well, it may
597 * be worth nop'ing out pci_set_mwi too though I haven't done that
600 * Note that it's a bit different for whatever is in the AGP slot.
601 * For now, I don't care, but this can become a real issue, we
602 * should probably hook pci_set_mwi anyway to make sure it sets
603 * the real cache line size in there.
605 if (machine_is_compatible("MacRISC4"))
606 pci_cache_line_size
= 16; /* 64 bytes */
608 pmac_check_ht_link();
609 #endif /* CONFIG_POWER4 */
612 #define GRACKLE_CFA(b, d, o) (0x80 | ((b) << 8) | ((d) << 16) \
613 | (((o) & ~3) << 24))
615 #define GRACKLE_PICR1_STG 0x00000040
616 #define GRACKLE_PICR1_LOOPSNOOP 0x00000010
618 /* N.B. this is called before bridges is initialized, so we can't
619 use grackle_pcibios_{read,write}_config_dword. */
620 static inline void grackle_set_stg(struct pci_controller
* bp
, int enable
)
624 out_be32(bp
->cfg_addr
, GRACKLE_CFA(0, 0, 0xa8));
625 val
= in_le32((volatile unsigned int *)bp
->cfg_data
);
626 val
= enable
? (val
| GRACKLE_PICR1_STG
) :
627 (val
& ~GRACKLE_PICR1_STG
);
628 out_be32(bp
->cfg_addr
, GRACKLE_CFA(0, 0, 0xa8));
629 out_le32((volatile unsigned int *)bp
->cfg_data
, val
);
630 (void)in_le32((volatile unsigned int *)bp
->cfg_data
);
633 static inline void grackle_set_loop_snoop(struct pci_controller
*bp
, int enable
)
637 out_be32(bp
->cfg_addr
, GRACKLE_CFA(0, 0, 0xa8));
638 val
= in_le32((volatile unsigned int *)bp
->cfg_data
);
639 val
= enable
? (val
| GRACKLE_PICR1_LOOPSNOOP
) :
640 (val
& ~GRACKLE_PICR1_LOOPSNOOP
);
641 out_be32(bp
->cfg_addr
, GRACKLE_CFA(0, 0, 0xa8));
642 out_le32((volatile unsigned int *)bp
->cfg_data
, val
);
643 (void)in_le32((volatile unsigned int *)bp
->cfg_data
);
647 setup_uninorth(struct pci_controller
* hose
, struct reg_property
* addr
)
649 pci_assign_all_busses
= 1;
651 hose
->ops
= ¯isc_pci_ops
;
652 hose
->cfg_addr
= ioremap(addr
->address
+ 0x800000, 0x1000);
653 hose
->cfg_data
= ioremap(addr
->address
+ 0xc00000, 0x1000);
654 /* We "know" that the bridge at f2000000 has the PCI slots. */
655 return addr
->address
== 0xf2000000;
659 setup_bandit(struct pci_controller
* hose
, struct reg_property
* addr
)
661 hose
->ops
= ¯isc_pci_ops
;
662 hose
->cfg_addr
= (volatile unsigned int *)
663 ioremap(addr
->address
+ 0x800000, 0x1000);
664 hose
->cfg_data
= (volatile unsigned char *)
665 ioremap(addr
->address
+ 0xc00000, 0x1000);
670 setup_chaos(struct pci_controller
* hose
, struct reg_property
* addr
)
672 /* assume a `chaos' bridge */
673 hose
->ops
= &chaos_pci_ops
;
674 hose
->cfg_addr
= (volatile unsigned int *)
675 ioremap(addr
->address
+ 0x800000, 0x1000);
676 hose
->cfg_data
= (volatile unsigned char *)
677 ioremap(addr
->address
+ 0xc00000, 0x1000);
683 setup_u3_agp(struct pci_controller
* hose
, struct reg_property
* addr
)
685 /* On G5, we move AGP up to high bus number so we don't need
686 * to reassign bus numbers for HT. If we ever have P2P bridges
687 * on AGP, we'll have to move pci_assign_all_busses to the
688 * pci_controller structure so we enable it for AGP and not for
690 * We hard code the address because of the different size of
691 * the reg address cell, we shall fix that by killing struct
692 * reg_property and using some accessor functions instead
694 hose
->first_busno
= 0xf0;
695 hose
->last_busno
= 0xff;
697 hose
->ops
= ¯isc_pci_ops
;
698 hose
->cfg_addr
= ioremap(0xf0000000 + 0x800000, 0x1000);
699 hose
->cfg_data
= ioremap(0xf0000000 + 0xc00000, 0x1000);
705 setup_u3_ht(struct pci_controller
* hose
, struct reg_property
*addr
)
707 struct device_node
*np
= (struct device_node
*)hose
->arch_data
;
710 hose
->ops
= &u3_ht_pci_ops
;
712 /* We hard code the address because of the different size of
713 * the reg address cell, we shall fix that by killing struct
714 * reg_property and using some accessor functions instead
716 hose
->cfg_data
= (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
719 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
720 * have been allocated to AGP. So far, this version of the code doesn't assign
721 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
722 * We need to fix that sooner or later by either parsing all child "ranges"
723 * properties or figuring out the U3 address space decoding logic and
724 * then read its configuration register (if any).
726 hose
->io_base_phys
= 0xf4000000;
727 hose
->io_base_virt
= ioremap(hose
->io_base_phys
, 0x00400000);
728 isa_io_base
= (unsigned long) hose
->io_base_virt
;
729 hose
->io_resource
.name
= np
->full_name
;
730 hose
->io_resource
.start
= 0;
731 hose
->io_resource
.end
= 0x003fffff;
732 hose
->io_resource
.flags
= IORESOURCE_IO
;
733 hose
->pci_mem_offset
= 0;
734 hose
->first_busno
= 0;
735 hose
->last_busno
= 0xef;
736 hose
->mem_resources
[0].name
= np
->full_name
;
737 hose
->mem_resources
[0].start
= 0x80000000;
738 hose
->mem_resources
[0].end
= 0xefffffff;
739 hose
->mem_resources
[0].flags
= IORESOURCE_MEM
;
741 if (u3_agp
== NULL
) {
742 DBG("U3 has no AGP, using full resource range\n");
746 /* We "remove" the AGP resources from the resources allocated to HT, that
747 * is we create "holes". However, that code does assumptions that so far
748 * happen to be true (cross fingers...), typically that resources in the
749 * AGP node are properly ordered
752 for (i
=0; i
<3; i
++) {
753 struct resource
*res
= &u3_agp
->mem_resources
[i
];
754 if (res
->flags
!= IORESOURCE_MEM
)
756 /* We don't care about "fine" resources */
757 if (res
->start
>= 0xf0000000)
759 /* Check if it's just a matter of "shrinking" us in one direction */
760 if (hose
->mem_resources
[cur
].start
== res
->start
) {
761 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
762 cur
, hose
->mem_resources
[cur
].start
, res
->end
+ 1);
763 hose
->mem_resources
[cur
].start
= res
->end
+ 1;
766 if (hose
->mem_resources
[cur
].end
== res
->end
) {
767 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
768 cur
, hose
->mem_resources
[cur
].end
, res
->start
- 1);
769 hose
->mem_resources
[cur
].end
= res
->start
- 1;
772 /* No, it's not the case, we need a hole */
774 /* not enough resources to make a hole, we drop part of the range */
775 printk(KERN_WARNING
"Running out of resources for /ht host !\n");
776 hose
->mem_resources
[cur
].end
= res
->start
- 1;
780 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
781 cur
-1, res
->start
- 1, cur
, res
->end
+ 1);
782 hose
->mem_resources
[cur
].name
= np
->full_name
;
783 hose
->mem_resources
[cur
].flags
= IORESOURCE_MEM
;
784 hose
->mem_resources
[cur
].start
= res
->end
+ 1;
785 hose
->mem_resources
[cur
].end
= hose
->mem_resources
[cur
-1].end
;
786 hose
->mem_resources
[cur
-1].end
= res
->start
- 1;
790 #endif /* CONFIG_POWER4 */
793 setup_grackle(struct pci_controller
*hose
)
795 setup_indirect_pci(hose
, 0xfec00000, 0xfee00000);
796 if (machine_is_compatible("AAPL,PowerBook1998"))
797 grackle_set_loop_snoop(hose
, 1);
798 #if 0 /* Disabled for now, HW problems ??? */
799 grackle_set_stg(hose
, 1);
804 * We assume that if we have a G3 powermac, we have one bridge called
805 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
806 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
809 add_bridge(struct device_node
*dev
)
812 struct pci_controller
*hose
;
813 struct reg_property
*addr
;
818 DBG("Adding PCI host bridge %s\n", dev
->full_name
);
820 addr
= (struct reg_property
*) get_property(dev
, "reg", &len
);
821 if (addr
== NULL
|| len
< sizeof(*addr
)) {
822 printk(KERN_WARNING
"Can't use %s: no address\n",
826 bus_range
= (int *) get_property(dev
, "bus-range", &len
);
827 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
828 printk(KERN_WARNING
"Can't get bus-range for %s, assume bus 0\n",
832 hose
= pcibios_alloc_controller();
835 hose
->arch_data
= dev
;
836 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
837 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
841 if (device_is_compatible(dev
, "u3-agp")) {
842 setup_u3_agp(hose
, addr
);
843 disp_name
= "U3-AGP";
845 } else if (device_is_compatible(dev
, "u3-ht")) {
846 setup_u3_ht(hose
, addr
);
850 #endif /* CONFIG_POWER4 */
851 if (device_is_compatible(dev
, "uni-north")) {
852 primary
= setup_uninorth(hose
, addr
);
853 disp_name
= "UniNorth";
854 } else if (strcmp(dev
->name
, "pci") == 0) {
855 /* XXX assume this is a mpc106 (grackle) */
857 disp_name
= "Grackle (MPC106)";
858 } else if (strcmp(dev
->name
, "bandit") == 0) {
859 setup_bandit(hose
, addr
);
860 disp_name
= "Bandit";
861 } else if (strcmp(dev
->name
, "chaos") == 0) {
862 setup_chaos(hose
, addr
);
866 printk(KERN_INFO
"Found %s PCI host bridge at 0x%08x. Firmware bus number: %d->%d\n",
867 disp_name
, addr
->address
, hose
->first_busno
, hose
->last_busno
);
868 DBG(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
869 hose
, hose
->cfg_addr
, hose
->cfg_data
);
871 /* Interpret the "ranges" property */
872 /* This also maps the I/O region and sets isa_io/mem_base */
873 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
875 /* Fixup "bus-range" OF property */
876 fixup_bus_range(dev
);
882 pcibios_fixup_OF_interrupts(void)
884 struct pci_dev
* dev
= NULL
;
887 * Open Firmware often doesn't initialize the
888 * PCI_INTERRUPT_LINE config register properly, so we
889 * should find the device node and apply the interrupt
890 * obtained from the OF device-tree
892 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
893 struct device_node
*node
;
894 node
= pci_device_to_OF_node(dev
);
895 /* this is the node, see if it has interrupts */
896 if (node
&& node
->n_intrs
> 0)
897 dev
->irq
= node
->intrs
[0].line
;
898 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, dev
->irq
);
903 pmac_pcibios_fixup(void)
905 /* Fixup interrupts according to OF tree */
906 pcibios_fixup_OF_interrupts();
910 pmac_pci_enable_device_hook(struct pci_dev
*dev
, int initial
)
912 struct device_node
* node
;
916 node
= pci_device_to_OF_node(dev
);
918 /* We don't want to enable USB controllers absent from the OF tree
919 * (iBook second controller)
921 if (dev
->vendor
== PCI_VENDOR_ID_APPLE
922 && dev
->device
== PCI_DEVICE_ID_APPLE_KL_USB
&& !node
)
928 uninorth_child
= node
->parent
&&
929 device_is_compatible(node
->parent
, "uni-north");
931 /* Firewire & GMAC were disabled after PCI probe, the driver is
932 * claiming them, we must re-enable them now.
934 if (uninorth_child
&& !strcmp(node
->name
, "firewire") &&
935 (device_is_compatible(node
, "pci106b,18") ||
936 device_is_compatible(node
, "pci106b,30") ||
937 device_is_compatible(node
, "pci11c1,5811"))) {
938 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, node
, 0, 1);
939 pmac_call_feature(PMAC_FTR_1394_ENABLE
, node
, 0, 1);
942 if (uninorth_child
&& !strcmp(node
->name
, "ethernet") &&
943 device_is_compatible(node
, "gmac")) {
944 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, node
, 0, 1);
952 * Make sure PCI is correctly configured
954 * We use old pci_bios versions of the function since, by
955 * default, gmac is not powered up, and so will be absent
956 * from the kernel initial PCI lookup.
958 * Should be replaced by 2.4 new PCI mechanisms and really
959 * register the device.
961 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
962 cmd
|= PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
| PCI_COMMAND_INVALIDATE
;
963 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
964 pci_write_config_byte(dev
, PCI_LATENCY_TIMER
, 16);
965 pci_write_config_byte(dev
, PCI_CACHE_LINE_SIZE
, pci_cache_line_size
);
971 /* We power down some devices after they have been probed. They'll
972 * be powered back on later on
975 pmac_pcibios_after_init(void)
977 struct device_node
* nd
;
979 #ifdef CONFIG_BLK_DEV_IDE
980 struct pci_dev
*dev
= NULL
;
982 /* OF fails to initialize IDE controllers on macs
983 * (and maybe other machines)
985 * Ideally, this should be moved to the IDE layer, but we need
986 * to check specifically with Andre Hedrick how to do it cleanly
987 * since the common IDE code seem to care about the fact that the
988 * BIOS may have disabled a controller.
992 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
993 if ((dev
->class >> 16) == PCI_BASE_CLASS_STORAGE
)
994 pci_enable_device(dev
);
996 #endif /* CONFIG_BLK_DEV_IDE */
998 nd
= find_devices("firewire");
1000 if (nd
->parent
&& (device_is_compatible(nd
, "pci106b,18") ||
1001 device_is_compatible(nd
, "pci106b,30") ||
1002 device_is_compatible(nd
, "pci11c1,5811"))
1003 && device_is_compatible(nd
->parent
, "uni-north")) {
1004 pmac_call_feature(PMAC_FTR_1394_ENABLE
, nd
, 0, 0);
1005 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER
, nd
, 0, 0);
1009 nd
= find_devices("ethernet");
1011 if (nd
->parent
&& device_is_compatible(nd
, "gmac")
1012 && device_is_compatible(nd
->parent
, "uni-north"))
1013 pmac_call_feature(PMAC_FTR_GMAC_ENABLE
, nd
, 0, 0);
1018 void pmac_pci_fixup_cardbus(struct pci_dev
* dev
)
1020 if (_machine
!= _MACH_Pmac
)
1023 * Fix the interrupt routing on the various cardbus bridges
1024 * used on powerbooks
1026 if (dev
->vendor
!= PCI_VENDOR_ID_TI
)
1028 if (dev
->device
== PCI_DEVICE_ID_TI_1130
||
1029 dev
->device
== PCI_DEVICE_ID_TI_1131
) {
1031 /* Enable PCI interrupt */
1032 if (pci_read_config_byte(dev
, 0x91, &val
) == 0)
1033 pci_write_config_byte(dev
, 0x91, val
| 0x30);
1034 /* Disable ISA interrupt mode */
1035 if (pci_read_config_byte(dev
, 0x92, &val
) == 0)
1036 pci_write_config_byte(dev
, 0x92, val
& ~0x06);
1038 if (dev
->device
== PCI_DEVICE_ID_TI_1210
||
1039 dev
->device
== PCI_DEVICE_ID_TI_1211
||
1040 dev
->device
== PCI_DEVICE_ID_TI_1410
||
1041 dev
->device
== PCI_DEVICE_ID_TI_1510
) {
1043 /* 0x8c == TI122X_IRQMUX, 2 says to route the INTA
1044 signal out the MFUNC0 pin */
1045 if (pci_read_config_byte(dev
, 0x8c, &val
) == 0)
1046 pci_write_config_byte(dev
, 0x8c, (val
& ~0x0f) | 2);
1047 /* Disable ISA interrupt mode */
1048 if (pci_read_config_byte(dev
, 0x92, &val
) == 0)
1049 pci_write_config_byte(dev
, 0x92, val
& ~0x06);
1053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI
, PCI_ANY_ID
, pmac_pci_fixup_cardbus
);
1055 void pmac_pci_fixup_pciata(struct pci_dev
* dev
)
1060 * On PowerMacs, we try to switch any PCI ATA controller to
1063 if (_machine
!= _MACH_Pmac
)
1065 /* Some controllers don't have the class IDE */
1066 if (dev
->vendor
== PCI_VENDOR_ID_PROMISE
)
1067 switch(dev
->device
) {
1068 case PCI_DEVICE_ID_PROMISE_20246
:
1069 case PCI_DEVICE_ID_PROMISE_20262
:
1070 case PCI_DEVICE_ID_PROMISE_20263
:
1071 case PCI_DEVICE_ID_PROMISE_20265
:
1072 case PCI_DEVICE_ID_PROMISE_20267
:
1073 case PCI_DEVICE_ID_PROMISE_20268
:
1074 case PCI_DEVICE_ID_PROMISE_20269
:
1075 case PCI_DEVICE_ID_PROMISE_20270
:
1076 case PCI_DEVICE_ID_PROMISE_20271
:
1077 case PCI_DEVICE_ID_PROMISE_20275
:
1078 case PCI_DEVICE_ID_PROMISE_20276
:
1079 case PCI_DEVICE_ID_PROMISE_20277
:
1082 /* Others, check PCI class */
1083 if ((dev
->class >> 8) != PCI_CLASS_STORAGE_IDE
)
1086 pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
);
1087 if ((progif
& 5) != 5) {
1088 printk(KERN_INFO
"Forcing PCI IDE into native mode: %s\n", pci_name(dev
));
1089 (void) pci_write_config_byte(dev
, PCI_CLASS_PROG
, progif
|5);
1090 if (pci_read_config_byte(dev
, PCI_CLASS_PROG
, &progif
) ||
1092 printk(KERN_ERR
"Rewrite of PROGIF failed !\n");
1095 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID
, PCI_ANY_ID
, pmac_pci_fixup_pciata
);
1099 * Disable second function on K2-SATA, it's broken
1100 * and disable IO BARs on first one
1102 void __pmac
pmac_pci_fixup_k2_sata(struct pci_dev
* dev
)
1107 if (PCI_FUNC(dev
->devfn
) > 0) {
1108 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1109 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
);
1110 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1111 for (i
= 0; i
< 6; i
++) {
1112 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
1113 dev
->resource
[i
].flags
= 0;
1114 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4 * i
, 0);
1117 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1118 cmd
&= ~PCI_COMMAND_IO
;
1119 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1120 for (i
= 0; i
< 5; i
++) {
1121 dev
->resource
[i
].start
= dev
->resource
[i
].end
= 0;
1122 dev
->resource
[i
].flags
= 0;
1123 pci_write_config_dword(dev
, PCI_BASE_ADDRESS_0
+ 4 * i
, 0);
1127 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS
, 0x0240, pmac_pci_fixup_k2_sata
);