arch/ppc/platforms/chrp_pci.c

   1 /*
   2  * CHRP pci routines.
   3  */
   4
   5 #include <linux/config.h>
   6 #include <linux/kernel.h>
   7 #include <linux/pci.h>
   8 #include <linux/delay.h>
   9 #include <linux/string.h>
  10 #include <linux/init.h>
  11 #include <linux/ide.h>
  12 #include <linux/bootmem.h>
  13
  14 #include <asm/io.h>
  15 #include <asm/pgtable.h>
  16 #include <asm/irq.h>
  17 #include <asm/hydra.h>
  18 #include <asm/prom.h>
  19 #include <asm/gg2.h>
  20 #include <asm/machdep.h>
  21 #include <asm/sections.h>
  22 #include <asm/pci-bridge.h>
  23 #include <asm/open_pic.h>
  24
  25 /* LongTrail */
  26 unsigned long gg2_pci_config_base;
  27
  28 /*
  29  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
  30  * limit the bus number to 3 bits
  31  */
  32
  33 int __chrp gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
  34                            int len, u32 *val)
  35 {
  36         volatile unsigned char *cfg_data;
  37         struct pci_controller *hose = bus->sysdata;
  38
  39         if (bus->number > 7)
  40                 return PCIBIOS_DEVICE_NOT_FOUND;
  41         /*
  42          * Note: the caller has already checked that off is
  43          * suitably aligned and that len is 1, 2 or 4.
  44          */
  45         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
  46         switch (len) {
  47         case 1:
  48                 *val =  in_8((u8 *)cfg_data);
  49                 break;
  50         case 2:
  51                 *val = in_le16((u16 *)cfg_data);
  52                 break;
  53         default:
  54                 *val = in_le32((u32 *)cfg_data);
  55                 break;
  56         }
  57         return PCIBIOS_SUCCESSFUL;
  58 }
  59
  60 int __chrp gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
  61                             int len, u32 val)
  62 {
  63         volatile unsigned char *cfg_data;
  64         struct pci_controller *hose = bus->sysdata;
  65
  66         if (bus->number > 7)
  67                 return PCIBIOS_DEVICE_NOT_FOUND;
  68         /*
  69          * Note: the caller has already checked that off is
  70          * suitably aligned and that len is 1, 2 or 4.
  71          */
  72         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
  73         switch (len) {
  74         case 1:
  75                 out_8((u8 *)cfg_data, val);
  76                 break;
  77         case 2:
  78                 out_le16((u16 *)cfg_data, val);
  79                 break;
  80         default:
  81                 out_le32((u32 *)cfg_data, val);
  82                 break;
  83         }
  84         return PCIBIOS_SUCCESSFUL;
  85 }
  86
  87 static struct pci_ops gg2_pci_ops =
  88 {
  89         gg2_read_config,
  90         gg2_write_config
  91 };
  92
  93 /*
  94  * Access functions for PCI config space using RTAS calls.
  95  */
  96 int __chrp
  97 rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
  98                  int len, u32 *val)
  99 {
 100         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
 101                 | ((bus->number & 0xff) << 16);
 102         unsigned long ret = ~0UL;
 103         int rval;
 104
 105         rval = call_rtas("read-pci-config", 2, 2, &ret, addr, len);
 106         *val = ret;
 107         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
 108 }
 109
 110 int __chrp
 111 rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
 112                   int len, u32 val)
 113 {
 114         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
 115                 | ((bus->number & 0xff) << 16);
 116         int rval;
 117
 118         rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
 119         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
 120 }
 121
 122 static struct pci_ops rtas_pci_ops =
 123 {
 124         rtas_read_config,
 125         rtas_write_config
 126 };
 127
 128 volatile struct Hydra *Hydra = NULL;
 129
 130 int __init
 131 hydra_init(void)
 132 {
 133         struct device_node *np;
 134
 135         np = find_devices("mac-io");
 136         if (np == NULL || np->n_addrs == 0)
 137                 return 0;
 138         Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
 139         printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
 140         printk("Hydra Feature_Control was %x",
 141                in_le32(&Hydra->Feature_Control));
 142         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
 143                                            HYDRA_FC_SCSI_CELL_EN |
 144                                            HYDRA_FC_SCCA_ENABLE |
 145                                            HYDRA_FC_SCCB_ENABLE |
 146                                            HYDRA_FC_ARB_BYPASS |
 147                                            HYDRA_FC_MPIC_ENABLE |
 148                                            HYDRA_FC_SLOW_SCC_PCLK |
 149                                            HYDRA_FC_MPIC_IS_MASTER));
 150         printk(", now %x\n", in_le32(&Hydra->Feature_Control));
 151         return 1;
 152 }
 153
 154 void __init
 155 chrp_pcibios_fixup(void)
 156 {
 157         struct pci_dev *dev = NULL;
 158         struct device_node *np;
 159
 160         /* PCI interrupts are controlled by the OpenPIC */
 161         while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) {
 162                 np = pci_device_to_OF_node(dev);
 163                 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
 164                         dev->irq = np->intrs[0].line;
 165                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 166         }
 167 }
 168
 169 #define PRG_CL_RESET_VALID 0x00010000
 170
 171 static void __init
 172 setup_python(struct pci_controller *hose, struct device_node *dev)
 173 {
 174         u32 *reg, val;
 175         unsigned long addr = dev->addrs[0].address;
 176
 177         setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
 178
 179         /* Clear the magic go-slow bit */
 180         reg = (u32 *) ioremap(dev->addrs[0].address + 0xf6000, 0x40);
 181         val = in_be32(&reg[12]);
 182         if (val & PRG_CL_RESET_VALID) {
 183                 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
 184                 in_be32(&reg[12]);
 185         }
 186         iounmap(reg);
 187 }
 188
 189 void __init
 190 chrp_find_bridges(void)
 191 {
 192         struct device_node *dev;
 193         int *bus_range;
 194         int len, index = -1;
 195         struct pci_controller *hose;
 196         unsigned int *dma;
 197         char *model, *machine;
 198         int is_longtrail = 0, is_mot = 0;
 199         struct device_node *root = find_path_device("/");
 200
 201         /*
 202          * The PCI host bridge nodes on some machines don't have
 203          * properties to adequately identify them, so we have to
 204          * look at what sort of machine this is as well.
 205          */
 206         machine = get_property(root, "model", NULL);
 207         if (machine != NULL) {
 208                 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
 209                 is_mot = strncmp(machine, "MOT", 3) == 0;
 210         }
 211         for (dev = root->child; dev != NULL; dev = dev->sibling) {
 212                 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
 213                         continue;
 214                 ++index;
 215                 /* The GG2 bridge on the LongTrail doesn't have an address */
 216                 if (dev->n_addrs < 1 && !is_longtrail) {
 217                         printk(KERN_WARNING "Can't use %s: no address\n",
 218                                dev->full_name);
 219                         continue;
 220                 }
 221                 bus_range = (int *) get_property(dev, "bus-range", &len);
 222                 if (bus_range == NULL || len < 2 * sizeof(int)) {
 223                         printk(KERN_WARNING "Can't get bus-range for %s\n",
 224                                 dev->full_name);
 225                         continue;
 226                 }
 227                 if (bus_range[1] == bus_range[0])
 228                         printk(KERN_INFO "PCI bus %d", bus_range[0]);
 229                 else
 230                         printk(KERN_INFO "PCI buses %d..%d",
 231                                bus_range[0], bus_range[1]);
 232                 printk(" controlled by %s", dev->type);
 233                 if (dev->n_addrs > 0)
 234                         printk(" at %x", dev->addrs[0].address);
 235                 printk("\n");
 236
 237                 hose = pcibios_alloc_controller();
 238                 if (!hose) {
 239                         printk("Can't allocate PCI controller structure for %s\n",
 240                                 dev->full_name);
 241                         continue;
 242                 }
 243                 hose->arch_data = dev;
 244                 hose->first_busno = bus_range[0];
 245                 hose->last_busno = bus_range[1];
 246
 247                 model = get_property(dev, "model", NULL);
 248                 if (model == NULL)
 249                         model = "<none>";
 250                 if (device_is_compatible(dev, "IBM,python")) {
 251                         setup_python(hose, dev);
 252                 } else if (is_mot
 253                            || strncmp(model, "Motorola, Grackle", 17) == 0) {
 254                         setup_grackle(hose);
 255                 } else if (is_longtrail) {
 256                         hose->ops = &gg2_pci_ops;
 257                         hose->cfg_data = (unsigned char *)
 258                                 ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
 259                         gg2_pci_config_base = (unsigned long) hose->cfg_data;
 260                 } else {
 261                         printk("No methods for %s (model %s), using RTAS\n",
 262                                dev->full_name, model);
 263                         hose->ops = &rtas_pci_ops;
 264                 }
 265
 266                 pci_process_bridge_OF_ranges(hose, dev, index == 0);
 267
 268                 /* check the first bridge for a property that we can
 269                    use to set pci_dram_offset */
 270                 dma = (unsigned int *)
 271                         get_property(dev, "ibm,dma-ranges", &len);
 272                 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
 273                         pci_dram_offset = dma[2] - dma[3];
 274                         printk("pci_dram_offset = %lx\n", pci_dram_offset);
 275                 }
 276         }
 277
 278         ppc_md.pcibios_fixup = chrp_pcibios_fixup;
 279 }