arch/ppc/platforms/85xx/mpc85xx_ads_common.c

   1 /*
   2  * arch/ppc/platforms/85xx/mpc85xx_ads_common.c
   3  *
   4  * MPC85xx ADS board common routines
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/stddef.h>
  18 #include <linux/kernel.h>
  19 #include <linux/init.h>
  20 #include <linux/errno.h>
  21 #include <linux/reboot.h>
  22 #include <linux/pci.h>
  23 #include <linux/kdev_t.h>
  24 #include <linux/major.h>
  25 #include <linux/console.h>
  26 #include <linux/delay.h>
  27 #include <linux/irq.h>
  28 #include <linux/seq_file.h>
  29 #include <linux/serial.h>
  30 #include <linux/module.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/page.h>
  35 #include <asm/atomic.h>
  36 #include <asm/time.h>
  37 #include <asm/io.h>
  38 #include <asm/machdep.h>
  39 #include <asm/prom.h>
  40 #include <asm/open_pic.h>
  41 #include <asm/bootinfo.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/mpc85xx.h>
  44 #include <asm/irq.h>
  45 #include <asm/immap_85xx.h>
  46 #include <asm/ocp.h>
  47
  48 #include <mm/mmu_decl.h>
  49
  50 #include <platforms/85xx/mpc85xx_ads_common.h>
  51
  52 #ifndef CONFIG_PCI
  53 unsigned long isa_io_base = 0;
  54 unsigned long isa_mem_base = 0;
  55 #endif
  56
  57 extern unsigned long total_memory;      /* in mm/init */
  58
  59 unsigned char __res[sizeof (bd_t)];
  60
  61 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  62
  63 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  0: L2 Cache */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  1: ECM */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  2: DDR DRAM */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  3: LBIU */
  68         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  4: DMA 0 */
  69         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  5: DMA 1 */
  70         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  6: DMA 2 */
  71         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  7: DMA 3 */
  72         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  8: PCI/PCI-X */
  73         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal  9: RIO Inbound Port Write Error */
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 10: RIO Doorbell Inbound */
  75         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 11: RIO Outbound Message */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 12: RIO Inbound Message */
  77         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 13: TSEC 0 Transmit */
  78         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 14: TSEC 0 Receive */
  79         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 15: Unused */
  80         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 16: Unused */
  81         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 17: Unused */
  82         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 18: TSEC 0 Receive/Transmit Error */
  83         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 19: TSEC 1 Transmit */
  84         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 20: TSEC 1 Receive */
  85         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 21: Unused */
  86         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 22: Unused */
  87         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 23: Unused */
  88         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 24: TSEC 1 Receive/Transmit Error */
  89         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 25: Fast Ethernet */
  90         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 26: DUART */
  91         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 27: I2C */
  92         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 28: Performance Monitor */
  93         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 29: Unused */
  94         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 30: CPM */
  95         (IRQ_SENSE_LEVEL | IRQ_POLARITY_POSITIVE),      /* Internal 31: Unused */
  96         0x0,                                            /* External  0: */
  97 #if defined(CONFIG_PCI)
  98         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
  99         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
 100         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
 101         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
 102 #else
 103         0x0,                            /* External  1: */
 104         0x0,                            /* External  2: */
 105         0x0,                            /* External  3: */
 106         0x0,                            /* External  4: */
 107 #endif
 108         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 5: PHY */
 109         0x0,                            /* External  6: */
 110         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 7: PHY */
 111         0x0,                            /* External  8: */
 112         0x0,                            /* External  9: */
 113         0x0,                            /* External 10: */
 114         0x0,                            /* External 11: */
 115 };
 116
 117 /* ************************************************************************ */
 118 int
 119 mpc85xx_ads_show_cpuinfo(struct seq_file *m)
 120 {
 121         uint pvid, svid, phid1;
 122         uint memsize = total_memory;
 123         bd_t *binfo = (bd_t *) __res;
 124         unsigned int freq;
 125
 126         /* get the core frequency */
 127         freq = binfo->bi_intfreq;
 128
 129         pvid = mfspr(PVR);
 130         svid = mfspr(SVR);
 131
 132         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
 133
 134         switch (svid & 0xffff0000) {
 135         case SVR_8540:
 136                 seq_printf(m, "Machine\t\t: mpc8540ads\n");
 137                 break;
 138         case SVR_8560:
 139                 seq_printf(m, "Machine\t\t: mpc8560ads\n");
 140                 break;
 141         default:
 142                 seq_printf(m, "Machine\t\t: unknown\n");
 143                 break;
 144         }
 145         seq_printf(m, "bus freq\t: %u.%.6u MHz\n", freq / 1000000,
 146                    freq % 1000000);
 147         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 148         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 149
 150         /* Display cpu Pll setting */
 151         phid1 = mfspr(HID1);
 152         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 153
 154         /* Display the amount of memory */
 155         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 156
 157         return 0;
 158 }
 159
 160 void __init
 161 mpc85xx_ads_init_IRQ(void)
 162 {
 163         bd_t *binfo = (bd_t *) __res;
 164         /* Determine the Physical Address of the OpenPIC regs */
 165         phys_addr_t OpenPIC_PAddr =
 166             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 167         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 168         OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
 169         OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
 170
 171         /* Skip reserved space and internal sources */
 172         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 173         /* Map PIC IRQs 0-11 */
 174         openpic_set_sources(32, 12, OpenPIC_Addr + 0x10000);
 175
 176         /* we let openpic interrupts starting from an offset, to
 177          * leave space for cascading interrupts underneath.
 178          */
 179         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 180
 181         return;
 182 }
 183
 184 #ifdef CONFIG_PCI
 185 /*
 186  * interrupt routing
 187  */
 188
 189 int
 190 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 191 {
 192         static char pci_irq_table[][4] =
 193             /*
 194              * This is little evil, but works around the fact
 195              * that revA boards have IDSEL starting at 18
 196              * and others boards (older) start at 12
 197              *
 198              *      PCI IDSEL/INTPIN->INTLINE
 199              *       A      B      C      D
 200              */
 201         {
 202                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 2 */
 203                 {PIRQD, PIRQA, PIRQB, PIRQC},
 204                 {PIRQC, PIRQD, PIRQA, PIRQB},
 205                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 5 */
 206                 {0, 0, 0, 0},   /* -- */
 207                 {0, 0, 0, 0},   /* -- */
 208                 {0, 0, 0, 0},   /* -- */
 209                 {0, 0, 0, 0},   /* -- */
 210                 {0, 0, 0, 0},   /* -- */
 211                 {0, 0, 0, 0},   /* -- */
 212                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 12 */
 213                 {PIRQD, PIRQA, PIRQB, PIRQC},
 214                 {PIRQC, PIRQD, PIRQA, PIRQB},
 215                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 15 */
 216                 {0, 0, 0, 0},   /* -- */
 217                 {0, 0, 0, 0},   /* -- */
 218                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 18 */
 219                 {PIRQD, PIRQA, PIRQB, PIRQC},
 220                 {PIRQC, PIRQD, PIRQA, PIRQB},
 221                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 21 */
 222         };
 223
 224         const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
 225         return PCI_IRQ_TABLE_LOOKUP;
 226 }
 227
 228 int
 229 mpc85xx_exclude_device(u_char bus, u_char devfn)
 230 {
 231         if (bus == 0 && PCI_SLOT(devfn) == 0)
 232                 return PCIBIOS_DEVICE_NOT_FOUND;
 233         else
 234                 return PCIBIOS_SUCCESSFUL;
 235 }
 236
 237 #endif /* CONFIG_PCI */