2 * Common pmac/prep/chrp pci routines. -- Cort
5 #include <linux/config.h>
6 #include <linux/kernel.h>
8 #include <linux/delay.h>
9 #include <linux/string.h>
10 #include <linux/init.h>
11 #include <linux/capability.h>
12 #include <linux/sched.h>
13 #include <linux/errno.h>
14 #include <linux/bootmem.h>
16 #include <asm/processor.h>
19 #include <asm/sections.h>
20 #include <asm/pci-bridge.h>
21 #include <asm/byteorder.h>
23 #include <asm/uaccess.h>
28 #define DBG(x...) printk(x)
33 unsigned long isa_io_base
= 0;
34 unsigned long isa_mem_base
= 0;
35 unsigned long pci_dram_offset
= 0;
36 int pcibios_assign_bus_offset
= 1;
38 void pcibios_make_OF_bus_map(void);
40 static int pci_relocate_bridge_resource(struct pci_bus
*bus
, int i
);
41 static int probe_resource(struct pci_bus
*parent
, struct resource
*pr
,
42 struct resource
*res
, struct resource
**conflict
);
43 static void update_bridge_base(struct pci_bus
*bus
, int i
);
44 static void pcibios_fixup_resources(struct pci_dev
* dev
);
45 static void fixup_broken_pcnet32(struct pci_dev
* dev
);
46 static int reparent_resources(struct resource
*parent
, struct resource
*res
);
47 static void fixup_rev1_53c810(struct pci_dev
* dev
);
48 static void fixup_cpc710_pci64(struct pci_dev
* dev
);
50 static u8
* pci_to_OF_bus_map
;
53 /* By default, we don't re-assign bus numbers. We do this only on
56 int pci_assign_all_busses
;
58 struct pci_controller
* hose_head
;
59 struct pci_controller
** hose_tail
= &hose_head
;
61 static int pci_bus_count
;
64 fixup_rev1_53c810(struct pci_dev
* dev
)
66 /* rev 1 ncr53c810 chips don't set the class at all which means
67 * they don't get their resources remapped. Fix that here.
70 if ((dev
->class == PCI_CLASS_NOT_DEFINED
)) {
71 printk("NCR 53c810 rev 1 detected, setting PCI class.\n");
72 dev
->class = PCI_CLASS_STORAGE_SCSI
;
75 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR
, PCI_DEVICE_ID_NCR_53C810
, fixup_rev1_53c810
);
78 fixup_broken_pcnet32(struct pci_dev
* dev
)
80 if ((dev
->class>>8 == PCI_CLASS_NETWORK_ETHERNET
)) {
81 dev
->vendor
= PCI_VENDOR_ID_AMD
;
82 pci_write_config_word(dev
, PCI_VENDOR_ID
, PCI_VENDOR_ID_AMD
);
86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT
, PCI_ANY_ID
, fixup_broken_pcnet32
);
89 fixup_cpc710_pci64(struct pci_dev
* dev
)
91 /* Hide the PCI64 BARs from the kernel as their content doesn't
92 * fit well in the resource management
94 dev
->resource
[0].start
= dev
->resource
[0].end
= 0;
95 dev
->resource
[0].flags
= 0;
96 dev
->resource
[1].start
= dev
->resource
[1].end
= 0;
97 dev
->resource
[1].flags
= 0;
99 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM
, PCI_DEVICE_ID_IBM_CPC710_PCI64
, fixup_cpc710_pci64
);
102 pcibios_fixup_resources(struct pci_dev
*dev
)
104 struct pci_controller
* hose
= (struct pci_controller
*)dev
->sysdata
;
106 unsigned long offset
;
109 printk(KERN_ERR
"No hose for PCI dev %s!\n", pci_name(dev
));
112 for (i
= 0; i
< DEVICE_COUNT_RESOURCE
; i
++) {
113 struct resource
*res
= dev
->resource
+ i
;
116 if (res
->end
== 0xffffffff) {
117 DBG("PCI:%s Resource %d [%08lx-%08lx] is unassigned\n",
118 pci_name(dev
), i
, res
->start
, res
->end
);
119 res
->end
-= res
->start
;
121 res
->flags
|= IORESOURCE_UNSET
;
125 if (res
->flags
& IORESOURCE_MEM
) {
126 offset
= hose
->pci_mem_offset
;
127 } else if (res
->flags
& IORESOURCE_IO
) {
128 offset
= (unsigned long) hose
->io_base_virt
132 res
->start
+= offset
;
135 printk("Fixup res %d (%lx) of dev %s: %lx -> %lx\n",
136 i
, res
->flags
, pci_name(dev
),
137 res
->start
- offset
, res
->start
);
142 /* Call machine specific resource fixup */
143 if (ppc_md
.pcibios_fixup_resources
)
144 ppc_md
.pcibios_fixup_resources(dev
);
146 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, pcibios_fixup_resources
);
148 void pcibios_resource_to_bus(struct pci_dev
*dev
, struct pci_bus_region
*region
,
149 struct resource
*res
)
151 unsigned long offset
= 0;
152 struct pci_controller
*hose
= dev
->sysdata
;
154 if (hose
&& res
->flags
& IORESOURCE_IO
)
155 offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
156 else if (hose
&& res
->flags
& IORESOURCE_MEM
)
157 offset
= hose
->pci_mem_offset
;
158 region
->start
= res
->start
- offset
;
159 region
->end
= res
->end
- offset
;
161 EXPORT_SYMBOL(pcibios_resource_to_bus
);
164 * We need to avoid collisions with `mirrored' VGA ports
165 * and other strange ISA hardware, so we always want the
166 * addresses to be allocated in the 0x000-0x0ff region
169 * Why? Because some silly external IO cards only decode
170 * the low 10 bits of the IO address. The 0x00-0xff region
171 * is reserved for motherboard devices that decode all 16
172 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
173 * but we want to try to avoid allocating at 0x2900-0x2bff
174 * which might have be mirrored at 0x0100-0x03ff..
176 void pcibios_align_resource(void *data
, struct resource
*res
, unsigned long size
,
179 struct pci_dev
*dev
= data
;
181 if (res
->flags
& IORESOURCE_IO
) {
182 unsigned long start
= res
->start
;
185 printk(KERN_ERR
"PCI: I/O Region %s/%d too large"
186 " (%ld bytes)\n", pci_name(dev
),
187 dev
->resource
- res
, size
);
191 start
= (start
+ 0x3ff) & ~0x3ff;
196 EXPORT_SYMBOL(pcibios_align_resource
);
199 * Handle resources of PCI devices. If the world were perfect, we could
200 * just allocate all the resource regions and do nothing more. It isn't.
201 * On the other hand, we cannot just re-allocate all devices, as it would
202 * require us to know lots of host bridge internals. So we attempt to
203 * keep as much of the original configuration as possible, but tweak it
204 * when it's found to be wrong.
206 * Known BIOS problems we have to work around:
207 * - I/O or memory regions not configured
208 * - regions configured, but not enabled in the command register
209 * - bogus I/O addresses above 64K used
210 * - expansion ROMs left enabled (this may sound harmless, but given
211 * the fact the PCI specs explicitly allow address decoders to be
212 * shared between expansion ROMs and other resource regions, it's
213 * at least dangerous)
216 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
217 * This gives us fixed barriers on where we can allocate.
218 * (2) Allocate resources for all enabled devices. If there is
219 * a collision, just mark the resource as unallocated. Also
220 * disable expansion ROMs during this step.
221 * (3) Try to allocate resources for disabled devices. If the
222 * resources were assigned correctly, everything goes well,
223 * if they weren't, they won't disturb allocation of other
225 * (4) Assign new addresses to resources which were either
226 * not configured at all or misconfigured. If explicitly
227 * requested by the user, configure expansion ROM address
232 pcibios_allocate_bus_resources(struct list_head
*bus_list
)
234 struct list_head
*ln
;
237 struct resource
*res
, *pr
;
239 /* Depth-First Search on bus tree */
240 for (ln
= bus_list
->next
; ln
!= bus_list
; ln
=ln
->next
) {
242 for (i
= 0; i
< 4; ++i
) {
243 if ((res
= bus
->resource
[i
]) == NULL
|| !res
->flags
244 || res
->start
> res
->end
)
246 if (bus
->parent
== NULL
)
247 pr
= (res
->flags
& IORESOURCE_IO
)?
248 &ioport_resource
: &iomem_resource
;
250 pr
= pci_find_parent_resource(bus
->self
, res
);
252 /* this happens when the generic PCI
253 * code (wrongly) decides that this
254 * bridge is transparent -- paulus
260 DBG("PCI: bridge rsrc %lx..%lx (%lx), parent %p\n",
261 res
->start
, res
->end
, res
->flags
, pr
);
263 if (request_resource(pr
, res
) == 0)
266 * Must be a conflict with an existing entry.
267 * Move that entry (or entries) under the
268 * bridge resource and try again.
270 if (reparent_resources(pr
, res
) == 0)
273 printk(KERN_ERR
"PCI: Cannot allocate resource region "
274 "%d of PCI bridge %d\n", i
, bus
->number
);
275 if (pci_relocate_bridge_resource(bus
, i
))
276 bus
->resource
[i
] = NULL
;
278 pcibios_allocate_bus_resources(&bus
->children
);
283 * Reparent resource children of pr that conflict with res
284 * under res, and make res replace those children.
287 reparent_resources(struct resource
*parent
, struct resource
*res
)
289 struct resource
*p
, **pp
;
290 struct resource
**firstpp
= NULL
;
292 for (pp
= &parent
->child
; (p
= *pp
) != NULL
; pp
= &p
->sibling
) {
293 if (p
->end
< res
->start
)
295 if (res
->end
< p
->start
)
297 if (p
->start
< res
->start
|| p
->end
> res
->end
)
298 return -1; /* not completely contained */
303 return -1; /* didn't find any conflicting entries? */
304 res
->parent
= parent
;
305 res
->child
= *firstpp
;
309 for (p
= res
->child
; p
!= NULL
; p
= p
->sibling
) {
311 DBG(KERN_INFO
"PCI: reparented %s [%lx..%lx] under %s\n",
312 p
->name
, p
->start
, p
->end
, res
->name
);
318 * A bridge has been allocated a range which is outside the range
319 * of its parent bridge, so it needs to be moved.
322 pci_relocate_bridge_resource(struct pci_bus
*bus
, int i
)
324 struct resource
*res
, *pr
, *conflict
;
325 unsigned long try, size
;
327 struct pci_bus
*parent
= bus
->parent
;
329 if (parent
== NULL
) {
330 /* shouldn't ever happen */
331 printk(KERN_ERR
"PCI: can't move host bridge resource\n");
334 res
= bus
->resource
[i
];
338 for (j
= 0; j
< 4; j
++) {
339 struct resource
*r
= parent
->resource
[j
];
342 if ((res
->flags
^ r
->flags
) & (IORESOURCE_IO
| IORESOURCE_MEM
))
344 if (!((res
->flags
^ r
->flags
) & IORESOURCE_PREFETCH
)) {
348 if (res
->flags
& IORESOURCE_PREFETCH
)
353 size
= res
->end
- res
->start
;
354 if (pr
->start
> pr
->end
|| size
> pr
->end
- pr
->start
)
358 res
->start
= try - size
;
360 if (probe_resource(bus
->parent
, pr
, res
, &conflict
) == 0)
362 if (conflict
->start
<= pr
->start
+ size
)
364 try = conflict
->start
- 1;
366 if (request_resource(pr
, res
)) {
367 DBG(KERN_ERR
"PCI: huh? couldn't move to %lx..%lx\n",
368 res
->start
, res
->end
);
369 return -1; /* "can't happen" */
371 update_bridge_base(bus
, i
);
372 printk(KERN_INFO
"PCI: bridge %d resource %d moved to %lx..%lx\n",
373 bus
->number
, i
, res
->start
, res
->end
);
378 probe_resource(struct pci_bus
*parent
, struct resource
*pr
,
379 struct resource
*res
, struct resource
**conflict
)
384 struct list_head
*ln
;
387 for (r
= pr
->child
; r
!= NULL
; r
= r
->sibling
) {
388 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
393 for (ln
= parent
->children
.next
; ln
!= &parent
->children
;
396 for (i
= 0; i
< 4; ++i
) {
397 if ((r
= bus
->resource
[i
]) == NULL
)
399 if (!r
->flags
|| r
->start
> r
->end
|| r
== res
)
401 if (pci_find_parent_resource(bus
->self
, r
) != pr
)
403 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
409 for (ln
= parent
->devices
.next
; ln
!= &parent
->devices
; ln
=ln
->next
) {
411 for (i
= 0; i
< 6; ++i
) {
412 r
= &dev
->resource
[i
];
413 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
415 if (pci_find_parent_resource(dev
, r
) != pr
)
417 if (r
->end
>= res
->start
&& res
->end
>= r
->start
) {
427 update_bridge_base(struct pci_bus
*bus
, int i
)
429 struct resource
*res
= bus
->resource
[i
];
430 u8 io_base_lo
, io_limit_lo
;
431 u16 mem_base
, mem_limit
;
433 unsigned long start
, end
, off
;
434 struct pci_dev
*dev
= bus
->self
;
435 struct pci_controller
*hose
= dev
->sysdata
;
438 printk("update_bridge_base: no hose?\n");
441 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
442 pci_write_config_word(dev
, PCI_COMMAND
,
443 cmd
& ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
));
444 if (res
->flags
& IORESOURCE_IO
) {
445 off
= (unsigned long) hose
->io_base_virt
- isa_io_base
;
446 start
= res
->start
- off
;
447 end
= res
->end
- off
;
448 io_base_lo
= (start
>> 8) & PCI_IO_RANGE_MASK
;
449 io_limit_lo
= (end
>> 8) & PCI_IO_RANGE_MASK
;
451 pci_write_config_word(dev
, PCI_IO_BASE_UPPER16
,
453 pci_write_config_word(dev
, PCI_IO_LIMIT_UPPER16
,
455 io_base_lo
|= PCI_IO_RANGE_TYPE_32
;
457 io_base_lo
|= PCI_IO_RANGE_TYPE_16
;
458 pci_write_config_byte(dev
, PCI_IO_BASE
, io_base_lo
);
459 pci_write_config_byte(dev
, PCI_IO_LIMIT
, io_limit_lo
);
461 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
463 off
= hose
->pci_mem_offset
;
464 mem_base
= ((res
->start
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
465 mem_limit
= ((res
->end
- off
) >> 16) & PCI_MEMORY_RANGE_MASK
;
466 pci_write_config_word(dev
, PCI_MEMORY_BASE
, mem_base
);
467 pci_write_config_word(dev
, PCI_MEMORY_LIMIT
, mem_limit
);
469 } else if ((res
->flags
& (IORESOURCE_MEM
| IORESOURCE_PREFETCH
))
470 == (IORESOURCE_MEM
| IORESOURCE_PREFETCH
)) {
471 off
= hose
->pci_mem_offset
;
472 mem_base
= ((res
->start
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
473 mem_limit
= ((res
->end
- off
) >> 16) & PCI_PREF_RANGE_MASK
;
474 pci_write_config_word(dev
, PCI_PREF_MEMORY_BASE
, mem_base
);
475 pci_write_config_word(dev
, PCI_PREF_MEMORY_LIMIT
, mem_limit
);
478 DBG(KERN_ERR
"PCI: ugh, bridge %s res %d has flags=%lx\n",
479 pci_name(dev
), i
, res
->flags
);
481 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
484 static inline void alloc_resource(struct pci_dev
*dev
, int idx
)
486 struct resource
*pr
, *r
= &dev
->resource
[idx
];
488 DBG("PCI:%s: Resource %d: %08lx-%08lx (f=%lx)\n",
489 pci_name(dev
), idx
, r
->start
, r
->end
, r
->flags
);
490 pr
= pci_find_parent_resource(dev
, r
);
491 if (!pr
|| request_resource(pr
, r
) < 0) {
492 printk(KERN_ERR
"PCI: Cannot allocate resource region %d"
493 " of device %s\n", idx
, pci_name(dev
));
495 DBG("PCI: parent is %p: %08lx-%08lx (f=%lx)\n",
496 pr
, pr
->start
, pr
->end
, pr
->flags
);
497 /* We'll assign a new address later */
498 r
->flags
|= IORESOURCE_UNSET
;
505 pcibios_allocate_resources(int pass
)
507 struct pci_dev
*dev
= NULL
;
512 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
513 pci_read_config_word(dev
, PCI_COMMAND
, &command
);
514 for (idx
= 0; idx
< 6; idx
++) {
515 r
= &dev
->resource
[idx
];
516 if (r
->parent
) /* Already allocated */
518 if (!r
->flags
|| (r
->flags
& IORESOURCE_UNSET
))
519 continue; /* Not assigned at all */
520 if (r
->flags
& IORESOURCE_IO
)
521 disabled
= !(command
& PCI_COMMAND_IO
);
523 disabled
= !(command
& PCI_COMMAND_MEMORY
);
524 if (pass
== disabled
)
525 alloc_resource(dev
, idx
);
529 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
530 if (r
->flags
& PCI_ROM_ADDRESS_ENABLE
) {
531 /* Turn the ROM off, leave the resource region, but keep it unregistered. */
533 DBG("PCI: Switching off ROM of %s\n", pci_name(dev
));
534 r
->flags
&= ~PCI_ROM_ADDRESS_ENABLE
;
535 pci_read_config_dword(dev
, dev
->rom_base_reg
, ®
);
536 pci_write_config_dword(dev
, dev
->rom_base_reg
,
537 reg
& ~PCI_ROM_ADDRESS_ENABLE
);
543 pcibios_assign_resources(void)
545 struct pci_dev
*dev
= NULL
;
549 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
550 int class = dev
->class >> 8;
552 /* Don't touch classless devices and host bridges */
553 if (!class || class == PCI_CLASS_BRIDGE_HOST
)
556 for (idx
= 0; idx
< 6; idx
++) {
557 r
= &dev
->resource
[idx
];
560 * We shall assign a new address to this resource,
561 * either because the BIOS (sic) forgot to do so
562 * or because we have decided the old address was
563 * unusable for some reason.
565 if ((r
->flags
& IORESOURCE_UNSET
) && r
->end
&&
566 (!ppc_md
.pcibios_enable_device_hook
||
567 !ppc_md
.pcibios_enable_device_hook(dev
, 1))) {
568 r
->flags
&= ~IORESOURCE_UNSET
;
569 pci_assign_resource(dev
, idx
);
573 #if 0 /* don't assign ROMs */
574 r
= &dev
->resource
[PCI_ROM_RESOURCE
];
578 pci_assign_resource(dev
, PCI_ROM_RESOURCE
);
585 pcibios_enable_resources(struct pci_dev
*dev
, int mask
)
591 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
593 for (idx
=0; idx
<6; idx
++) {
594 /* Only set up the requested stuff */
595 if (!(mask
& (1<<idx
)))
598 r
= &dev
->resource
[idx
];
599 if (r
->flags
& IORESOURCE_UNSET
) {
600 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
603 if (r
->flags
& IORESOURCE_IO
)
604 cmd
|= PCI_COMMAND_IO
;
605 if (r
->flags
& IORESOURCE_MEM
)
606 cmd
|= PCI_COMMAND_MEMORY
;
608 if (dev
->resource
[PCI_ROM_RESOURCE
].start
)
609 cmd
|= PCI_COMMAND_MEMORY
;
610 if (cmd
!= old_cmd
) {
611 printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev
), old_cmd
, cmd
);
612 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
617 static int next_controller_index
;
619 struct pci_controller
* __init
620 pcibios_alloc_controller(void)
622 struct pci_controller
*hose
;
624 hose
= (struct pci_controller
*)alloc_bootmem(sizeof(*hose
));
625 memset(hose
, 0, sizeof(struct pci_controller
));
628 hose_tail
= &hose
->next
;
630 hose
->index
= next_controller_index
++;
637 * Functions below are used on OpenFirmware machines.
639 static void __openfirmware
640 make_one_node_map(struct device_node
* node
, u8 pci_bus
)
645 if (pci_bus
>= pci_bus_count
)
647 bus_range
= (int *) get_property(node
, "bus-range", &len
);
648 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
649 printk(KERN_WARNING
"Can't get bus-range for %s, "
650 "assuming it starts at 0\n", node
->full_name
);
651 pci_to_OF_bus_map
[pci_bus
] = 0;
653 pci_to_OF_bus_map
[pci_bus
] = bus_range
[0];
655 for (node
=node
->child
; node
!= 0;node
= node
->sibling
) {
657 unsigned int *class_code
, *reg
;
659 class_code
= (unsigned int *) get_property(node
, "class-code", NULL
);
660 if (!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
661 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
))
663 reg
= (unsigned int *)get_property(node
, "reg", NULL
);
666 dev
= pci_find_slot(pci_bus
, ((reg
[0] >> 8) & 0xff));
667 if (!dev
|| !dev
->subordinate
)
669 make_one_node_map(node
, dev
->subordinate
->number
);
674 pcibios_make_OF_bus_map(void)
677 struct pci_controller
* hose
;
680 pci_to_OF_bus_map
= (u8
*)kmalloc(pci_bus_count
, GFP_KERNEL
);
681 if (!pci_to_OF_bus_map
) {
682 printk(KERN_ERR
"Can't allocate OF bus map !\n");
686 /* We fill the bus map with invalid values, that helps
689 for (i
=0; i
<pci_bus_count
; i
++)
690 pci_to_OF_bus_map
[i
] = 0xff;
692 /* For each hose, we begin searching bridges */
693 for(hose
=hose_head
; hose
; hose
=hose
->next
) {
694 struct device_node
* node
;
695 node
= (struct device_node
*)hose
->arch_data
;
698 make_one_node_map(node
, hose
->first_busno
);
700 of_prop_map
= get_property(find_path_device("/"), "pci-OF-bus-map", NULL
);
702 memcpy(of_prop_map
, pci_to_OF_bus_map
, pci_bus_count
);
704 printk("PCI->OF bus map:\n");
705 for (i
=0; i
<pci_bus_count
; i
++) {
706 if (pci_to_OF_bus_map
[i
] == 0xff)
708 printk("%d -> %d\n", i
, pci_to_OF_bus_map
[i
]);
713 typedef int (*pci_OF_scan_iterator
)(struct device_node
* node
, void* data
);
715 static struct device_node
* __openfirmware
716 scan_OF_pci_childs(struct device_node
* node
, pci_OF_scan_iterator filter
, void* data
)
718 struct device_node
* sub_node
;
720 for (; node
!= 0;node
= node
->sibling
) {
721 unsigned int *class_code
;
723 if (filter(node
, data
))
726 /* For PCI<->PCI bridges or CardBus bridges, we go down
727 * Note: some OFs create a parent node "multifunc-device" as
728 * a fake root for all functions of a multi-function device,
729 * we go down them as well.
731 class_code
= (unsigned int *) get_property(node
, "class-code", NULL
);
732 if ((!class_code
|| ((*class_code
>> 8) != PCI_CLASS_BRIDGE_PCI
&&
733 (*class_code
>> 8) != PCI_CLASS_BRIDGE_CARDBUS
)) &&
734 strcmp(node
->name
, "multifunc-device"))
736 sub_node
= scan_OF_pci_childs(node
->child
, filter
, data
);
744 scan_OF_pci_childs_iterator(struct device_node
* node
, void* data
)
747 u8
* fdata
= (u8
*)data
;
749 reg
= (unsigned int *) get_property(node
, "reg", NULL
);
750 if (reg
&& ((reg
[0] >> 8) & 0xff) == fdata
[1]
751 && ((reg
[0] >> 16) & 0xff) == fdata
[0])
756 static struct device_node
* __openfirmware
757 scan_OF_childs_for_device(struct device_node
* node
, u8 bus
, u8 dev_fn
)
759 u8 filter_data
[2] = {bus
, dev_fn
};
761 return scan_OF_pci_childs(node
, scan_OF_pci_childs_iterator
, filter_data
);
765 * Scans the OF tree for a device node matching a PCI device
768 pci_busdev_to_OF_node(struct pci_bus
*bus
, int devfn
)
770 struct pci_controller
*hose
;
771 struct device_node
*node
;
777 /* Lookup the hose */
779 hose
= pci_bus_to_hose(busnr
);
783 /* Check it has an OF node associated */
784 node
= (struct device_node
*) hose
->arch_data
;
788 /* Fixup bus number according to what OF think it is. */
789 #ifdef CONFIG_PPC_PMAC
790 /* The G5 need a special case here. Basically, we don't remap all
791 * busses on it so we don't create the pci-OF-map. However, we do
792 * remap the AGP bus and so have to deal with it. A future better
793 * fix has to be done by making the remapping per-host and always
794 * filling the pci_to_OF map. --BenH
796 if (_machine
== _MACH_Pmac
&& busnr
>= 0xf0)
800 if (pci_to_OF_bus_map
)
801 busnr
= pci_to_OF_bus_map
[busnr
];
805 /* Now, lookup childs of the hose */
806 return scan_OF_childs_for_device(node
->child
, busnr
, devfn
);
810 pci_device_to_OF_node(struct pci_dev
*dev
)
812 return pci_busdev_to_OF_node(dev
->bus
, dev
->devfn
);
815 /* This routine is meant to be used early during boot, when the
816 * PCI bus numbers have not yet been assigned, and you need to
817 * issue PCI config cycles to an OF device.
818 * It could also be used to "fix" RTAS config cycles if you want
819 * to set pci_assign_all_busses to 1 and still use RTAS for PCI
822 struct pci_controller
*
823 pci_find_hose_for_OF_device(struct device_node
* node
)
828 struct pci_controller
* hose
;
829 for (hose
=hose_head
;hose
;hose
=hose
->next
)
830 if (hose
->arch_data
== node
)
837 static int __openfirmware
838 find_OF_pci_device_filter(struct device_node
* node
, void* data
)
840 return ((void *)node
== data
);
844 * Returns the PCI device matching a given OF node
847 pci_device_from_OF_node(struct device_node
* node
, u8
* bus
, u8
* devfn
)
850 struct pci_controller
* hose
;
851 struct pci_dev
* dev
= NULL
;
855 /* Make sure it's really a PCI device */
856 hose
= pci_find_hose_for_OF_device(node
);
857 if (!hose
|| !hose
->arch_data
)
859 if (!scan_OF_pci_childs(((struct device_node
*)hose
->arch_data
)->child
,
860 find_OF_pci_device_filter
, (void *)node
))
862 reg
= (unsigned int *) get_property(node
, "reg", NULL
);
865 *bus
= (reg
[0] >> 16) & 0xff;
866 *devfn
= ((reg
[0] >> 8) & 0xff);
868 /* Ok, here we need some tweak. If we have already renumbered
869 * all busses, we can't rely on the OF bus number any more.
870 * the pci_to_OF_bus_map is not enough as several PCI busses
871 * may match the same OF bus number.
873 if (!pci_to_OF_bus_map
)
875 while ((dev
= pci_find_device(PCI_ANY_ID
, PCI_ANY_ID
, dev
)) != NULL
) {
876 if (pci_to_OF_bus_map
[dev
->bus
->number
] != *bus
)
878 if (dev
->devfn
!= *devfn
)
880 *bus
= dev
->bus
->number
;
887 pci_process_bridge_OF_ranges(struct pci_controller
*hose
,
888 struct device_node
*dev
, int primary
)
890 static unsigned int static_lc_ranges
[256] __initdata
;
891 unsigned int *dt_ranges
, *lc_ranges
, *ranges
, *prev
;
893 int rlen
= 0, orig_rlen
;
895 struct resource
*res
;
896 int np
, na
= prom_n_addr_cells(dev
);
899 /* First we try to merge ranges to fix a problem with some pmacs
900 * that can have more than 3 ranges, fortunately using contiguous
903 dt_ranges
= (unsigned int *) get_property(dev
, "ranges", &rlen
);
906 /* Sanity check, though hopefully that never happens */
907 if (rlen
> sizeof(static_lc_ranges
)) {
908 printk(KERN_WARNING
"OF ranges property too large !\n");
909 rlen
= sizeof(static_lc_ranges
);
911 lc_ranges
= static_lc_ranges
;
912 memcpy(lc_ranges
, dt_ranges
, rlen
);
915 /* Let's work on a copy of the "ranges" property instead of damaging
916 * the device-tree image in memory
920 while ((rlen
-= np
* sizeof(unsigned int)) >= 0) {
922 if (prev
[0] == ranges
[0] && prev
[1] == ranges
[1] &&
923 (prev
[2] + prev
[na
+4]) == ranges
[2] &&
924 (prev
[na
+2] + prev
[na
+4]) == ranges
[na
+2]) {
925 prev
[na
+4] += ranges
[na
+4];
936 * The ranges property is laid out as an array of elements,
937 * each of which comprises:
938 * cells 0 - 2: a PCI address
939 * cells 3 or 3+4: a CPU physical address
940 * (size depending on dev->n_addr_cells)
941 * cells 4+5 or 5+6: the size of the range
945 while (ranges
&& (rlen
-= np
* sizeof(unsigned int)) >= 0) {
948 switch (ranges
[0] >> 24) {
949 case 1: /* I/O space */
952 hose
->io_base_phys
= ranges
[na
+2];
953 /* limit I/O space to 16MB */
954 if (size
> 0x01000000)
956 hose
->io_base_virt
= ioremap(ranges
[na
+2], size
);
958 isa_io_base
= (unsigned long) hose
->io_base_virt
;
959 res
= &hose
->io_resource
;
960 res
->flags
= IORESOURCE_IO
;
961 res
->start
= ranges
[2];
963 case 2: /* memory space */
965 if (ranges
[1] == 0 && ranges
[2] == 0
966 && ranges
[na
+4] <= (16 << 20)) {
967 /* 1st 16MB, i.e. ISA memory area */
969 isa_mem_base
= ranges
[na
+2];
972 while (memno
< 3 && hose
->mem_resources
[memno
].flags
)
975 hose
->pci_mem_offset
= ranges
[na
+2] - ranges
[2];
977 res
= &hose
->mem_resources
[memno
];
978 res
->flags
= IORESOURCE_MEM
;
979 res
->start
= ranges
[na
+2];
984 res
->name
= dev
->full_name
;
985 res
->end
= res
->start
+ size
- 1;
994 /* We create the "pci-OF-bus-map" property now so it appears in the
998 pci_create_OF_bus_map(void)
1000 struct property
* of_prop
;
1002 of_prop
= (struct property
*) alloc_bootmem(sizeof(struct property
) + 256);
1003 if (of_prop
&& find_path_device("/")) {
1004 memset(of_prop
, -1, sizeof(struct property
) + 256);
1005 of_prop
->name
= "pci-OF-bus-map";
1006 of_prop
->length
= 256;
1007 of_prop
->value
= (unsigned char *)&of_prop
[1];
1008 prom_add_property(find_path_device("/"), of_prop
);
1012 static ssize_t
pci_show_devspec(struct device
*dev
, char *buf
)
1014 struct pci_dev
*pdev
;
1015 struct device_node
*np
;
1017 pdev
= to_pci_dev (dev
);
1018 np
= pci_device_to_OF_node(pdev
);
1019 if (np
== NULL
|| np
->full_name
== NULL
)
1021 return sprintf(buf
, "%s", np
->full_name
);
1023 static DEVICE_ATTR(devspec
, S_IRUGO
, pci_show_devspec
, NULL
);
1025 #endif /* CONFIG_PPC_OF */
1027 /* Add sysfs properties */
1028 void pcibios_add_platform_entries(struct pci_dev
*pdev
)
1030 #ifdef CONFIG_PPC_OF
1031 device_create_file(&pdev
->dev
, &dev_attr_devspec
);
1032 #endif /* CONFIG_PPC_OF */
1036 #ifdef CONFIG_PPC_PMAC
1038 * This set of routines checks for PCI<->PCI bridges that have closed
1039 * IO resources and have child devices. It tries to re-open an IO
1042 * This is a _temporary_ fix to workaround a problem with Apple's OF
1043 * closing IO windows on P2P bridges when the OF drivers of cards
1044 * below this bridge don't claim any IO range (typically ATI or
1047 * A more complete fix would be to use drivers/pci/setup-bus.c, which
1048 * involves a working pcibios_fixup_pbus_ranges(), some more care about
1049 * ordering when creating the host bus resources, and maybe a few more
1053 /* Initialize bridges with base/limit values we have collected */
1055 do_update_p2p_io_resource(struct pci_bus
*bus
, int enable_vga
)
1057 struct pci_dev
*bridge
= bus
->self
;
1058 struct pci_controller
* hose
= (struct pci_controller
*)bridge
->sysdata
;
1061 struct resource res
;
1063 if (bus
->resource
[0] == NULL
)
1065 res
= *(bus
->resource
[0]);
1067 DBG("Remapping Bus %d, bridge: %s\n", bus
->number
, bridge
->slot_name
);
1068 res
.start
-= ((unsigned long) hose
->io_base_virt
- isa_io_base
);
1069 res
.end
-= ((unsigned long) hose
->io_base_virt
- isa_io_base
);
1070 DBG(" IO window: %08lx-%08lx\n", res
.start
, res
.end
);
1072 /* Set up the top and bottom of the PCI I/O segment for this bus. */
1073 pci_read_config_dword(bridge
, PCI_IO_BASE
, &l
);
1075 l
|= (res
.start
>> 8) & 0x00f0;
1076 l
|= res
.end
& 0xf000;
1077 pci_write_config_dword(bridge
, PCI_IO_BASE
, l
);
1079 if ((l
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
) {
1080 l
= (res
.start
>> 16) | (res
.end
& 0xffff0000);
1081 pci_write_config_dword(bridge
, PCI_IO_BASE_UPPER16
, l
);
1084 pci_read_config_word(bridge
, PCI_COMMAND
, &w
);
1085 w
|= PCI_COMMAND_IO
;
1086 pci_write_config_word(bridge
, PCI_COMMAND
, w
);
1088 #if 0 /* Enabling this causes XFree 4.2.0 to hang during PCI probe */
1090 pci_read_config_word(bridge
, PCI_BRIDGE_CONTROL
, &w
);
1091 w
|= PCI_BRIDGE_CTL_VGA
;
1092 pci_write_config_word(bridge
, PCI_BRIDGE_CONTROL
, w
);
1097 /* This function is pretty basic and actually quite broken for the
1098 * general case, it's enough for us right now though. It's supposed
1099 * to tell us if we need to open an IO range at all or not and what
1103 check_for_io_childs(struct pci_bus
*bus
, struct resource
* res
, int *found_vga
)
1105 struct list_head
*ln
;
1109 #define push_end(res, size) do { unsigned long __sz = (size) ; \
1110 res->end = ((res->end + __sz) / (__sz + 1)) * (__sz + 1) + __sz; \
1113 for (ln
=bus
->devices
.next
; ln
!= &bus
->devices
; ln
=ln
->next
) {
1114 struct pci_dev
*dev
= pci_dev_b(ln
);
1115 u16
class = dev
->class >> 8;
1117 if (class == PCI_CLASS_DISPLAY_VGA
||
1118 class == PCI_CLASS_NOT_DEFINED_VGA
)
1120 if (class >> 8 == PCI_BASE_CLASS_BRIDGE
&& dev
->subordinate
)
1121 rc
|= check_for_io_childs(dev
->subordinate
, res
, found_vga
);
1122 if (class == PCI_CLASS_BRIDGE_CARDBUS
)
1123 push_end(res
, 0xfff);
1125 for (i
=0; i
<PCI_NUM_RESOURCES
; i
++) {
1127 unsigned long r_size
;
1129 if (dev
->class >> 8 == PCI_CLASS_BRIDGE_PCI
1130 && i
>= PCI_BRIDGE_RESOURCES
)
1132 r
= &dev
->resource
[i
];
1133 r_size
= r
->end
- r
->start
;
1136 if (r
->flags
& IORESOURCE_IO
&& (r_size
) != 0) {
1138 push_end(res
, r_size
);
1146 /* Here we scan all P2P bridges of a given level that have a closed
1147 * IO window. Note that the test for the presence of a VGA card should
1148 * be improved to take into account already configured P2P bridges,
1149 * currently, we don't see them and might end up configuring 2 bridges
1150 * with VGA pass through enabled
1153 do_fixup_p2p_level(struct pci_bus
*bus
)
1155 struct list_head
*ln
;
1159 for (parent_io
=0; parent_io
<4; parent_io
++)
1160 if (bus
->resource
[parent_io
]
1161 && bus
->resource
[parent_io
]->flags
& IORESOURCE_IO
)
1166 for (ln
=bus
->children
.next
; ln
!= &bus
->children
; ln
=ln
->next
) {
1167 struct pci_bus
*b
= pci_bus_b(ln
);
1168 struct pci_dev
*d
= b
->self
;
1169 struct pci_controller
* hose
= (struct pci_controller
*)d
->sysdata
;
1170 struct resource
*res
= b
->resource
[0];
1171 struct resource tmp_res
;
1175 memset(&tmp_res
, 0, sizeof(tmp_res
));
1176 tmp_res
.start
= bus
->resource
[parent_io
]->start
;
1178 /* We don't let low addresses go through that closed P2P bridge, well,
1179 * that may not be necessary but I feel safer that way
1181 if (tmp_res
.start
== 0)
1182 tmp_res
.start
= 0x1000;
1184 if (!list_empty(&b
->devices
) && res
&& res
->flags
== 0 &&
1185 res
!= bus
->resource
[parent_io
] &&
1186 (d
->class >> 8) == PCI_CLASS_BRIDGE_PCI
&&
1187 check_for_io_childs(b
, &tmp_res
, &found_vga
)) {
1190 printk(KERN_INFO
"Fixing up IO bus %s\n", b
->name
);
1194 printk(KERN_WARNING
"Skipping VGA, already active"
1195 " on bus segment\n");
1200 pci_read_config_byte(d
, PCI_IO_BASE
, &io_base_lo
);
1202 if ((io_base_lo
& PCI_IO_RANGE_TYPE_MASK
) == PCI_IO_RANGE_TYPE_32
)
1203 max
= ((unsigned long) hose
->io_base_virt
1204 - isa_io_base
) + 0xffffffff;
1206 max
= ((unsigned long) hose
->io_base_virt
1207 - isa_io_base
) + 0xffff;
1210 res
->flags
= IORESOURCE_IO
;
1211 res
->name
= b
->name
;
1213 /* Find a resource in the parent where we can allocate */
1214 for (i
= 0 ; i
< 4; i
++) {
1215 struct resource
*r
= bus
->resource
[i
];
1218 if ((r
->flags
& IORESOURCE_IO
) == 0)
1220 DBG("Trying to allocate from %08lx, size %08lx from parent"
1221 " res %d: %08lx -> %08lx\n",
1222 res
->start
, res
->end
, i
, r
->start
, r
->end
);
1224 if (allocate_resource(r
, res
, res
->end
+ 1, res
->start
, max
,
1225 res
->end
+ 1, NULL
, NULL
) < 0) {
1229 do_update_p2p_io_resource(b
, found_vga
);
1233 do_fixup_p2p_level(b
);
1238 pcibios_fixup_p2p_bridges(void)
1240 struct list_head
*ln
;
1242 for(ln
=pci_root_buses
.next
; ln
!= &pci_root_buses
; ln
=ln
->next
) {
1243 struct pci_bus
*b
= pci_bus_b(ln
);
1244 do_fixup_p2p_level(b
);
1248 #endif /* CONFIG_PPC_PMAC */
1253 struct pci_controller
*hose
;
1254 struct pci_bus
*bus
;
1257 printk(KERN_INFO
"PCI: Probing PCI hardware\n");
1259 /* Scan all of the recorded PCI controllers. */
1260 for (next_busno
= 0, hose
= hose_head
; hose
; hose
= hose
->next
) {
1261 if (pci_assign_all_busses
)
1262 hose
->first_busno
= next_busno
;
1263 hose
->last_busno
= 0xff;
1264 bus
= pci_scan_bus(hose
->first_busno
, hose
->ops
, hose
);
1265 hose
->last_busno
= bus
->subordinate
;
1266 if (pci_assign_all_busses
|| next_busno
<= hose
->last_busno
)
1267 next_busno
= hose
->last_busno
+ pcibios_assign_bus_offset
;
1269 pci_bus_count
= next_busno
;
1271 /* OpenFirmware based machines need a map of OF bus
1272 * numbers vs. kernel bus numbers since we may have to
1275 if (pci_assign_all_busses
&& have_of
)
1276 pcibios_make_OF_bus_map();
1278 /* Do machine dependent PCI interrupt routing */
1279 if (ppc_md
.pci_swizzle
&& ppc_md
.pci_map_irq
)
1280 pci_fixup_irqs(ppc_md
.pci_swizzle
, ppc_md
.pci_map_irq
);
1282 /* Call machine dependent fixup */
1283 if (ppc_md
.pcibios_fixup
)
1284 ppc_md
.pcibios_fixup();
1286 /* Allocate and assign resources */
1287 pcibios_allocate_bus_resources(&pci_root_buses
);
1288 pcibios_allocate_resources(0);
1289 pcibios_allocate_resources(1);
1290 #ifdef CONFIG_PPC_PMAC
1291 pcibios_fixup_p2p_bridges();
1292 #endif /* CONFIG_PPC_PMAC */
1293 pcibios_assign_resources();
1295 /* Call machine dependent post-init code */
1296 if (ppc_md
.pcibios_after_init
)
1297 ppc_md
.pcibios_after_init();
1302 subsys_initcall(pcibios_init
);
1304 unsigned char __init
1305 common_swizzle(struct pci_dev
*dev
, unsigned char *pinp
)
1307 struct pci_controller
*hose
= dev
->sysdata
;
1309 if (dev
->bus
->number
!= hose
->first_busno
) {
1312 pin
= bridge_swizzle(pin
, PCI_SLOT(dev
->devfn
));
1313 /* Move up the chain of bridges. */
1314 dev
= dev
->bus
->self
;
1315 } while (dev
->bus
->self
);
1318 /* The slot is the idsel of the last bridge. */
1320 return PCI_SLOT(dev
->devfn
);
1323 unsigned long resource_fixup(struct pci_dev
* dev
, struct resource
* res
,
1324 unsigned long start
, unsigned long size
)
1329 void __init
pcibios_fixup_bus(struct pci_bus
*bus
)
1331 struct pci_controller
*hose
= (struct pci_controller
*) bus
->sysdata
;
1332 unsigned long io_offset
;
1333 struct resource
*res
;
1336 io_offset
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1337 if (bus
->parent
== NULL
) {
1338 /* This is a host bridge - fill in its resources */
1341 bus
->resource
[0] = res
= &hose
->io_resource
;
1344 printk(KERN_ERR
"I/O resource not set for host"
1345 " bridge %d\n", hose
->index
);
1347 res
->end
= IO_SPACE_LIMIT
;
1348 res
->flags
= IORESOURCE_IO
;
1350 res
->start
+= io_offset
;
1351 res
->end
+= io_offset
;
1353 for (i
= 0; i
< 3; ++i
) {
1354 res
= &hose
->mem_resources
[i
];
1358 printk(KERN_ERR
"Memory resource not set for "
1359 "host bridge %d\n", hose
->index
);
1360 res
->start
= hose
->pci_mem_offset
;
1362 res
->flags
= IORESOURCE_MEM
;
1364 bus
->resource
[i
+1] = res
;
1367 /* This is a subordinate bridge */
1368 pci_read_bridge_bases(bus
);
1370 for (i
= 0; i
< 4; ++i
) {
1371 if ((res
= bus
->resource
[i
]) == NULL
)
1375 if (io_offset
&& (res
->flags
& IORESOURCE_IO
)) {
1376 res
->start
+= io_offset
;
1377 res
->end
+= io_offset
;
1378 } else if (hose
->pci_mem_offset
1379 && (res
->flags
& IORESOURCE_MEM
)) {
1380 res
->start
+= hose
->pci_mem_offset
;
1381 res
->end
+= hose
->pci_mem_offset
;
1386 if (ppc_md
.pcibios_fixup_bus
)
1387 ppc_md
.pcibios_fixup_bus(bus
);
1390 char __init
*pcibios_setup(char *str
)
1395 /* the next one is stolen from the alpha port... */
1397 pcibios_update_irq(struct pci_dev
*dev
, int irq
)
1399 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, irq
);
1400 /* XXX FIXME - update OF device tree node interrupt property */
1403 int pcibios_enable_device(struct pci_dev
*dev
, int mask
)
1409 if (ppc_md
.pcibios_enable_device_hook
)
1410 if (ppc_md
.pcibios_enable_device_hook(dev
, 0))
1413 pci_read_config_word(dev
, PCI_COMMAND
, &cmd
);
1415 for (idx
=0; idx
<6; idx
++) {
1416 r
= &dev
->resource
[idx
];
1417 if (r
->flags
& IORESOURCE_UNSET
) {
1418 printk(KERN_ERR
"PCI: Device %s not available because of resource collisions\n", pci_name(dev
));
1421 if (r
->flags
& IORESOURCE_IO
)
1422 cmd
|= PCI_COMMAND_IO
;
1423 if (r
->flags
& IORESOURCE_MEM
)
1424 cmd
|= PCI_COMMAND_MEMORY
;
1426 if (cmd
!= old_cmd
) {
1427 printk("PCI: Enabling device %s (%04x -> %04x)\n",
1428 pci_name(dev
), old_cmd
, cmd
);
1429 pci_write_config_word(dev
, PCI_COMMAND
, cmd
);
1434 struct pci_controller
*
1435 pci_bus_to_hose(int bus
)
1437 struct pci_controller
* hose
= hose_head
;
1439 for (; hose
; hose
= hose
->next
)
1440 if (bus
>= hose
->first_busno
&& bus
<= hose
->last_busno
)
1446 pci_bus_io_base(unsigned int bus
)
1448 struct pci_controller
*hose
;
1450 hose
= pci_bus_to_hose(bus
);
1453 return hose
->io_base_virt
;
1457 pci_bus_io_base_phys(unsigned int bus
)
1459 struct pci_controller
*hose
;
1461 hose
= pci_bus_to_hose(bus
);
1464 return hose
->io_base_phys
;
1468 pci_bus_mem_base_phys(unsigned int bus
)
1470 struct pci_controller
*hose
;
1472 hose
= pci_bus_to_hose(bus
);
1475 return hose
->pci_mem_offset
;
1479 pci_resource_to_bus(struct pci_dev
*pdev
, struct resource
*res
)
1481 /* Hack alert again ! See comments in chrp_pci.c
1483 struct pci_controller
* hose
=
1484 (struct pci_controller
*)pdev
->sysdata
;
1485 if (hose
&& res
->flags
& IORESOURCE_MEM
)
1486 return res
->start
- hose
->pci_mem_offset
;
1487 /* We may want to do something with IOs here... */
1492 * Platform support for /proc/bus/pci/X/Y mmap()s,
1493 * modelled on the sparc64 implementation by Dave Miller.
1498 * Adjust vm_pgoff of VMA such that it is the physical page offset
1499 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
1501 * Basically, the user finds the base address for his device which he wishes
1502 * to mmap. They read the 32-bit value from the config space base register,
1503 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
1504 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
1506 * Returns negative error code on failure, zero on success.
1508 static __inline__
int
1509 __pci_mmap_make_offset(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1510 enum pci_mmap_state mmap_state
)
1512 struct pci_controller
*hose
= (struct pci_controller
*) dev
->sysdata
;
1513 unsigned long offset
= vma
->vm_pgoff
<< PAGE_SHIFT
;
1514 unsigned long size
= vma
->vm_end
- vma
->vm_start
;
1516 struct resource
*res
;
1521 return -EINVAL
; /* should never happen */
1522 if (offset
+ size
<= offset
)
1525 if (mmap_state
== pci_mmap_mem
) {
1526 /* PCI memory space */
1527 base
= hose
->pci_mem_offset
;
1528 for (i
= 0; i
< 3; ++i
) {
1529 res
= &hose
->mem_resources
[i
];
1530 if (res
->flags
== 0)
1532 if (offset
>= res
->start
- base
1533 && offset
+ size
- 1 <= res
->end
- base
) {
1538 offset
+= hose
->pci_mem_offset
;
1541 base
= (unsigned long)hose
->io_base_virt
- isa_io_base
;
1542 res
= &hose
->io_resource
;
1543 if (offset
>= res
->start
- base
1544 && offset
+ size
- 1 <= res
->end
- base
)
1546 offset
+= hose
->io_base_phys
;
1549 vma
->vm_pgoff
= offset
>> PAGE_SHIFT
;
1554 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
1557 static __inline__
void
1558 __pci_mmap_set_flags(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1559 enum pci_mmap_state mmap_state
)
1561 vma
->vm_flags
|= VM_SHM
| VM_LOCKED
| VM_IO
;
1565 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
1568 static __inline__
void
1569 __pci_mmap_set_pgprot(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1570 enum pci_mmap_state mmap_state
, int write_combine
)
1572 int prot
= pgprot_val(vma
->vm_page_prot
);
1574 /* XXX would be nice to have a way to ask for write-through */
1575 prot
|= _PAGE_NO_CACHE
;
1577 prot
|= _PAGE_GUARDED
;
1578 vma
->vm_page_prot
= __pgprot(prot
);
1582 * Perform the actual remap of the pages for a PCI device mapping, as
1583 * appropriate for this architecture. The region in the process to map
1584 * is described by vm_start and vm_end members of VMA, the base physical
1585 * address is found in vm_pgoff.
1586 * The pci device structure is provided so that architectures may make mapping
1587 * decisions on a per-device or per-bus basis.
1589 * Returns a negative error code on failure, zero on success.
1591 int pci_mmap_page_range(struct pci_dev
*dev
, struct vm_area_struct
*vma
,
1592 enum pci_mmap_state mmap_state
,
1597 ret
= __pci_mmap_make_offset(dev
, vma
, mmap_state
);
1601 __pci_mmap_set_flags(dev
, vma
, mmap_state
);
1602 __pci_mmap_set_pgprot(dev
, vma
, mmap_state
, write_combine
);
1604 ret
= remap_page_range(vma
, vma
->vm_start
, vma
->vm_pgoff
<< PAGE_SHIFT
,
1605 vma
->vm_end
- vma
->vm_start
, vma
->vm_page_prot
);
1610 /* Obsolete functions. Should be removed once the symbios driver
1614 phys_to_bus(unsigned long pa
)
1616 struct pci_controller
*hose
;
1619 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
1620 for (i
= 0; i
< 3; ++i
) {
1621 if (pa
>= hose
->mem_resources
[i
].start
1622 && pa
<= hose
->mem_resources
[i
].end
) {
1624 * XXX the hose->pci_mem_offset really
1625 * only applies to mem_resources[0].
1626 * We need a way to store an offset for
1627 * the others. -- paulus
1630 pa
-= hose
->pci_mem_offset
;
1635 /* hmmm, didn't find it */
1640 pci_phys_to_bus(unsigned long pa
, int busnr
)
1642 struct pci_controller
* hose
= pci_bus_to_hose(busnr
);
1645 return pa
- hose
->pci_mem_offset
;
1649 pci_bus_to_phys(unsigned int ba
, int busnr
)
1651 struct pci_controller
* hose
= pci_bus_to_hose(busnr
);
1654 return ba
+ hose
->pci_mem_offset
;
1657 /* Provide information on locations of various I/O regions in physical
1658 * memory. Do this on a per-card basis so that we choose the right
1660 * Note that the returned IO or memory base is a physical address
1663 long sys_pciconfig_iobase(long which
, unsigned long bus
, unsigned long devfn
)
1665 struct pci_controller
* hose
;
1666 long result
= -EOPNOTSUPP
;
1668 /* Argh ! Please forgive me for that hack, but that's the
1669 * simplest way to get existing XFree to not lockup on some
1670 * G5 machines... So when something asks for bus 0 io base
1671 * (bus 0 is HT root), we return the AGP one instead.
1673 #ifdef CONFIG_PPC_PMAC
1674 if (_machine
== _MACH_Pmac
&& machine_is_compatible("MacRISC4"))
1677 #endif /* CONFIG_PPC_PMAC */
1679 hose
= pci_bus_to_hose(bus
);
1684 case IOBASE_BRIDGE_NUMBER
:
1685 return (long)hose
->first_busno
;
1687 return (long)hose
->pci_mem_offset
;
1689 return (long)hose
->io_base_phys
;
1691 return (long)isa_io_base
;
1692 case IOBASE_ISA_MEM
:
1693 return (long)isa_mem_base
;
1700 pci_init_resource(struct resource
*res
, unsigned long start
, unsigned long end
,
1701 int flags
, char *name
)
1708 res
->sibling
= NULL
;
1712 void __iomem
*pci_iomap(struct pci_dev
*dev
, int bar
, unsigned long max
)
1714 unsigned long start
= pci_resource_start(dev
, bar
);
1715 unsigned long len
= pci_resource_len(dev
, bar
);
1716 unsigned long flags
= pci_resource_flags(dev
, bar
);
1720 if (max
&& len
> max
)
1722 if (flags
& IORESOURCE_IO
)
1723 return ioport_map(start
, len
);
1724 if (flags
& IORESOURCE_MEM
)
1725 return (void __iomem
*) start
;
1730 void pci_iounmap(struct pci_dev
*dev
, void __iomem
*addr
)
1734 EXPORT_SYMBOL(pci_iomap
);
1735 EXPORT_SYMBOL(pci_iounmap
);
1739 * Null PCI config access functions, for the case when we can't
1742 #define NULL_PCI_OP(rw, size, type) \
1744 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1746 return PCIBIOS_DEVICE_NOT_FOUND; \
1750 null_read_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1753 return PCIBIOS_DEVICE_NOT_FOUND
;
1757 null_write_config(struct pci_bus
*bus
, unsigned int devfn
, int offset
,
1760 return PCIBIOS_DEVICE_NOT_FOUND
;
1763 static struct pci_ops null_pci_ops
=
1770 * These functions are used early on before PCI scanning is done
1771 * and all of the pci_dev and pci_bus structures have been created.
1773 static struct pci_bus
*
1774 fake_pci_bus(struct pci_controller
*hose
, int busnr
)
1776 static struct pci_bus bus
;
1779 hose
= pci_bus_to_hose(busnr
);
1781 printk(KERN_ERR
"Can't find hose for PCI bus %d!\n", busnr
);
1785 bus
.ops
= hose
? hose
->ops
: &null_pci_ops
;
1789 #define EARLY_PCI_OP(rw, size, type) \
1790 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1791 int devfn, int offset, type value) \
1793 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1794 devfn, offset, value); \
1797 EARLY_PCI_OP(read
, byte
, u8
*)
1798 EARLY_PCI_OP(read
, word
, u16
*)
1799 EARLY_PCI_OP(read
, dword
, u32
*)
1800 EARLY_PCI_OP(write
, byte
, u8
)
1801 EARLY_PCI_OP(write
, word
, u16
)
1802 EARLY_PCI_OP(write
, dword
, u32
)