arch/parisc/kernel/perf.c

   1 /*
   2  *  Parisc performance counters
   3  *  Copyright (C) 2001 Randolph Chung <tausq@debian.org>
   4  *
   5  *  This code is derived, with permission, from HP/UX sources.
   6  *
   7  *    This program is free software; you can redistribute it and/or modify
   8  *    it under the terms of the GNU General Public License as published by
   9  *    the Free Software Foundation; either version 2, or (at your option)
  10  *    any later version.
  11  *
  12  *    This program is distributed in the hope that it will be useful,
  13  *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  *    GNU General Public License for more details.
  16  *
  17  *    You should have received a copy of the GNU General Public License
  18  *    along with this program; if not, write to the Free Software
  19  *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20  */
  21
  22 /*
  23  *  Edited comment from original sources:
  24  *
  25  *  This driver programs the PCX-U/PCX-W performance counters
  26  *  on the PA-RISC 2.0 chips.  The driver keeps all images now
  27  *  internally to the kernel to hopefully eliminate the possiblity
  28  *  of a bad image halting the CPU.  Also, there are different
  29  *  images for the PCX-W and later chips vs the PCX-U chips.
  30  *
  31  *  Only 1 process is allowed to access the driver at any time,
  32  *  so the only protection that is needed is at open and close.
  33  *  A variable "perf_enabled" is used to hold the state of the
  34  *  driver.  The spinlock "perf_lock" is used to protect the
  35  *  modification of the state during open/close operations so
  36  *  multiple processes don't get into the driver simultaneously.
  37  *
  38  *  This driver accesses the processor directly vs going through
  39  *  the PDC INTRIGUE calls.  This is done to eliminate bugs introduced
  40  *  in various PDC revisions.  The code is much more maintainable
  41  *  and reliable this way vs having to debug on every version of PDC
  42  *  on every box.
  43  */
  44
  45 #include <linux/config.h>
  46 #include <linux/init.h>
  47 #include <linux/proc_fs.h>
  48 #include <linux/miscdevice.h>
  49 #include <linux/spinlock.h>
  50
  51 #include <asm/uaccess.h>
  52 #include <asm/perf.h>
  53 #include <asm/parisc-device.h>
  54 #include <asm/processor.h>
  55 #include <asm/runway.h>
  56 #include <asm/io.h>             /* for __raw_read() */
  57
  58 #include "perf_images.h"
  59
  60 #define MAX_RDR_WORDS   24
  61 #define PERF_VERSION    2       /* derived from hpux's PI v2 interface */
  62
  63 /* definition of RDR regs */
  64 struct rdr_tbl_ent {
  65         uint16_t        width;
  66         uint8_t         num_words;
  67         uint8_t         write_control;
  68 };
  69
  70 static int perf_processor_interface = UNKNOWN_INTF;
  71 static int perf_enabled = 0;
  72 static spinlock_t perf_lock;
  73 struct parisc_device *cpu_device = NULL;
  74
  75 /* RDRs to write for PCX-W */
  76 static int perf_rdrs_W[] =
  77         { 0, 1, 4, 5, 6, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
  78
  79 /* RDRs to write for PCX-U */
  80 static int perf_rdrs_U[] =
  81         { 0, 1, 4, 5, 6, 7, 16, 17, 18, 20, 21, 22, 23, 24, 25, -1 };
  82
  83 /* RDR register descriptions for PCX-W */
  84 static struct rdr_tbl_ent perf_rdr_tbl_W[] = {
  85         { 19,   1,      8 },   /* RDR 0 */
  86         { 16,   1,      16 },  /* RDR 1 */
  87         { 72,   2,      0 },   /* RDR 2 */
  88         { 81,   2,      0 },   /* RDR 3 */
  89         { 328,  6,      0 },   /* RDR 4 */
  90         { 160,  3,      0 },   /* RDR 5 */
  91         { 336,  6,      0 },   /* RDR 6 */
  92         { 164,  3,      0 },   /* RDR 7 */
  93         { 0,    0,      0 },   /* RDR 8 */
  94         { 35,   1,      0 },   /* RDR 9 */
  95         { 6,    1,      0 },   /* RDR 10 */
  96         { 18,   1,      0 },   /* RDR 11 */
  97         { 13,   1,      0 },   /* RDR 12 */
  98         { 8,    1,      0 },   /* RDR 13 */
  99         { 8,    1,      0 },   /* RDR 14 */
 100         { 8,    1,      0 },   /* RDR 15 */
 101         { 1530, 24,     0 },   /* RDR 16 */
 102         { 16,   1,      0 },   /* RDR 17 */
 103         { 4,    1,      0 },   /* RDR 18 */
 104         { 0,    0,      0 },   /* RDR 19 */
 105         { 152,  3,      24 },  /* RDR 20 */
 106         { 152,  3,      24 },  /* RDR 21 */
 107         { 233,  4,      48 },  /* RDR 22 */
 108         { 233,  4,      48 },  /* RDR 23 */
 109         { 71,   2,      0 },   /* RDR 24 */
 110         { 71,   2,      0 },   /* RDR 25 */
 111         { 11,   1,      0 },   /* RDR 26 */
 112         { 18,   1,      0 },   /* RDR 27 */
 113         { 128,  2,      0 },   /* RDR 28 */
 114         { 0,    0,      0 },   /* RDR 29 */
 115         { 16,   1,      0 },   /* RDR 30 */
 116         { 16,   1,      0 },   /* RDR 31 */
 117 };
 118
 119 /* RDR register descriptions for PCX-U */
 120 static struct rdr_tbl_ent perf_rdr_tbl_U[] = {
 121         { 19,   1,      8 },              /* RDR 0 */
 122         { 32,   1,      16 },             /* RDR 1 */
 123         { 20,   1,      0 },              /* RDR 2 */
 124         { 0,    0,      0 },              /* RDR 3 */
 125         { 344,  6,      0 },              /* RDR 4 */
 126         { 176,  3,      0 },              /* RDR 5 */
 127         { 336,  6,      0 },              /* RDR 6 */
 128         { 0,    0,      0 },              /* RDR 7 */
 129         { 0,    0,      0 },              /* RDR 8 */
 130         { 0,    0,      0 },              /* RDR 9 */
 131         { 28,   1,      0 },              /* RDR 10 */
 132         { 33,   1,      0 },              /* RDR 11 */
 133         { 0,    0,      0 },              /* RDR 12 */
 134         { 230,  4,      0 },              /* RDR 13 */
 135         { 32,   1,      0 },              /* RDR 14 */
 136         { 128,  2,      0 },              /* RDR 15 */
 137         { 1494, 24,     0 },              /* RDR 16 */
 138         { 18,   1,      0 },              /* RDR 17 */
 139         { 4,    1,      0 },              /* RDR 18 */
 140         { 0,    0,      0 },              /* RDR 19 */
 141         { 158,  3,      24 },             /* RDR 20 */
 142         { 158,  3,      24 },             /* RDR 21 */
 143         { 194,  4,      48 },             /* RDR 22 */
 144         { 194,  4,      48 },             /* RDR 23 */
 145         { 71,   2,      0 },              /* RDR 24 */
 146         { 71,   2,      0 },              /* RDR 25 */
 147         { 28,   1,      0 },              /* RDR 26 */
 148         { 33,   1,      0 },              /* RDR 27 */
 149         { 88,   2,      0 },              /* RDR 28 */
 150         { 32,   1,      0 },              /* RDR 29 */
 151         { 24,   1,      0 },              /* RDR 30 */
 152         { 16,   1,      0 },              /* RDR 31 */
 153 };
 154
 155 /*
 156  * A non-zero write_control in the above tables is a byte offset into
 157  * this array.
 158  */
 159 static uint64_t perf_bitmasks[] = {
 160         0x0000000000000000,     /* first dbl word must be zero */
 161         0xfdffe00000000000,     /* RDR0 bitmask */
 162         0x003f000000000000,     /* RDR1 bitmask */
 163         0x00ffffffffffffff,     /* RDR20-RDR21 bitmask (152 bits) */
 164         0xffffffffffffffff,
 165         0xfffffffc00000000,
 166         0xffffffffffffffff,     /* RDR22-RDR23 bitmask (233 bits) */
 167         0xffffffffffffffff,
 168         0xfffffffffffffffc,
 169         0xff00000000000000
 170 };
 171
 172 /*
 173  * Write control bitmasks for Pa-8700 processor given
 174  * somethings have changed slightly.
 175  */
 176 static uint64_t perf_bitmasks_piranha[] = {
 177         0x0000000000000000,     /* first dbl word must be zero */
 178         0xfdffe00000000000,     /* RDR0 bitmask */
 179         0x003f000000000000,     /* RDR1 bitmask */
 180         0x00ffffffffffffff,     /* RDR20-RDR21 bitmask (158 bits) */
 181         0xffffffffffffffff,
 182         0xfffffffc00000000,
 183         0xffffffffffffffff,     /* RDR22-RDR23 bitmask (210 bits) */
 184         0xffffffffffffffff,
 185         0xffffffffffffffff,
 186         0xfffc000000000000
 187 };
 188
 189 static uint64_t *bitmask_array;   /* array of bitmasks to use */
 190
 191 /******************************************************************************
 192  * Function Prototypes
 193  *****************************************************************************/
 194 static int perf_config(uint32_t *image_ptr);
 195 static int perf_release(struct inode *inode, struct file *file);
 196 static int perf_open(struct inode *inode, struct file *file);
 197 static ssize_t perf_read(struct file *file, char *buf, size_t cnt, loff_t *ppos);
 198 static ssize_t perf_write(struct file *file, const char *buf, size_t count,
 199         loff_t *ppos);
 200 static int perf_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 201         unsigned long arg);
 202 static void perf_start_counters(void);
 203 static int perf_stop_counters(uint32_t *raddr);
 204 static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num);
 205 static int perf_rdr_read_ubuf(uint32_t  rdr_num, uint64_t *buffer);
 206 static int perf_rdr_clear(uint32_t rdr_num);
 207 static int perf_write_image(uint64_t *memaddr);
 208 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer);
 209
 210 /* External Assembly Routines */
 211 extern uint64_t perf_rdr_shift_in_W (uint32_t rdr_num, uint16_t width);
 212 extern uint64_t perf_rdr_shift_in_U (uint32_t rdr_num, uint16_t width);
 213 extern void perf_rdr_shift_out_W (uint32_t rdr_num, uint64_t buffer);
 214 extern void perf_rdr_shift_out_U (uint32_t rdr_num, uint64_t buffer);
 215 extern void perf_intrigue_enable_perf_counters (void);
 216 extern void perf_intrigue_disable_perf_counters (void);
 217
 218 /******************************************************************************
 219  * Function Definitions
 220  *****************************************************************************/
 221
 222
 223 /*
 224  * configure:
 225  *
 226  * Configure the cpu with a given data image.  First turn off the counters,
 227  * then download the image, then turn the counters back on.
 228  */
 229 static int perf_config(uint32_t *image_ptr)
 230 {
 231         long error;
 232         uint32_t raddr[4];
 233
 234         /* Stop the counters*/
 235         error = perf_stop_counters(raddr);
 236         if (error != 0) {
 237                 printk("perf_config: perf_stop_counters = %ld\n", error);
 238                 return -EINVAL;
 239         }
 240
 241 printk("Preparing to write image\n");
 242         /* Write the image to the chip */
 243         error = perf_write_image((uint64_t *)image_ptr);
 244         if (error != 0) {
 245                 printk("perf_config: DOWNLOAD = %ld\n", error);
 246                 return -EINVAL;
 247         }
 248
 249 printk("Preparing to start counters\n");
 250
 251         /* Start the counters */
 252         perf_start_counters();
 253
 254         return sizeof(uint32_t);
 255 }
 256
 257 /*
 258  * Open the device and initialize all of its memory.  The device is only
 259  * opened once, but can be "queried" by multiple processes that know its
 260  * file descriptor.
 261  */
 262 static int perf_open(struct inode *inode, struct file *file)
 263 {
 264         spin_lock(&perf_lock);
 265         if (perf_enabled) {
 266                 spin_unlock(&perf_lock);
 267                 return -EBUSY;
 268         }
 269         perf_enabled = 1;
 270         spin_unlock(&perf_lock);
 271
 272         return 0;
 273 }
 274
 275 /*
 276  * Close the device.
 277  */
 278 static int perf_release(struct inode *inode, struct file *file)
 279 {
 280         spin_lock(&perf_lock);
 281         perf_enabled = 0;
 282         spin_unlock(&perf_lock);
 283
 284         return 0;
 285 }
 286
 287 /*
 288  * Read does nothing for this driver
 289  */
 290 static ssize_t perf_read(struct file *file, char *buf, size_t cnt, loff_t *ppos)
 291 {
 292         return 0;
 293 }
 294
 295 /*
 296  * write:
 297  *
 298  * This routine downloads the image to the chip.  It must be
 299  * called on the processor that the download should happen
 300  * on.
 301  */
 302 static ssize_t perf_write(struct file *file, const char *buf, size_t count,
 303         loff_t *ppos)
 304 {
 305         int err;
 306         size_t image_size;
 307         uint32_t image_type;
 308         uint32_t interface_type;
 309         uint32_t test;
 310
 311         if (perf_processor_interface == ONYX_INTF)
 312                 image_size = PCXU_IMAGE_SIZE;
 313         else if (perf_processor_interface == CUDA_INTF)
 314                 image_size = PCXW_IMAGE_SIZE;
 315         else
 316                 return -EFAULT;
 317
 318         if (!capable(CAP_SYS_ADMIN))
 319                 return -EACCES;
 320
 321         if (count != sizeof(uint32_t))
 322                 return -EIO;
 323
 324         if ((err = copy_from_user(&image_type, buf, sizeof(uint32_t))) != 0)
 325                 return err;
 326
 327         /* Get the interface type and test type */
 328         interface_type = (image_type >> 16) & 0xffff;
 329         test           = (image_type & 0xffff);
 330
 331         /* Make sure everything makes sense */
 332
 333         /* First check the machine type is correct for
 334            the requested image */
 335         if (((perf_processor_interface == CUDA_INTF) &&
 336                        (interface_type != CUDA_INTF)) ||
 337             ((perf_processor_interface == ONYX_INTF) &&
 338                        (interface_type != ONYX_INTF)))
 339                 return -EINVAL;
 340
 341         /* Next check to make sure the requested image
 342            is valid */
 343         if (((interface_type == CUDA_INTF) &&
 344                        (test >= MAX_CUDA_IMAGES)) ||
 345             ((interface_type == ONYX_INTF) &&
 346                        (test >= MAX_ONYX_IMAGES)))
 347                 return -EINVAL;
 348
 349         /* Copy the image into the processor */
 350         if (interface_type == CUDA_INTF)
 351                 return perf_config(cuda_images[test]);
 352         else
 353                 return perf_config(onyx_images[test]);
 354
 355         return count;
 356 }
 357
 358 /*
 359  * Patch the images that need to know the IVA addresses.
 360  */
 361 static void perf_patch_images(void)
 362 {
 363 #if 0 /* FIXME!! */
 364 /*
 365  * NOTE:  this routine is VERY specific to the current TLB image.
 366  * If the image is changed, this routine might also need to be changed.
 367  */
 368         extern void $i_itlb_miss_2_0();
 369         extern void $i_dtlb_miss_2_0();
 370         extern void PA2_0_iva();
 371
 372         /*
 373          * We can only use the lower 32-bits, the upper 32-bits should be 0
 374          * anyway given this is in the kernel
 375          */
 376         uint32_t itlb_addr  = (uint32_t)&($i_itlb_miss_2_0);
 377         uint32_t dtlb_addr  = (uint32_t)&($i_dtlb_miss_2_0);
 378         uint32_t IVAaddress = (uint32_t)&PA2_0_iva;
 379
 380         if (perf_processor_interface == ONYX_INTF) {
 381                 /* clear last 2 bytes */
 382                 onyx_images[TLBMISS][15] &= 0xffffff00;
 383                 /* set 2 bytes */
 384                 onyx_images[TLBMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
 385                 onyx_images[TLBMISS][16] = (dtlb_addr << 8)&0xffffff00;
 386                 onyx_images[TLBMISS][17] = itlb_addr;
 387
 388                 /* clear last 2 bytes */
 389                 onyx_images[TLBHANDMISS][15] &= 0xffffff00;
 390                 /* set 2 bytes */
 391                 onyx_images[TLBHANDMISS][15] |= (0x000000ff&((dtlb_addr) >> 24));
 392                 onyx_images[TLBHANDMISS][16] = (dtlb_addr << 8)&0xffffff00;
 393                 onyx_images[TLBHANDMISS][17] = itlb_addr;
 394
 395                 /* clear last 2 bytes */
 396                 onyx_images[BIG_CPI][15] &= 0xffffff00;
 397                 /* set 2 bytes */
 398                 onyx_images[BIG_CPI][15] |= (0x000000ff&((dtlb_addr) >> 24));
 399                 onyx_images[BIG_CPI][16] = (dtlb_addr << 8)&0xffffff00;
 400                 onyx_images[BIG_CPI][17] = itlb_addr;
 401
 402             onyx_images[PANIC][15] &= 0xffffff00;  /* clear last 2 bytes */
 403                 onyx_images[PANIC][15] |= (0x000000ff&((IVAaddress) >> 24)); /* set 2 bytes */
 404                 onyx_images[PANIC][16] = (IVAaddress << 8)&0xffffff00;
 405
 406
 407         } else if (perf_processor_interface == CUDA_INTF) {
 408                 /* Cuda interface */
 409                 cuda_images[TLBMISS][16] =
 410                         (cuda_images[TLBMISS][16]&0xffff0000) |
 411                         ((dtlb_addr >> 8)&0x0000ffff);
 412                 cuda_images[TLBMISS][17] =
 413                         ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
 414                 cuda_images[TLBMISS][18] = (itlb_addr << 16)&0xffff0000;
 415
 416                 cuda_images[TLBHANDMISS][16] =
 417                         (cuda_images[TLBHANDMISS][16]&0xffff0000) |
 418                         ((dtlb_addr >> 8)&0x0000ffff);
 419                 cuda_images[TLBHANDMISS][17] =
 420                         ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
 421                 cuda_images[TLBHANDMISS][18] = (itlb_addr << 16)&0xffff0000;
 422
 423                 cuda_images[BIG_CPI][16] =
 424                         (cuda_images[BIG_CPI][16]&0xffff0000) |
 425                         ((dtlb_addr >> 8)&0x0000ffff);
 426                 cuda_images[BIG_CPI][17] =
 427                         ((dtlb_addr << 24)&0xff000000) | ((itlb_addr >> 16)&0x000000ff);
 428                 cuda_images[BIG_CPI][18] = (itlb_addr << 16)&0xffff0000;
 429         } else {
 430                 /* Unknown type */
 431         }
 432 #endif
 433 }
 434
 435
 436 /*
 437  * ioctl routine
 438  * All routines effect the processor that they are executed on.  Thus you
 439  * must be running on the processor that you wish to change.
 440  */
 441
 442 static int perf_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 443         unsigned long arg)
 444 {
 445         long error_start;
 446         uint32_t raddr[4];
 447
 448         switch (cmd) {
 449
 450             case PA_PERF_ON:
 451                         /* Start the counters */
 452                         perf_start_counters();
 453                         return 0;
 454
 455             case PA_PERF_OFF:
 456                         error_start = perf_stop_counters(raddr);
 457                         if (error_start != 0) {
 458                                 printk(KERN_ERR "perf_off: perf_stop_counters = %ld\n", error_start);
 459                                 return -EFAULT;
 460                         }
 461
 462                         /* copy out the Counters */
 463                         if (copy_to_user((void *)arg, raddr,
 464                                         sizeof (raddr)) != 0) {
 465                                 return -EFAULT;
 466                         }
 467                         return 0;
 468
 469             case PA_PERF_VERSION:
 470                         /* Return the version # */
 471                         return put_user(PERF_VERSION, (int *)arg);
 472
 473             default:
 474                         break;
 475         }
 476         return -ENOTTY;
 477 }
 478
 479 static struct file_operations perf_fops = {
 480         .llseek = no_llseek,
 481         .read = perf_read,
 482         .write = perf_write,
 483         .ioctl = perf_ioctl,
 484         .open = perf_open,
 485         .release = perf_release
 486 };
 487
 488 static struct miscdevice perf_dev = {
 489         MISC_DYNAMIC_MINOR,
 490         PA_PERF_DEV,
 491         &perf_fops
 492 };
 493
 494 /*
 495  * Initialize the module
 496  */
 497 static int __init perf_init(void)
 498 {
 499         int ret;
 500
 501         /* Determine correct processor interface to use */
 502         bitmask_array = perf_bitmasks;
 503
 504         if (boot_cpu_data.cpu_type == pcxu ||
 505             boot_cpu_data.cpu_type == pcxu_) {
 506                 perf_processor_interface = ONYX_INTF;
 507         } else if (boot_cpu_data.cpu_type == pcxw ||
 508                  boot_cpu_data.cpu_type == pcxw_ ||
 509                  boot_cpu_data.cpu_type == pcxw2 ||
 510                  boot_cpu_data.cpu_type == mako) {
 511                 perf_processor_interface = CUDA_INTF;
 512                 if (boot_cpu_data.cpu_type == pcxw2 ||
 513                     boot_cpu_data.cpu_type == mako)
 514                         bitmask_array = perf_bitmasks_piranha;
 515         } else {
 516                 perf_processor_interface = UNKNOWN_INTF;
 517                 printk("Performance monitoring counters not supported on this processor\n");
 518                 return -ENODEV;
 519         }
 520
 521         ret = misc_register(&perf_dev);
 522         if (ret) {
 523                 printk(KERN_ERR "Performance monitoring counters: "
 524                         "cannot register misc device.\n");
 525                 return ret;
 526         }
 527
 528         /* Patch the images to match the system */
 529         perf_patch_images();
 530
 531         spin_lock_init(&perf_lock);
 532
 533         /* TODO: this only lets us access the first cpu.. what to do for SMP? */
 534         cpu_device = cpu_data[0].dev;
 535         printk("Performance monitoring counters enabled for %s\n",
 536                 cpu_data[0].dev->name);
 537
 538         return 0;
 539 }
 540
 541 /*
 542  * perf_start_counters(void)
 543  *
 544  * Start the counters.
 545  */
 546 static void perf_start_counters(void)
 547 {
 548         /* Enable performance monitor counters */
 549         perf_intrigue_enable_perf_counters();
 550 }
 551
 552 /*
 553  * perf_stop_counters
 554  *
 555  * Stop the performance counters and save counts
 556  * in a per_processor array.
 557  */
 558 static int perf_stop_counters(uint32_t *raddr)
 559 {
 560         uint64_t userbuf[MAX_RDR_WORDS];
 561
 562         /* Disable performance counters */
 563         perf_intrigue_disable_perf_counters();
 564
 565         if (perf_processor_interface == ONYX_INTF) {
 566                 uint64_t tmp64;
 567                 /*
 568                  * Read the counters
 569                  */
 570                 if (!perf_rdr_read_ubuf(16, userbuf))
 571                         return -13;
 572
 573                 /* Counter0 is bits 1398 thru 1429 */
 574                 tmp64 =  (userbuf[21] << 22) & 0x00000000ffc00000;
 575                 tmp64 |= (userbuf[22] >> 42) & 0x00000000003fffff;
 576                 /* OR sticky0 (bit 1430) to counter0 bit 32 */
 577                 tmp64 |= (userbuf[22] >> 10) & 0x0000000080000000;
 578                 raddr[0] = (uint32_t)tmp64;
 579
 580                 /* Counter1 is bits 1431 thru 1462 */
 581                 tmp64 =  (userbuf[22] >> 9) & 0x00000000ffffffff;
 582                 /* OR sticky1 (bit 1463) to counter1 bit 32 */
 583                 tmp64 |= (userbuf[22] << 23) & 0x0000000080000000;
 584                 raddr[1] = (uint32_t)tmp64;
 585
 586                 /* Counter2 is bits 1464 thru 1495 */
 587                 tmp64 =  (userbuf[22] << 24) & 0x00000000ff000000;
 588                 tmp64 |= (userbuf[23] >> 40) & 0x0000000000ffffff;
 589                 /* OR sticky2 (bit 1496) to counter2 bit 32 */
 590                 tmp64 |= (userbuf[23] >> 8) & 0x0000000080000000;
 591                 raddr[2] = (uint32_t)tmp64;
 592
 593                 /* Counter3 is bits 1497 thru 1528 */
 594                 tmp64 =  (userbuf[23] >> 7) & 0x00000000ffffffff;
 595                 /* OR sticky3 (bit 1529) to counter3 bit 32 */
 596                 tmp64 |= (userbuf[23] << 25) & 0x0000000080000000;
 597                 raddr[3] = (uint32_t)tmp64;
 598
 599                 /*
 600                  * Zero out the counters
 601                  */
 602
 603                 /*
 604                  * The counters and sticky-bits comprise the last 132 bits
 605                  * (1398 - 1529) of RDR16 on a U chip.  We'll zero these
 606                  * out the easy way: zero out last 10 bits of dword 21,
 607                  * all of dword 22 and 58 bits (plus 6 don't care bits) of
 608                  * dword 23.
 609                  */
 610                 userbuf[21] &= 0xfffffffffffffc00;      /* 0 to last 10 bits */
 611                 userbuf[22] = 0;
 612                 userbuf[23] = 0;
 613
 614                 /*
 615                  * Write back the zero'ed bytes + the image given
 616                  * the read was destructive.
 617                  */
 618                 perf_rdr_write(16, userbuf);
 619         } else {
 620
 621                 /*
 622                  * Read RDR-15 which contains the counters and sticky bits
 623                  */
 624                 if (!perf_rdr_read_ubuf(15, userbuf)) {
 625                         return -13;
 626                 }
 627
 628                 /*
 629                  * Clear out the counters
 630                  */
 631                 perf_rdr_clear(15);
 632
 633                 /*
 634                  * Copy the counters
 635                  */
 636                 raddr[0] = (uint32_t)((userbuf[0] >> 32) & 0x00000000ffffffffUL);
 637                 raddr[1] = (uint32_t)(userbuf[0] & 0x00000000ffffffffUL);
 638                 raddr[2] = (uint32_t)((userbuf[1] >> 32) & 0x00000000ffffffffUL);
 639                 raddr[3] = (uint32_t)(userbuf[1] & 0x00000000ffffffffUL);
 640         }
 641
 642         return 0;
 643 }
 644
 645 /*
 646  * perf_rdr_get_entry
 647  *
 648  * Retrieve a pointer to the description of what this
 649  * RDR contains.
 650  */
 651 static struct rdr_tbl_ent * perf_rdr_get_entry(uint32_t rdr_num)
 652 {
 653         if (perf_processor_interface == ONYX_INTF) {
 654                 return &perf_rdr_tbl_U[rdr_num];
 655         } else {
 656                 return &perf_rdr_tbl_W[rdr_num];
 657         }
 658 }
 659
 660 /*
 661  * perf_rdr_read_ubuf
 662  *
 663  * Read the RDR value into the buffer specified.
 664  */
 665 static int perf_rdr_read_ubuf(uint32_t  rdr_num, uint64_t *buffer)
 666 {
 667         uint64_t        data, data_mask = 0;
 668         uint32_t        width, xbits, i;
 669         struct rdr_tbl_ent *tentry;
 670
 671         tentry = perf_rdr_get_entry(rdr_num);
 672         if ((width = tentry->width) == 0)
 673                 return 0;
 674
 675         /* Clear out buffer */
 676         i = tentry->num_words;
 677         while (i--) {
 678                 buffer[i] = 0;
 679         }
 680
 681         /* Check for bits an even number of 64 */
 682         if ((xbits = width & 0x03f) != 0) {
 683                 data_mask = 1;
 684                 data_mask <<= (64 - xbits);
 685                 data_mask--;
 686         }
 687
 688         /* Grab all of the data */
 689         i = tentry->num_words;
 690         while (i--) {
 691
 692                 if (perf_processor_interface == ONYX_INTF) {
 693                         data = perf_rdr_shift_in_U(rdr_num, width);
 694                 } else {
 695                         data = perf_rdr_shift_in_W(rdr_num, width);
 696                 }
 697                 if (xbits) {
 698                         buffer[i] |= (data << (64 - xbits));
 699                         if (i) {
 700                                 buffer[i-1] |= ((data >> xbits) & data_mask);
 701                         }
 702                 } else {
 703                         buffer[i] = data;
 704                 }
 705         }
 706
 707         return 1;
 708 }
 709
 710 /*
 711  * perf_rdr_clear
 712  *
 713  * Zero out the given RDR register
 714  */
 715 static int perf_rdr_clear(uint32_t      rdr_num)
 716 {
 717         struct rdr_tbl_ent *tentry;
 718         int32_t         i;
 719
 720         tentry = perf_rdr_get_entry(rdr_num);
 721
 722         if (tentry->width == 0) {
 723                 return -1;
 724         }
 725
 726         i = tentry->num_words;
 727         while (i--) {
 728                 if (perf_processor_interface == ONYX_INTF) {
 729                         perf_rdr_shift_out_U(rdr_num, 0UL);
 730                 } else {
 731                         perf_rdr_shift_out_W(rdr_num, 0UL);
 732                 }
 733         }
 734
 735         return 0;
 736 }
 737
 738
 739 /*
 740  * perf_write_image
 741  *
 742  * Write the given image out to the processor
 743  */
 744 static int perf_write_image(uint64_t *memaddr)
 745 {
 746         uint64_t buffer[MAX_RDR_WORDS];
 747         uint64_t *bptr;
 748         uint32_t dwords;
 749         uint32_t *intrigue_rdr;
 750         uint64_t *intrigue_bitmask, tmp64, proc_hpa;
 751         struct rdr_tbl_ent *tentry;
 752         int i;
 753
 754         /* Clear out counters */
 755         if (perf_processor_interface == ONYX_INTF) {
 756
 757                 perf_rdr_clear(16);
 758
 759                 /* Toggle performance monitor */
 760                 perf_intrigue_enable_perf_counters();
 761                 perf_intrigue_disable_perf_counters();
 762
 763                 intrigue_rdr = perf_rdrs_U;
 764         } else {
 765                 perf_rdr_clear(15);
 766                 intrigue_rdr = perf_rdrs_W;
 767         }
 768
 769         /* Write all RDRs */
 770         while (*intrigue_rdr != -1) {
 771                 tentry = perf_rdr_get_entry(*intrigue_rdr);
 772                 perf_rdr_read_ubuf(*intrigue_rdr, buffer);
 773                 bptr   = &buffer[0];
 774                 dwords = tentry->num_words;
 775                 if (tentry->write_control) {
 776                         intrigue_bitmask = &bitmask_array[tentry->write_control >> 3];
 777                         while (dwords--) {
 778                                 tmp64 = *intrigue_bitmask & *memaddr++;
 779                                 tmp64 |= (~(*intrigue_bitmask++)) & *bptr;
 780                                 *bptr++ = tmp64;
 781                         }
 782                 } else {
 783                         while (dwords--) {
 784                                 *bptr++ = *memaddr++;
 785                         }
 786                 }
 787
 788                 perf_rdr_write(*intrigue_rdr, buffer);
 789                 intrigue_rdr++;
 790         }
 791
 792         /*
 793          * Now copy out the Runway stuff which is not in RDRs
 794          */
 795
 796         if (cpu_device == NULL)
 797         {
 798                 printk(KERN_ERR "write_image: cpu_device not yet initialized!\n");
 799                 return -1;
 800         }
 801
 802         proc_hpa = cpu_device->hpa;
 803
 804         /* Merge intrigue bits into Runway STATUS 0 */
 805         tmp64 = __raw_readq(proc_hpa + RUNWAY_STATUS) & 0xffecffffffffffff;
 806         __raw_writeq(tmp64 | (*memaddr++ & 0x0013000000000000), proc_hpa + RUNWAY_STATUS);
 807
 808         /* Write RUNWAY DEBUG registers */
 809         for (i = 0; i < 8; i++) {
 810                 __raw_writeq(*memaddr++, proc_hpa + RUNWAY_DEBUG + i);
 811         }
 812
 813         return 0;
 814 }
 815
 816 /*
 817  * perf_rdr_write
 818  *
 819  * Write the given RDR register with the contents
 820  * of the given buffer.
 821  */
 822 static void perf_rdr_write(uint32_t rdr_num, uint64_t *buffer)
 823 {
 824         struct rdr_tbl_ent *tentry;
 825         int32_t         i;
 826
 827 printk("perf_rdr_write\n");
 828         tentry = perf_rdr_get_entry(rdr_num);
 829         if (tentry->width == 0) { return; }
 830
 831         i = tentry->num_words;
 832         while (i--) {
 833                 if (perf_processor_interface == ONYX_INTF) {
 834                         perf_rdr_shift_out_U(rdr_num, buffer[i]);
 835                 } else {
 836                         perf_rdr_shift_out_W(rdr_num, buffer[i]);
 837                 }
 838         }
 839 printk("perf_rdr_write done\n");
 840 }
 841
 842 module_init(perf_init);