arch/mips/sibyte/sb1250/irq.c

   1 /*
   2  * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18 #include <linux/config.h>
  19 #include <linux/kernel.h>
  20 #include <linux/init.h>
  21 #include <linux/linkage.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/spinlock.h>
  24 #include <linux/smp.h>
  25 #include <linux/mm.h>
  26 #include <linux/slab.h>
  27 #include <linux/kernel_stat.h>
  28
  29 #include <asm/errno.h>
  30 #include <asm/signal.h>
  31 #include <asm/system.h>
  32 #include <asm/ptrace.h>
  33 #include <asm/io.h>
  34
  35 #include <asm/sibyte/sb1250_regs.h>
  36 #include <asm/sibyte/sb1250_int.h>
  37 #include <asm/sibyte/sb1250_uart.h>
  38 #include <asm/sibyte/sb1250_scd.h>
  39 #include <asm/sibyte/sb1250.h>
  40
  41 /*
  42  * These are the routines that handle all the low level interrupt stuff.
  43  * Actions handled here are: initialization of the interrupt map, requesting of
  44  * interrupt lines by handlers, dispatching if interrupts to handlers, probing
  45  * for interrupt lines
  46  */
  47
  48
  49 #define shutdown_sb1250_irq     disable_sb1250_irq
  50 static void end_sb1250_irq(unsigned int irq);
  51 static void enable_sb1250_irq(unsigned int irq);
  52 static void disable_sb1250_irq(unsigned int irq);
  53 static unsigned int startup_sb1250_irq(unsigned int irq);
  54 static void ack_sb1250_irq(unsigned int irq);
  55 #ifdef CONFIG_SMP
  56 static void sb1250_set_affinity(unsigned int irq, unsigned long mask);
  57 #endif
  58
  59 #ifdef CONFIG_SIBYTE_HAS_LDT
  60 extern unsigned long ldt_eoi_space;
  61 #endif
  62
  63 #ifdef CONFIG_KGDB
  64 #include <asm/gdb-stub.h>
  65 extern void breakpoint(void);
  66 static int kgdb_irq;
  67
  68 /* kgdb is on when configured.  Pass "nokgdb" kernel arg to turn it off */
  69 static int kgdb_flag = 1;
  70 static int __init nokgdb(char *str)
  71 {
  72         kgdb_flag = 0;
  73         return 1;
  74 }
  75 __setup("nokgdb", nokgdb);
  76
  77 /* Default to UART1 */
  78 int kgdb_port = 1;
  79 #ifdef CONFIG_SIBYTE_SB1250_DUART
  80 extern char sb1250_duart_present[];
  81 #endif
  82 #endif
  83
  84 static struct hw_interrupt_type sb1250_irq_type = {
  85         "SB1250-IMR",
  86         startup_sb1250_irq,
  87         shutdown_sb1250_irq,
  88         enable_sb1250_irq,
  89         disable_sb1250_irq,
  90         ack_sb1250_irq,
  91         end_sb1250_irq,
  92 #ifdef CONFIG_SMP
  93         sb1250_set_affinity
  94 #else
  95         NULL
  96 #endif
  97 };
  98
  99 /* Store the CPU id (not the logical number) */
 100 int sb1250_irq_owner[SB1250_NR_IRQS];
 101
 102 spinlock_t sb1250_imr_lock = SPIN_LOCK_UNLOCKED;
 103
 104 void sb1250_mask_irq(int cpu, int irq)
 105 {
 106         unsigned long flags;
 107         u64 cur_ints;
 108
 109         spin_lock_irqsave(&sb1250_imr_lock, flags);
 110         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK));
 111         cur_ints |= (((u64) 1) << irq);
 112         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK));
 113         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 114 }
 115
 116 void sb1250_unmask_irq(int cpu, int irq)
 117 {
 118         unsigned long flags;
 119         u64 cur_ints;
 120
 121         spin_lock_irqsave(&sb1250_imr_lock, flags);
 122         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK));
 123         cur_ints &= ~(((u64) 1) << irq);
 124         ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK));
 125         spin_unlock_irqrestore(&sb1250_imr_lock, flags);
 126 }
 127
 128 #ifdef CONFIG_SMP
 129 static void sb1250_set_affinity(unsigned int irq, unsigned long mask)
 130 {
 131         int i = 0, old_cpu, cpu, int_on;
 132         u64 cur_ints;
 133         irq_desc_t *desc = irq_desc + irq;
 134         unsigned long flags;
 135
 136         while (mask) {
 137                 if (mask & 1) {
 138                         mask >>= 1;
 139                         break;
 140                 }
 141                 mask >>= 1;
 142                 i++;
 143         }
 144
 145         if (mask) {
 146                 printk("attempted to set irq affinity for irq %d to multiple CPUs\n", irq);
 147                 return;
 148         }
 149
 150         /* Convert logical CPU to physical CPU */
 151         cpu = cpu_logical_map(i);
 152
 153         /* Protect against other affinity changers and IMR manipulation */
 154         spin_lock_irqsave(&desc->lock, flags);
 155         spin_lock(&sb1250_imr_lock);
 156
 157         /* Swizzle each CPU's IMR (but leave the IP selection alone) */
 158         old_cpu = sb1250_irq_owner[irq];
 159         cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK));
 160         int_on = !(cur_ints & (((u64) 1) << irq));
 161         if (int_on) {
 162                 /* If it was on, mask it */
 163                 cur_ints |= (((u64) 1) << irq);
 164                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(old_cpu) + R_IMR_INTERRUPT_MASK));
 165         }
 166         sb1250_irq_owner[irq] = cpu;
 167         if (int_on) {
 168                 /* unmask for the new CPU */
 169                 cur_ints = ____raw_readq(IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK));
 170                 cur_ints &= ~(((u64) 1) << irq);
 171                 ____raw_writeq(cur_ints, IOADDR(A_IMR_MAPPER(cpu) + R_IMR_INTERRUPT_MASK));
 172         }
 173         spin_unlock(&sb1250_imr_lock);
 174         spin_unlock_irqrestore(&desc->lock, flags);
 175 }
 176 #endif
 177
 178
 179 /* Defined in arch/mips/sibyte/sb1250/irq_handler.S */
 180 extern void sb1250_irq_handler(void);
 181
 182 /*****************************************************************************/
 183
 184 static unsigned int startup_sb1250_irq(unsigned int irq)
 185 {
 186         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 187
 188         return 0;               /* never anything pending */
 189 }
 190
 191
 192 static void disable_sb1250_irq(unsigned int irq)
 193 {
 194         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 195 }
 196
 197 static void enable_sb1250_irq(unsigned int irq)
 198 {
 199         sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 200 }
 201
 202
 203 static void ack_sb1250_irq(unsigned int irq)
 204 {
 205 #ifdef CONFIG_SIBYTE_HAS_LDT
 206         u64 pending;
 207
 208         /*
 209          * If the interrupt was an HT interrupt, now is the time to
 210          * clear it.  NOTE: we assume the HT bridge was set up to
 211          * deliver the interrupts to all CPUs (which makes affinity
 212          * changing easier for us)
 213          */
 214         pending = __raw_readq(IOADDR(A_IMR_REGISTER(sb1250_irq_owner[irq],
 215                                                     R_IMR_LDT_INTERRUPT)));
 216         pending &= ((u64)1 << (irq));
 217         if (pending) {
 218                 int i;
 219                 for (i=0; i<NR_CPUS; i++) {
 220                         int cpu;
 221 #ifdef CONFIG_SMP
 222                         cpu = cpu_logical_map(i);
 223 #else
 224                         cpu = i;
 225 #endif
 226                         /*
 227                          * Clear for all CPUs so an affinity switch
 228                          * doesn't find an old status
 229                          */
 230                         __raw_writeq(pending,
 231                                      IOADDR(A_IMR_REGISTER(cpu, R_IMR_LDT_INTERRUPT_CLR)));
 232                 }
 233
 234                 /*
 235                  * Generate EOI.  For Pass 1 parts, EOI is a nop.  For
 236                  * Pass 2, the LDT world may be edge-triggered, but
 237                  * this EOI shouldn't hurt.  If they are
 238                  * level-sensitive, the EOI is required.
 239                  */
 240                 *(uint32_t *)(ldt_eoi_space+(irq<<16)+(7<<2)) = 0;
 241         }
 242 #endif
 243         sb1250_mask_irq(sb1250_irq_owner[irq], irq);
 244 }
 245
 246
 247 static void end_sb1250_irq(unsigned int irq)
 248 {
 249         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
 250                 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
 251         }
 252 }
 253
 254
 255 void __init init_sb1250_irqs(void)
 256 {
 257         int i;
 258
 259         for (i = 0; i < NR_IRQS; i++) {
 260                 irq_desc[i].status = IRQ_DISABLED;
 261                 irq_desc[i].action = 0;
 262                 irq_desc[i].depth = 1;
 263                 if (i < SB1250_NR_IRQS) {
 264                         irq_desc[i].handler = &sb1250_irq_type;
 265                         sb1250_irq_owner[i] = 0;
 266                 } else {
 267                         irq_desc[i].handler = &no_irq_type;
 268                 }
 269         }
 270 }
 271
 272
 273 static irqreturn_t  sb1250_dummy_handler(int irq, void *dev_id,
 274         struct pt_regs *regs)
 275 {
 276         return IRQ_NONE;
 277 }
 278
 279 static struct irqaction sb1250_dummy_action = {
 280         .handler = sb1250_dummy_handler,
 281         .flags   = 0,
 282         .mask    = CPU_MASK_NONE,
 283         .name    = "sb1250-private",
 284         .next    = NULL,
 285         .dev_id  = 0
 286 };
 287
 288 int sb1250_steal_irq(int irq)
 289 {
 290         irq_desc_t *desc = irq_desc + irq;
 291         unsigned long flags;
 292         int retval = 0;
 293
 294         if (irq >= SB1250_NR_IRQS)
 295                 return -EINVAL;
 296
 297         spin_lock_irqsave(&desc->lock,flags);
 298         /* Don't allow sharing at all for these */
 299         if (desc->action != NULL)
 300                 retval = -EBUSY;
 301         else {
 302                 desc->action = &sb1250_dummy_action;
 303                 desc->depth = 0;
 304         }
 305         spin_unlock_irqrestore(&desc->lock,flags);
 306         return 0;
 307 }
 308
 309 /*
 310  *  init_IRQ is called early in the boot sequence from init/main.c.  It
 311  *  is responsible for setting up the interrupt mapper and installing the
 312  *  handler that will be responsible for dispatching interrupts to the
 313  *  "right" place.
 314  */
 315 /*
 316  * For now, map all interrupts to IP[2].  We could save
 317  * some cycles by parceling out system interrupts to different
 318  * IP lines, but keep it simple for bringup.  We'll also direct
 319  * all interrupts to a single CPU; we should probably route
 320  * PCI and LDT to one cpu and everything else to the other
 321  * to balance the load a bit.
 322  *
 323  * On the second cpu, everything is set to IP5, which is
 324  * ignored, EXCEPT the mailbox interrupt.  That one is
 325  * set to IP[2] so it is handled.  This is needed so we
 326  * can do cross-cpu function calls, as requred by SMP
 327  */
 328
 329 #define IMR_IP2_VAL     K_INT_MAP_I0
 330 #define IMR_IP3_VAL     K_INT_MAP_I1
 331 #define IMR_IP4_VAL     K_INT_MAP_I2
 332 #define IMR_IP5_VAL     K_INT_MAP_I3
 333 #define IMR_IP6_VAL     K_INT_MAP_I4
 334
 335 void __init init_IRQ(void)
 336 {
 337
 338         unsigned int i;
 339         u64 tmp;
 340         unsigned int imask = STATUSF_IP4 | STATUSF_IP3 | STATUSF_IP2 |
 341                 STATUSF_IP1 | STATUSF_IP0;
 342
 343         /* Default everything to IP2 */
 344         for (i = 0; i < SB1250_NR_IRQS; i++) {  /* was I0 */
 345                 __raw_writeq(IMR_IP2_VAL,
 346                              IOADDR(A_IMR_REGISTER(0,
 347                                                    R_IMR_INTERRUPT_MAP_BASE) +
 348                                     (i << 3)));
 349                 __raw_writeq(IMR_IP2_VAL,
 350                              IOADDR(A_IMR_REGISTER(1,
 351                                                     R_IMR_INTERRUPT_MAP_BASE) +
 352                                     (i << 3)));
 353         }
 354
 355         init_sb1250_irqs();
 356
 357         /*
 358          * Map the high 16 bits of the mailbox registers to IP[3], for
 359          * inter-cpu messages
 360          */
 361         /* Was I1 */
 362         __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 363                                          (K_INT_MBOX_0 << 3)));
 364         __raw_writeq(IMR_IP3_VAL, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MAP_BASE) +
 365                                          (K_INT_MBOX_0 << 3)));
 366
 367         /* Clear the mailboxes.  The firmware may leave them dirty */
 368         __raw_writeq(0xffffffffffffffff,
 369                      IOADDR(A_IMR_REGISTER(0, R_IMR_MAILBOX_CLR_CPU)));
 370         __raw_writeq(0xffffffffffffffff,
 371                      IOADDR(A_IMR_REGISTER(1, R_IMR_MAILBOX_CLR_CPU)));
 372
 373         /* Mask everything except the mailbox registers for both cpus */
 374         tmp = ~((u64) 0) ^ (((u64) 1) << K_INT_MBOX_0);
 375         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MASK)));
 376         __raw_writeq(tmp, IOADDR(A_IMR_REGISTER(1, R_IMR_INTERRUPT_MASK)));
 377
 378         sb1250_steal_irq(K_INT_MBOX_0);
 379
 380         /*
 381          * Note that the timer interrupts are also mapped, but this is
 382          * done in sb1250_time_init().  Also, the profiling driver
 383          * does its own management of IP7.
 384          */
 385
 386 #ifdef CONFIG_KGDB
 387         imask |= STATUSF_IP6;
 388 #endif
 389         /* Enable necessary IPs, disable the rest */
 390         change_c0_status(ST0_IM, imask);
 391         set_except_vector(0, sb1250_irq_handler);
 392
 393 #ifdef CONFIG_KGDB
 394         if (kgdb_flag) {
 395                 kgdb_irq = K_INT_UART_0 + kgdb_port;
 396
 397 #ifdef CONFIG_SIBYTE_SB1250_DUART
 398                 sb1250_duart_present[kgdb_port] = 0;
 399 #endif
 400                 /* Setup uart 1 settings, mapper */
 401                 __raw_writeq(M_DUART_IMR_BRK, IOADDR(A_DUART_IMRREG(kgdb_port)));
 402
 403                 sb1250_steal_irq(kgdb_irq);
 404                 __raw_writeq(IMR_IP6_VAL,
 405                              IOADDR(A_IMR_REGISTER(0, R_IMR_INTERRUPT_MAP_BASE) +
 406                                     (kgdb_irq<<3)));
 407                 sb1250_unmask_irq(0, kgdb_irq);
 408
 409                 prom_printf("Waiting for GDB on UART port %d\n", kgdb_port);
 410                 set_debug_traps();
 411                 breakpoint();
 412         }
 413 #endif
 414 }
 415
 416 #ifdef CONFIG_KGDB
 417
 418 #include <linux/delay.h>
 419
 420 #define duart_out(reg, val)     csr_out32(val, IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 421 #define duart_in(reg)           csr_in32(IOADDR(A_DUART_CHANREG(kgdb_port,reg)))
 422
 423 void sb1250_kgdb_interrupt(struct pt_regs *regs)
 424 {
 425         /*
 426          * Clear break-change status (allow some time for the remote
 427          * host to stop the break, since we would see another
 428          * interrupt on the end-of-break too)
 429          */
 430         kstat_this_cpu.irqs[kgdb_irq]++;
 431         mdelay(500);
 432         duart_out(R_DUART_CMD, V_DUART_MISC_CMD_RESET_BREAK_INT |
 433                                 M_DUART_RX_EN | M_DUART_TX_EN);
 434         set_async_breakpoint(&regs->cp0_epc);
 435 }
 436
 437 #endif  /* CONFIG_KGDB */