arch/mips/pci/pci-ocelot-g.c

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 2004 by Ralf Baechle
   7  *
   8  * This doesn't really fly - but I don't have a GT64240 system for testing.
   9  */
  10 #include <linux/init.h>
  11 #include <linux/kernel.h>
  12 #include <linux/types.h>
  13 #include <linux/pci.h>
  14 #include <asm/gt64240.h>
  15 #include <asm/pci_channel.h>
  16
  17 /*
  18  * We assume these address ranges have been programmed into the GT-64240 by
  19  * the firmware.  PMON in case of the Ocelot G does that.  Note the size of
  20  * the I/O range is completly stupid; I/O mappings are limited to at most
  21  * 256 bytes by the PCI spec and deprecated; and just to make things worse
  22  * apparently many devices don't decode more than 64k of I/O space.
  23  */
  24
  25 #define gt_io_size      0x20000000UL
  26 #define gt_io_base      0xe0000000UL
  27
  28 static struct resource gt_pci_mem0_resource = {
  29         .name   = "MV64240 PCI0 MEM",
  30         .start  = 0xc0000000UL,
  31         .end    = 0xcfffffffUL,
  32         .flags  = IORESOURCE_MEM
  33 };
  34
  35 static struct resource gt_pci_io_mem0_resource = {
  36         .name   = "MV64240 PCI0 IO MEM",
  37         .start  = 0xe0000000UL,
  38         .end    = 0xefffffffUL,
  39         .flags  = IORESOURCE_IO
  40 };
  41
  42 static struct mv_pci_controller gt_bus0_controller = {
  43         .pcic = {
  44                 .pci_ops        = &mv_pci_ops,
  45                 .mem_resource   = &gt_pci_mem0_resource,
  46                 .mem_offset     = 0xc0000000UL,
  47                 .io_resource    = &gt_pci_io_mem0_resource,
  48                 .io_offset      = 0x00000000UL
  49         },
  50         .config_addr    = PCI_0CONFIGURATION_ADDRESS,
  51         .config_vreg    = PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
  52 };
  53
  54 static struct resource gt_pci_mem1_resource = {
  55         .name   = "MV64240 PCI1 MEM",
  56         .start  = 0xd0000000UL,
  57         .end    = 0xdfffffffUL,
  58         .flags  = IORESOURCE_MEM
  59 };
  60
  61 static struct resource gt_pci_io_mem1_resource = {
  62         .name   = "MV64240 PCI1 IO MEM",
  63         .start  = 0xf0000000UL,
  64         .end    = 0xffffffffUL,
  65         .flags  = IORESOURCE_IO
  66 };
  67
  68 static struct mv_pci_controller gt_bus1_controller = {
  69         .pcic = {
  70                 .pci_ops        = &mv_pci_ops,
  71                 .mem_resource   = &gt_pci_mem1_resource,
  72                 .mem_offset     = 0xd0000000UL,
  73                 .io_resource    = &gt_pci_io_mem1_resource,
  74                 .io_offset      = 0x10000000UL
  75         },
  76         .config_addr    = PCI_1CONFIGURATION_ADDRESS,
  77         .config_vreg    = PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER,
  78 };
  79
  80 static __init int __init ocelot_g_pci_init(void)
  81 {
  82         unsigned long io_v_base;
  83
  84         if (gt_io_size) {
  85                 io_v_base = (unsigned long) ioremap(gt_io_base, gt_io_size);
  86                 if (!io_v_base)
  87                         panic("Could not ioremap I/O port range");
  88
  89                 set_io_port_base(io_v_base);
  90         }
  91
  92         register_pci_controller(&gt_bus0_controller.pcic);
  93         register_pci_controller(&gt_bus1_controller.pcic);
  94
  95         return 0;
  96 }
  97
  98 arch_initcall(ocelot_g_pci_init);